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GET /api/patches/810430/?format=api
{ "id": 810430, "url": "http://patchwork.ozlabs.org/api/patches/810430/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/patch/20170906080751.6773-3-brendanhiggins@google.com/", "project": { "id": 56, "url": "http://patchwork.ozlabs.org/api/projects/56/?format=api", "name": "OpenBMC development", "link_name": "openbmc", "list_id": "openbmc.lists.ozlabs.org", "list_email": "openbmc@lists.ozlabs.org", "web_url": "http://github.com/openbmc/", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906080751.6773-3-brendanhiggins@google.com>", "list_archive_url": null, "date": "2017-09-06T08:07:50", "name": "[v4,2/3] arm: dts: add Nuvoton NPCM750 device tree", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "560b1edcd80793edc52cf88ed0a665a0a1eec2eb", "submitter": { "id": 69647, "url": "http://patchwork.ozlabs.org/api/people/69647/?format=api", "name": "Brendan Higgins", "email": "brendanhiggins@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/openbmc/patch/20170906080751.6773-3-brendanhiggins@google.com/mbox/", "series": [ { "id": 1714, "url": "http://patchwork.ozlabs.org/api/series/1714/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/list/?series=1714", "date": "2017-09-06T08:07:48", "name": "arm: npcm: add basic support for Nuvoton BMCs", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/1714/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810430/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810430/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Received": [ "from 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linux@armlinux.org.uk,\n\tavifishman70@gmail.com, tmaimon77@gmail.com, raltherr@google.com,\n\tf.fainelli@gmail.com, joel@jms.id.au", "Subject": "[PATCH v4 2/3] arm: dts: add Nuvoton NPCM750 device tree", "Date": "Wed, 6 Sep 2017 01:07:50 -0700", "Message-Id": "<20170906080751.6773-3-brendanhiggins@google.com>", "X-Mailer": "git-send-email 2.14.1.581.gf28d330327-goog", "In-Reply-To": "<20170906080751.6773-1-brendanhiggins@google.com>", "References": "<20170906080751.6773-1-brendanhiggins@google.com>", "X-BeenThere": "openbmc@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Development list for OpenBMC <openbmc.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/openbmc>,\n\t<mailto:openbmc-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/openbmc/>", "List-Post": "<mailto:openbmc@lists.ozlabs.org>", "List-Help": "<mailto:openbmc-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/openbmc>,\n\t<mailto:openbmc-request@lists.ozlabs.org?subject=subscribe>", "Cc": "devicetree@vger.kernel.org, openbmc@lists.ozlabs.org,\n\tBrendan Higgins <brendanhiggins@google.com>,\n\tlinux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org", "Errors-To": "openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"openbmc\"\n\t<openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "Add a common device tree for all Nuvoton NPCM750 BMCs and a board\nspecific device tree for the NPCM750 (Poleg) evaluation board.\n\nSigned-off-by: Brendan Higgins <brendanhiggins@google.com>\nReviewed-by: Tomer Maimon <tmaimon77@gmail.com>\nReviewed-by: Avi Fishman <avifishman70@gmail.com>\nTested-by: Tomer Maimon <tmaimon77@gmail.com>\nTested-by: Avi Fishman <avifishman70@gmail.com>\n---\n .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 +++++\n .../devicetree/bindings/arm/npcm/npcm.txt | 6 +\n arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 57 +++++++\n arch/arm/boot/dts/nuvoton-npcm750.dtsi | 177 +++++++++++++++++++++\n include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 +++++\n 5 files changed, 321 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt\n create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi\n create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h", "diff": "diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\nnew file mode 100644\nindex 000000000000..e81f85b400cf\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n@@ -0,0 +1,42 @@\n+=========================================================\n+Secondary CPU enable-method \"nuvoton,npcm7xx-smp\" binding\n+=========================================================\n+\n+To apply to all CPUs, a single \"nuvoton,npcm7xx-smp\" enable method should be\n+defined in the \"cpus\" node.\n+\n+Enable method name:\t\"nuvoton,npcm7xx-smp\"\n+Compatible machines:\t\"nuvoton,npcm750\"\n+Compatible CPUs:\t\"arm,cortex-a9\"\n+Related properties:\t(none)\n+\n+Note:\n+This enable method needs valid nodes compatible with \"arm,cortex-a9-scu\" and\n+\"nuvoton,npcm750-gcr\".\n+\n+Example:\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tenable-method = \"nuvoton,npcm7xx-smp\";\n+\n+\t\tcpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a9\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n+\t\t\tclock-names = \"clk_cpu\";\n+\t\t\treg = <0>;\n+\t\t\tnext-level-cache = <&L2>;\n+\t\t};\n+\n+\t\tcpu@1 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a9\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n+\t\t\tclock-names = \"clk_cpu\";\n+\t\t\treg = <1>;\n+\t\t\tnext-level-cache = <&L2>;\n+\t\t};\n+\t};\n+\ndiff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\nnew file mode 100644\nindex 000000000000..2d87d9ecea85\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n@@ -0,0 +1,6 @@\n+NPCM Platforms Device Tree Bindings\n+-----------------------------------\n+NPCM750 SoC\n+Required root node properties:\n+\t- compatible = \"nuvoton,npcm750\";\n+\ndiff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\nnew file mode 100644\nindex 000000000000..e54a870d3ee0\n--- /dev/null\n+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n@@ -0,0 +1,57 @@\n+/*\n+ * DTS file for all NPCM750 SoCs\n+ *\n+ * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com>\n+ *\n+ * The code contained herein is licensed under the GNU General Public\n+ * License. You may obtain a copy of the GNU General Public License\n+ * Version 2 or later at the following locations:\n+ *\n+ * http://www.opensource.org/licenses/gpl-license.html\n+ * http://www.gnu.org/copyleft/gpl.html\n+ */\n+\n+/dts-v1/;\n+#include \"nuvoton-npcm750.dtsi\"\n+\n+/ {\n+\tmodel = \"Nuvoton npcm750 Development Board (Device Tree)\";\n+\tcompatible = \"nuvoton,npcm750\";\n+\n+\tchosen {\n+\t\tstdout-path = &serial3;\n+\t\tbootargs = \"earlyprintk=serial,serial3,115200\";\n+\t};\n+\n+\tmemory {\n+\t\treg = <0 0x40000000>;\n+\t};\n+\n+\tcpus {\n+\t\tenable-method = \"nuvoton,npcm7xx-smp\";\n+\t};\n+};\n+\n+&clk {\n+\tstatus = \"okay\";\n+};\n+\n+&watchdog1 {\n+\tstatus = \"okay\";\n+};\n+\n+&serial0 {\n+\tstatus = \"okay\";\n+};\n+\n+&serial1 {\n+\tstatus = \"okay\";\n+};\n+\n+&serial2 {\n+\tstatus = \"okay\";\n+};\n+\n+&serial3 {\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\nnew file mode 100644\nindex 000000000000..bca96b3ae9d3\n--- /dev/null\n+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n@@ -0,0 +1,177 @@\n+/*\n+ * DTSi file for the NPCM750 SoC\n+ *\n+ * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com>\n+ *\n+ * The code contained herein is licensed under the GNU General Public\n+ * License. You may obtain a copy of the GNU General Public License\n+ * Version 2 or later at the following locations:\n+ *\n+ * http://www.opensource.org/licenses/gpl-license.html\n+ * http://www.gnu.org/copyleft/gpl.html\n+ */\n+\n+#include \"skeleton.dtsi\"\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/clock/nuvoton,npcm7xx-clks.h>\n+\n+/ {\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\tinterrupt-parent = <&gic>;\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a9\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n+\t\t\tclock-names = \"clk_cpu\";\n+\t\t\treg = <0>;\n+\t\t\tnext-level-cache = <&l2>;\n+\t\t};\n+\n+\t\tcpu@1 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a9\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n+\t\t\tclock-names = \"clk_cpu\";\n+\t\t\treg = <1>;\n+\t\t\tnext-level-cache = <&l2>;\n+\t\t};\n+\t};\n+\n+\tgcr: gcr@f0800000 {\n+\t\tcompatible = \"nuvoton,npcm750-gcr\", \"syscon\",\n+\t\t\t\"simple-mfd\";\n+\t\treg = <0xf0800000 0x1000>;\n+\t};\n+\n+\tscu: scu@f03fe000 {\n+\t\tcompatible = \"arm,cortex-a9-scu\";\n+\t\treg = <0xf03fe000 0x1000>;\n+\t};\n+\n+\tl2: l2-cache@f03fc000 {\n+\t\tcompatible = \"arm,pl310-cache\";\n+\t\treg = <0xf03fc000 0x1000>;\n+\t\tinterrupts = <0 21 4>;\n+\t\tcache-unified;\n+\t\tcache-level = <2>;\n+\t\tclocks = <&clk NPCM7XX_CLK_AXI>;\n+\t};\n+\n+\tgic: interrupt-controller@f03ff000 {\n+\t\tcompatible = \"arm,cortex-a9-gic\";\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <3>;\n+\t\treg = <0xf03ff000 0x1000>,\n+\t\t <0xf03fe100 0x100>;\n+\t};\n+\n+\tclk: clock-controller@f0801000 {\n+\t\tcompatible = \"nuvoton,npcm750-clk\";\n+\t\t#clock-cells = <1>;\n+\t\treg = <0xf0801000 0x1000>;\n+\t};\n+\n+\t/* external clock signal rg1refck, supplied by the phy */\n+\tclk-rg1refck {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <125000000>;\n+\t};\n+\n+\t/* external clock signal rg2refck, supplied by the phy */\n+\tclk-rg2refck {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <125000000>;\n+\t};\n+\n+\tclk-xin {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <50000000>;\n+\t};\n+\n+\ttimer@f03fe600 {\n+\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n+\t\treg = <0xf03fe600 0x20>;\n+\t\tinterrupts = <1 13 0x304>;\n+\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n+\t};\n+\n+\tapb {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"simple-bus\";\n+\t\tinterrupt-parent = <&gic>;\n+\t\tranges;\n+\n+\t\ttimer0: timer@f0000000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-timer\";\n+\t\t\tinterrupts = <0 32 4>;\n+\t\t\treg = <0xf0000000 0x1000>;\n+\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n+\t\t};\n+\n+\t\twatchdog0: watchdog@f0008000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n+\t\t\tinterrupts = <0 47 4>;\n+\t\t\treg = <0xf0008000 0x1000>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n+\t\t};\n+\n+\t\twatchdog1: watchdog@f0009000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n+\t\t\tinterrupts = <0 48 4>;\n+\t\t\treg = <0xf0009000 0x1000>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n+\t\t};\n+\n+\t\twatchdog2: watchdog@f000a000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n+\t\t\tinterrupts = <0 49 4>;\n+\t\t\treg = <0xf000a000 0x1000>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n+\t\t};\n+\n+\t\tserial0: serial0@f0001000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n+\t\t\treg = <0xf0001000 0x1000>;\n+\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n+\t\t\tinterrupts = <0 2 4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tserial1: serial1@f0002000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n+\t\t\treg = <0xf0002000 0x1000>;\n+\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n+\t\t\tinterrupts = <0 3 4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tserial2: serial2@f0003000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n+\t\t\treg = <0xf0003000 0x1000>;\n+\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n+\t\t\tinterrupts = <0 4 4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tserial3: serial3@f0004000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n+\t\t\treg = <0xf0004000 0x1000>;\n+\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n+\t\t\tinterrupts = <0 5 4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+};\ndiff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\nnew file mode 100644\nindex 000000000000..c69d3bbf7e42\n--- /dev/null\n+++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n@@ -0,0 +1,39 @@\n+/*\n+ * Copyright (C) 2016 Nuvoton Technologies, tali.perry@nuvoton.com\n+ *\n+ * This software is licensed under the terms of the GNU General Public\n+ * License version 2, as published by the Free Software Foundation, and\n+ * may be copied, distributed, and modified under those terms.\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_NPCM7XX_H\n+#define _DT_BINDINGS_CLK_NPCM7XX_H\n+\n+#define NPCM7XX_CLK_PLL0\t0\n+#define NPCM7XX_CLK_PLL1\t1\n+#define NPCM7XX_CLK_PLL2\t2\n+#define NPCM7XX_CLK_GFX\t\t3\n+#define NPCM7XX_CLK_APB1\t4\n+#define NPCM7XX_CLK_APB2\t5\n+#define NPCM7XX_CLK_APB3\t6\n+#define NPCM7XX_CLK_APB4\t7\n+#define NPCM7XX_CLK_APB5\t8\n+#define NPCM7XX_CLK_MC\t\t9\n+#define NPCM7XX_CLK_CPU\t\t10\n+#define NPCM7XX_CLK_SPI0\t11\n+#define NPCM7XX_CLK_SPI3\t12\n+#define NPCM7XX_CLK_SPIX\t13\n+#define NPCM7XX_CLK_UART_CORE\t14\n+#define NPCM7XX_CLK_TIMER\t15\n+#define NPCM7XX_CLK_HOST_UART\t16\n+#define NPCM7XX_CLK_MMC\t\t17\n+#define NPCM7XX_CLK_SDHC\t18\n+#define NPCM7XX_CLK_ADC\t\t19\n+#define NPCM7XX_CLK_GFX_MEM\t20\n+#define NPCM7XX_CLK_USB_BRIDGE\t21\n+#define NPCM7XX_CLK_AXI\t\t22\n+#define NPCM7XX_CLK_AHB\t\t23\n+#define NPCM7XX_CLK_EMC\t\t24\n+#define NPCM7XX_CLK_GMAC\t25\n+\n+#endif\n", "prefixes": [ "v4", "2/3" ] }