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GET /api/patches/810358/?format=api
{ "id": 810358, "url": "http://patchwork.ozlabs.org/api/patches/810358/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170906014950.132960-3-sjg@chromium.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906014950.132960-3-sjg@chromium.org>", "list_archive_url": null, "date": "2017-09-06T01:49:46", "name": "[U-Boot,v3,2/6] dm: x86: Allow TSC timer to be used before DM is ready", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "f0cb1ba39de16ad6b52c3f5274816a44039956c8", "submitter": { "id": 6170, "url": "http://patchwork.ozlabs.org/api/people/6170/?format=api", "name": "Simon Glass", "email": "sjg@chromium.org" }, "delegate": { "id": 56520, "url": "http://patchwork.ozlabs.org/api/users/56520/?format=api", "username": "bmeng", "first_name": "Bin", "last_name": "Meng", "email": "bmeng.cn@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170906014950.132960-3-sjg@chromium.org/mbox/", "series": [ { "id": 1680, "url": "http://patchwork.ozlabs.org/api/series/1680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1680", "date": "2017-09-06T01:49:44", "name": "x86: bootstage: Fix bootstage operation on link", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/1680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810358/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810358/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=google.com header.i=@google.com\n\theader.b=\"nPxz22xZ\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xn64s4YNFz9sNq\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 6 Sep 2017 11:51:25 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 5DC46C21DBC; Wed, 6 Sep 2017 01:50:23 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id CAA30C21E8E;\n\tWed, 6 Sep 2017 01:50:21 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 60047C21DB9; Wed, 6 Sep 2017 01:50:17 +0000 (UTC)", "from mail-oi0-f53.google.com (mail-oi0-f53.google.com\n\t[209.85.218.53])\n\tby lists.denx.de (Postfix) with ESMTPS id 18665C21D75\n\tfor <u-boot@lists.denx.de>; Wed, 6 Sep 2017 01:50:17 +0000 (UTC)", "by mail-oi0-f53.google.com with SMTP id n18so34507229oig.2\n\tfor <u-boot@lists.denx.de>; Tue, 05 Sep 2017 18:50:17 -0700 (PDT)", "from kiwi.bld.corp.google.com ([100.101.164.89])\n\tby smtp.gmail.com with ESMTPSA id\n\tb186sm1908434oia.31.2017.09.05.18.50.12\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 05 Sep 2017 18:50:12 -0700 (PDT)", "by kiwi.bld.corp.google.com (Postfix, from userid 121222)\n\tid E8BA01406E0; Tue, 5 Sep 2017 19:50:11 -0600 (MDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tRCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;\n\ts=20161025; \n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=3N1zXWIaxIPxeThpTLLdpgrFSECPIx8HhkJWI1nXXZg=;\n\tb=nPxz22xZHm+bUfJlP7iK0UFObgL7NCPQabl9eGxqezO0bhHfWXrRB4BCbgQpah65Om\n\tiaFo48f7o+qAvz6BUH4E4XNv+F4Awi/zyrb+Jc/PwxxpxIgm0p8WTPZ5e88zipv0agK9\n\tvi/k0x3HFmMo05K5Uek1ZFx+fsO7un90ilS+hlyw9CE5wX8FRyt4F/XCnn3b58zDTfEn\n\t2oP0b2AQVB3XSkDE3gu7ml/UMZDVGlGevDMqy70d4gJoJ6x/+dk6qaqhPvB8AvHyWcib\n\t3YU418sjmziQwszQHJzwhLF8Rb2XYFCG5hPsMkl0R5tvq1TUmKyYJnDsfksxIOMaYmt6\n\tWW9Q==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references;\n\tbh=3N1zXWIaxIPxeThpTLLdpgrFSECPIx8HhkJWI1nXXZg=;\n\tb=bMs7U/tiOwtj7h8ZGigfdlaFmTukZXvKgDrHDZMOGosFrLiilgc9oYYrYjXoBw39hP\n\t4ShQSSDlEAjcuYLJOL6XEebg+VJaMu/lFlerXZC5lzOJc7h6X/mlko0b3m9gy45LXWjE\n\tSuluPo4GZ674f7gw5GO1Bp62+l753VVgc0y5voqWAX5TbVuWXijb3D/z9yyprl68DvEx\n\tnXW/vQ7r9kVNvrHRnNZ81bbI8PyqRTgNhJ0gvQdt6fPtiABwnHfo0VssMYse4uhg86r8\n\tgeY7aeYmTdkvgIfo2FyJXhcKMDcEKeaRu09v7r6gjohfKlcRCSKkAO97zdGg88BQLtuC\n\t78FA==", "X-Gm-Message-State": "AHPjjUi8UryYFJVg2JxqBw7AS5T9sL8T/jMBOTL9X4mBy/sYZceqltir\n\tfVOSDKMBYzkhPyZ+", "X-Google-Smtp-Source": "ADKCNb7lGkLAqeX4L1MJpDLc7HHg382b900PE42a0N59UHJavJPfAz+bnfWnfMSVNLjTaSXVe4jTgw==", "X-Received": "by 10.202.108.130 with SMTP id\n\th124mr1043319oic.143.1504662615706; \n\tTue, 05 Sep 2017 18:50:15 -0700 (PDT)", "From": "Simon Glass <sjg@chromium.org>", "To": "U-Boot Mailing List <u-boot@lists.denx.de>", "Date": "Tue, 5 Sep 2017 19:49:46 -0600", "Message-Id": "<20170906014950.132960-3-sjg@chromium.org>", "X-Mailer": "git-send-email 2.14.1.581.gf28d330327-goog", "In-Reply-To": "<20170906014950.132960-1-sjg@chromium.org>", "References": "<20170906014950.132960-1-sjg@chromium.org>", "Subject": "[U-Boot] [PATCH v3 2/6] dm: x86: Allow TSC timer to be used before\n\tDM is ready", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "With bootstage we need access to the timer before driver model is set up.\nTo handle this, put the required state in global_data and provide a new\nfunction to set up the device, separate from the driver's probe() method.\n\nThis will be used by the 'early' timer also.\n\nSigned-off-by: Simon Glass <sjg@chromium.org>\nReviewed-by: Bin Meng <bmeng.cn@gmail.com>\n---\n\nChanges in v3: None\nChanges in v2:\n- Update to support the early timer\n\n arch/x86/include/asm/global_data.h | 1 +\n drivers/timer/tsc_timer.c | 30 +++++++++++++++++++++++++-----\n 2 files changed, 26 insertions(+), 5 deletions(-)", "diff": "diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h\nindex 93a80fe2b6..fcb6853a38 100644\n--- a/arch/x86/include/asm/global_data.h\n+++ b/arch/x86/include/asm/global_data.h\n@@ -77,6 +77,7 @@ struct arch_global_data {\n \tuint8_t x86_mask;\n \tuint32_t x86_device;\n \tuint64_t tsc_base;\t\t/* Initial value returned by rdtsc() */\n+\tunsigned long clock_rate;\t/* Clock rate of timer in Hz */\n \tvoid *new_fdt;\t\t\t/* Relocated FDT */\n \tuint32_t bist;\t\t\t/* Built-in self test value */\n \tenum pei_boot_mode_t pei_boot_mode;\ndiff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c\nindex 4d1fc9cd13..0012fecde0 100644\n--- a/drivers/timer/tsc_timer.c\n+++ b/drivers/timer/tsc_timer.c\n@@ -328,17 +328,17 @@ static int tsc_timer_get_count(struct udevice *dev, u64 *count)\n \treturn 0;\n }\n \n-static int tsc_timer_probe(struct udevice *dev)\n+static void tsc_timer_ensure_setup(void)\n {\n-\tstruct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);\n-\n+\tif (gd->arch.tsc_base)\n+\t\treturn;\n \tgd->arch.tsc_base = rdtsc();\n \n \t/*\n \t * If there is no clock frequency specified in the device tree,\n \t * calibrate it by ourselves.\n \t */\n-\tif (!uc_priv->clock_rate) {\n+\tif (!gd->arch.clock_rate) {\n \t\tunsigned long fast_calibrate;\n \n \t\tfast_calibrate = cpu_mhz_from_msr();\n@@ -348,12 +348,32 @@ static int tsc_timer_probe(struct udevice *dev)\n \t\t\t\tpanic(\"TSC frequency is ZERO\");\n \t\t}\n \n-\t\tuc_priv->clock_rate = fast_calibrate * 1000000;\n+\t\tgd->arch.clock_rate = fast_calibrate * 1000000;\n \t}\n+}\n+\n+static int tsc_timer_probe(struct udevice *dev)\n+{\n+\tstruct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);\n+\n+\ttsc_timer_ensure_setup();\n+\tuc_priv->clock_rate = gd->arch.clock_rate;\n \n \treturn 0;\n }\n \n+unsigned long notrace timer_early_get_rate(void)\n+{\n+\ttsc_timer_ensure_setup();\n+\n+\treturn gd->arch.clock_rate;\n+}\n+\n+u64 notrace timer_early_get_count(void)\n+{\n+\treturn rdtsc() - gd->arch.tsc_base;\n+}\n+\n static const struct timer_ops tsc_timer_ops = {\n \t.get_count = tsc_timer_get_count,\n };\n", "prefixes": [ "U-Boot", "v3", "2/6" ] }