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GET /api/patches/810248/?format=api
{ "id": 810248, "url": "http://patchwork.ozlabs.org/api/patches/810248/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170905182707.27030.43056.stgit@bhelgaas-glaptop.roam.corp.google.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170905182707.27030.43056.stgit@bhelgaas-glaptop.roam.corp.google.com>", "list_archive_url": null, "date": "2017-09-05T18:27:07", "name": "[2/4] PCI: iproc: Clean up whitespace", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "3710c080c45f4d64091cffdd2064f015f129d834", "submitter": { "id": 7584, "url": "http://patchwork.ozlabs.org/api/people/7584/?format=api", "name": "Bjorn Helgaas", "email": "bhelgaas@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170905182707.27030.43056.stgit@bhelgaas-glaptop.roam.corp.google.com/mbox/", "series": [ { "id": 1628, "url": "http://patchwork.ozlabs.org/api/series/1628/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=1628", "date": "2017-09-05T18:26:52", "name": "iproc/xgene PCIe cap & whitespace cleanup", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1628/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810248/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810248/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "mail.kernel.org; dmarc=fail (p=reject dis=none)\n\theader.from=google.com", "mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmwDH2wPQz9sCZ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 6 Sep 2017 04:27:11 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752199AbdIES1K (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 5 Sep 2017 14:27:10 -0400", "from mail.kernel.org ([198.145.29.99]:59580 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752108AbdIES1J (ORCPT <rfc822;linux-pci@vger.kernel.org>);\n\tTue, 5 Sep 2017 14:27:09 -0400", "from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id C991421E93;\n\tTue, 5 Sep 2017 18:27:08 +0000 (UTC)" ], "DMARC-Filter": "OpenDMARC Filter v1.3.2 mail.kernel.org C991421E93", "Subject": "[PATCH 2/4] PCI: iproc: Clean up whitespace", "From": "Bjorn Helgaas <bhelgaas@google.com>", "To": "Jon Mason <jonmason@broadcom.com>, Ray Jui <rjui@broadcom.com>,\n\tOza Pawandeep <oza.oza@broadcom.com>, Tanmay Inamdar <tinamdar@apm.com>,\n\tScott Branden <sbranden@broadcom.com>", "Cc": "linux-pci@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com", "Date": "Tue, 05 Sep 2017 13:27:07 -0500", "Message-ID": "<20170905182707.27030.43056.stgit@bhelgaas-glaptop.roam.corp.google.com>", "In-Reply-To": "<20170905181602.27030.65715.stgit@bhelgaas-glaptop.roam.corp.google.com>", "References": "<20170905181602.27030.65715.stgit@bhelgaas-glaptop.roam.corp.google.com>", "User-Agent": "StGit/0.17.1-dirty", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Use tabs (not spaces) for indentation. No functional change intended.\n\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\n---\n drivers/pci/host/pcie-iproc.c | 231 ++++++++++++++++++++---------------------\n 1 file changed, 115 insertions(+), 116 deletions(-)", "diff": "diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c\nindex 4e83a9ffa5e2..3a8b9d20ee57 100644\n--- a/drivers/pci/host/pcie-iproc.c\n+++ b/drivers/pci/host/pcie-iproc.c\n@@ -31,71 +31,71 @@\n \n #include \"pcie-iproc.h\"\n \n-#define EP_PERST_SOURCE_SELECT_SHIFT 2\n-#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)\n-#define EP_MODE_SURVIVE_PERST_SHIFT 1\n-#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)\n-#define RC_PCIE_RST_OUTPUT_SHIFT 0\n-#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)\n-#define PAXC_RESET_MASK 0x7f\n-\n-#define GIC_V3_CFG_SHIFT 0\n-#define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT)\n-\n-#define MSI_ENABLE_CFG_SHIFT 0\n-#define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT)\n-\n-#define CFG_IND_ADDR_MASK 0x00001ffc\n-\n-#define CFG_ADDR_BUS_NUM_SHIFT 20\n-#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000\n-#define CFG_ADDR_DEV_NUM_SHIFT 15\n-#define CFG_ADDR_DEV_NUM_MASK 0x000f8000\n-#define CFG_ADDR_FUNC_NUM_SHIFT 12\n-#define CFG_ADDR_FUNC_NUM_MASK 0x00007000\n-#define CFG_ADDR_REG_NUM_SHIFT 2\n-#define CFG_ADDR_REG_NUM_MASK 0x00000ffc\n-#define CFG_ADDR_CFG_TYPE_SHIFT 0\n-#define CFG_ADDR_CFG_TYPE_MASK 0x00000003\n-\n-#define SYS_RC_INTX_MASK 0xf\n-\n-#define PCIE_PHYLINKUP_SHIFT 3\n-#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)\n-#define PCIE_DL_ACTIVE_SHIFT 2\n-#define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)\n-\n-#define APB_ERR_EN_SHIFT 0\n-#define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)\n-\n-#define CFG_RETRY_STATUS 0xffff0001\n-#define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milliseconds */\n+#define EP_PERST_SOURCE_SELECT_SHIFT\t2\n+#define EP_PERST_SOURCE_SELECT\t\tBIT(EP_PERST_SOURCE_SELECT_SHIFT)\n+#define EP_MODE_SURVIVE_PERST_SHIFT\t1\n+#define EP_MODE_SURVIVE_PERST\t\tBIT(EP_MODE_SURVIVE_PERST_SHIFT)\n+#define RC_PCIE_RST_OUTPUT_SHIFT\t0\n+#define RC_PCIE_RST_OUTPUT\t\tBIT(RC_PCIE_RST_OUTPUT_SHIFT)\n+#define PAXC_RESET_MASK\t\t\t0x7f\n+\n+#define GIC_V3_CFG_SHIFT\t\t0\n+#define GIC_V3_CFG\t\t\tBIT(GIC_V3_CFG_SHIFT)\n+\n+#define MSI_ENABLE_CFG_SHIFT\t\t0\n+#define MSI_ENABLE_CFG\t\t\tBIT(MSI_ENABLE_CFG_SHIFT)\n+\n+#define CFG_IND_ADDR_MASK\t\t0x00001ffc\n+\n+#define CFG_ADDR_BUS_NUM_SHIFT\t\t20\n+#define CFG_ADDR_BUS_NUM_MASK\t\t0x0ff00000\n+#define CFG_ADDR_DEV_NUM_SHIFT\t\t15\n+#define CFG_ADDR_DEV_NUM_MASK\t\t0x000f8000\n+#define CFG_ADDR_FUNC_NUM_SHIFT\t\t12\n+#define CFG_ADDR_FUNC_NUM_MASK\t\t0x00007000\n+#define CFG_ADDR_REG_NUM_SHIFT\t\t2\n+#define CFG_ADDR_REG_NUM_MASK\t\t0x00000ffc\n+#define CFG_ADDR_CFG_TYPE_SHIFT\t\t0\n+#define CFG_ADDR_CFG_TYPE_MASK\t\t0x00000003\n+\n+#define SYS_RC_INTX_MASK\t\t0xf\n+\n+#define PCIE_PHYLINKUP_SHIFT\t\t3\n+#define PCIE_PHYLINKUP\t\t\tBIT(PCIE_PHYLINKUP_SHIFT)\n+#define PCIE_DL_ACTIVE_SHIFT\t\t2\n+#define PCIE_DL_ACTIVE\t\t\tBIT(PCIE_DL_ACTIVE_SHIFT)\n+\n+#define APB_ERR_EN_SHIFT\t\t0\n+#define APB_ERR_EN\t\t\tBIT(APB_ERR_EN_SHIFT)\n+\n+#define CFG_RETRY_STATUS\t\t0xffff0001\n+#define CFG_RETRY_STATUS_TIMEOUT_US\t500000 /* 500 milliseconds */\n \n /* derive the enum index of the outbound/inbound mapping registers */\n-#define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)\n+#define MAP_REG(base_reg, index)\t((base_reg) + (index) * 2)\n \n /*\n * Maximum number of outbound mapping window sizes that can be supported by any\n * OARR/OMAP mapping pair\n */\n-#define MAX_NUM_OB_WINDOW_SIZES 4\n+#define MAX_NUM_OB_WINDOW_SIZES\t\t4\n \n-#define OARR_VALID_SHIFT 0\n-#define OARR_VALID BIT(OARR_VALID_SHIFT)\n-#define OARR_SIZE_CFG_SHIFT 1\n+#define OARR_VALID_SHIFT\t\t0\n+#define OARR_VALID\t\t\tBIT(OARR_VALID_SHIFT)\n+#define OARR_SIZE_CFG_SHIFT\t\t1\n \n /*\n * Maximum number of inbound mapping region sizes that can be supported by an\n * IARR\n */\n-#define MAX_NUM_IB_REGION_SIZES 9\n+#define MAX_NUM_IB_REGION_SIZES\t\t9\n \n-#define IMAP_VALID_SHIFT 0\n-#define IMAP_VALID BIT(IMAP_VALID_SHIFT)\n+#define IMAP_VALID_SHIFT\t\t0\n+#define IMAP_VALID\t\t\tBIT(IMAP_VALID_SHIFT)\n \n #define IPROC_PCI_EXP_CAP\t\t0xac\n \n-#define IPROC_PCIE_REG_INVALID 0xffff\n+#define IPROC_PCIE_REG_INVALID\t\t0xffff\n \n /**\n * iProc PCIe outbound mapping controller specific parameters\n@@ -307,80 +307,80 @@ enum iproc_pcie_reg {\n \n /* iProc PCIe PAXB BCMA registers */\n static const u16 iproc_pcie_reg_paxb_bcma[] = {\n-\t[IPROC_PCIE_CLK_CTRL] = 0x000,\n-\t[IPROC_PCIE_CFG_IND_ADDR] = 0x120,\n-\t[IPROC_PCIE_CFG_IND_DATA] = 0x124,\n-\t[IPROC_PCIE_CFG_ADDR] = 0x1f8,\n-\t[IPROC_PCIE_CFG_DATA] = 0x1fc,\n-\t[IPROC_PCIE_INTX_EN] = 0x330,\n-\t[IPROC_PCIE_LINK_STATUS] = 0xf0c,\n+\t[IPROC_PCIE_CLK_CTRL]\t\t= 0x000,\n+\t[IPROC_PCIE_CFG_IND_ADDR]\t= 0x120,\n+\t[IPROC_PCIE_CFG_IND_DATA]\t= 0x124,\n+\t[IPROC_PCIE_CFG_ADDR]\t\t= 0x1f8,\n+\t[IPROC_PCIE_CFG_DATA]\t\t= 0x1fc,\n+\t[IPROC_PCIE_INTX_EN]\t\t= 0x330,\n+\t[IPROC_PCIE_LINK_STATUS]\t= 0xf0c,\n };\n \n /* iProc PCIe PAXB registers */\n static const u16 iproc_pcie_reg_paxb[] = {\n-\t[IPROC_PCIE_CLK_CTRL] = 0x000,\n-\t[IPROC_PCIE_CFG_IND_ADDR] = 0x120,\n-\t[IPROC_PCIE_CFG_IND_DATA] = 0x124,\n-\t[IPROC_PCIE_CFG_ADDR] = 0x1f8,\n-\t[IPROC_PCIE_CFG_DATA] = 0x1fc,\n-\t[IPROC_PCIE_INTX_EN] = 0x330,\n-\t[IPROC_PCIE_OARR0] = 0xd20,\n-\t[IPROC_PCIE_OMAP0] = 0xd40,\n-\t[IPROC_PCIE_OARR1] = 0xd28,\n-\t[IPROC_PCIE_OMAP1] = 0xd48,\n-\t[IPROC_PCIE_LINK_STATUS] = 0xf0c,\n-\t[IPROC_PCIE_APB_ERR_EN] = 0xf40,\n+\t[IPROC_PCIE_CLK_CTRL]\t\t= 0x000,\n+\t[IPROC_PCIE_CFG_IND_ADDR]\t= 0x120,\n+\t[IPROC_PCIE_CFG_IND_DATA]\t= 0x124,\n+\t[IPROC_PCIE_CFG_ADDR]\t\t= 0x1f8,\n+\t[IPROC_PCIE_CFG_DATA]\t\t= 0x1fc,\n+\t[IPROC_PCIE_INTX_EN]\t\t= 0x330,\n+\t[IPROC_PCIE_OARR0]\t\t= 0xd20,\n+\t[IPROC_PCIE_OMAP0]\t\t= 0xd40,\n+\t[IPROC_PCIE_OARR1]\t\t= 0xd28,\n+\t[IPROC_PCIE_OMAP1]\t\t= 0xd48,\n+\t[IPROC_PCIE_LINK_STATUS]\t= 0xf0c,\n+\t[IPROC_PCIE_APB_ERR_EN]\t\t= 0xf40,\n };\n \n /* iProc PCIe PAXB v2 registers */\n static const u16 iproc_pcie_reg_paxb_v2[] = {\n-\t[IPROC_PCIE_CLK_CTRL] = 0x000,\n-\t[IPROC_PCIE_CFG_IND_ADDR] = 0x120,\n-\t[IPROC_PCIE_CFG_IND_DATA] = 0x124,\n-\t[IPROC_PCIE_CFG_ADDR] = 0x1f8,\n-\t[IPROC_PCIE_CFG_DATA] = 0x1fc,\n-\t[IPROC_PCIE_INTX_EN] = 0x330,\n-\t[IPROC_PCIE_OARR0] = 0xd20,\n-\t[IPROC_PCIE_OMAP0] = 0xd40,\n-\t[IPROC_PCIE_OARR1] = 0xd28,\n-\t[IPROC_PCIE_OMAP1] = 0xd48,\n-\t[IPROC_PCIE_OARR2] = 0xd60,\n-\t[IPROC_PCIE_OMAP2] = 0xd68,\n-\t[IPROC_PCIE_OARR3] = 0xdf0,\n-\t[IPROC_PCIE_OMAP3] = 0xdf8,\n-\t[IPROC_PCIE_IARR0] = 0xd00,\n-\t[IPROC_PCIE_IMAP0] = 0xc00,\n-\t[IPROC_PCIE_IARR2] = 0xd10,\n-\t[IPROC_PCIE_IMAP2] = 0xcc0,\n-\t[IPROC_PCIE_IARR3] = 0xe00,\n-\t[IPROC_PCIE_IMAP3] = 0xe08,\n-\t[IPROC_PCIE_IARR4] = 0xe68,\n-\t[IPROC_PCIE_IMAP4] = 0xe70,\n-\t[IPROC_PCIE_LINK_STATUS] = 0xf0c,\n-\t[IPROC_PCIE_APB_ERR_EN] = 0xf40,\n+\t[IPROC_PCIE_CLK_CTRL]\t\t= 0x000,\n+\t[IPROC_PCIE_CFG_IND_ADDR]\t= 0x120,\n+\t[IPROC_PCIE_CFG_IND_DATA]\t= 0x124,\n+\t[IPROC_PCIE_CFG_ADDR]\t\t= 0x1f8,\n+\t[IPROC_PCIE_CFG_DATA]\t\t= 0x1fc,\n+\t[IPROC_PCIE_INTX_EN]\t\t= 0x330,\n+\t[IPROC_PCIE_OARR0]\t\t= 0xd20,\n+\t[IPROC_PCIE_OMAP0]\t\t= 0xd40,\n+\t[IPROC_PCIE_OARR1]\t\t= 0xd28,\n+\t[IPROC_PCIE_OMAP1]\t\t= 0xd48,\n+\t[IPROC_PCIE_OARR2]\t\t= 0xd60,\n+\t[IPROC_PCIE_OMAP2]\t\t= 0xd68,\n+\t[IPROC_PCIE_OARR3]\t\t= 0xdf0,\n+\t[IPROC_PCIE_OMAP3]\t\t= 0xdf8,\n+\t[IPROC_PCIE_IARR0]\t\t= 0xd00,\n+\t[IPROC_PCIE_IMAP0]\t\t= 0xc00,\n+\t[IPROC_PCIE_IARR2]\t\t= 0xd10,\n+\t[IPROC_PCIE_IMAP2]\t\t= 0xcc0,\n+\t[IPROC_PCIE_IARR3]\t\t= 0xe00,\n+\t[IPROC_PCIE_IMAP3]\t\t= 0xe08,\n+\t[IPROC_PCIE_IARR4]\t\t= 0xe68,\n+\t[IPROC_PCIE_IMAP4]\t\t= 0xe70,\n+\t[IPROC_PCIE_LINK_STATUS]\t= 0xf0c,\n+\t[IPROC_PCIE_APB_ERR_EN]\t\t= 0xf40,\n };\n \n /* iProc PCIe PAXC v1 registers */\n static const u16 iproc_pcie_reg_paxc[] = {\n-\t[IPROC_PCIE_CLK_CTRL] = 0x000,\n-\t[IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,\n-\t[IPROC_PCIE_CFG_IND_DATA] = 0x1f4,\n-\t[IPROC_PCIE_CFG_ADDR] = 0x1f8,\n-\t[IPROC_PCIE_CFG_DATA] = 0x1fc,\n+\t[IPROC_PCIE_CLK_CTRL]\t\t= 0x000,\n+\t[IPROC_PCIE_CFG_IND_ADDR]\t= 0x1f0,\n+\t[IPROC_PCIE_CFG_IND_DATA]\t= 0x1f4,\n+\t[IPROC_PCIE_CFG_ADDR]\t\t= 0x1f8,\n+\t[IPROC_PCIE_CFG_DATA]\t\t= 0x1fc,\n };\n \n /* iProc PCIe PAXC v2 registers */\n static const u16 iproc_pcie_reg_paxc_v2[] = {\n-\t[IPROC_PCIE_MSI_GIC_MODE] = 0x050,\n-\t[IPROC_PCIE_MSI_BASE_ADDR] = 0x074,\n-\t[IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,\n-\t[IPROC_PCIE_MSI_ADDR_LO] = 0x07c,\n-\t[IPROC_PCIE_MSI_ADDR_HI] = 0x080,\n-\t[IPROC_PCIE_MSI_EN_CFG] = 0x09c,\n-\t[IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,\n-\t[IPROC_PCIE_CFG_IND_DATA] = 0x1f4,\n-\t[IPROC_PCIE_CFG_ADDR] = 0x1f8,\n-\t[IPROC_PCIE_CFG_DATA] = 0x1fc,\n+\t[IPROC_PCIE_MSI_GIC_MODE]\t= 0x050,\n+\t[IPROC_PCIE_MSI_BASE_ADDR]\t= 0x074,\n+\t[IPROC_PCIE_MSI_WINDOW_SIZE]\t= 0x078,\n+\t[IPROC_PCIE_MSI_ADDR_LO]\t= 0x07c,\n+\t[IPROC_PCIE_MSI_ADDR_HI]\t= 0x080,\n+\t[IPROC_PCIE_MSI_EN_CFG]\t\t= 0x09c,\n+\t[IPROC_PCIE_CFG_IND_ADDR]\t= 0x1f0,\n+\t[IPROC_PCIE_CFG_IND_DATA]\t= 0x1f4,\n+\t[IPROC_PCIE_CFG_ADDR]\t\t= 0x1f8,\n+\t[IPROC_PCIE_CFG_DATA]\t\t= 0x1fc,\n };\n \n static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)\n@@ -511,7 +511,7 @@ static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)\n }\n \n static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,\n-\t\t\t\t int where, int size, u32 *val)\n+\t\t\t\t int where, int size, u32 *val)\n {\n \tstruct iproc_pcie *pcie = iproc_data(bus);\n \tunsigned int slot = PCI_SLOT(devfn);\n@@ -552,8 +552,7 @@ static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,\n * by 'pci_lock' in drivers/pci/access.c\n */\n static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie,\n-\t\t\t\t\t int busno,\n-\t\t\t\t\t unsigned int devfn,\n+\t\t\t\t\t int busno, unsigned int devfn,\n \t\t\t\t\t int where)\n {\n \tunsigned slot = PCI_SLOT(devfn);\n@@ -726,16 +725,16 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie)\n \t}\n \n \t/* make sure we are not in EP mode */\n-\tiproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type);\n+\tiproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type);\n \tif ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {\n \t\tdev_err(dev, \"in EP mode, hdr=%#02x\\n\", hdr_type);\n \t\treturn -EFAULT;\n \t}\n \n \t/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */\n-#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c\n-#define PCI_CLASS_BRIDGE_MASK 0xffff00\n-#define PCI_CLASS_BRIDGE_SHIFT 8\n+#define PCI_BRIDGE_CTRL_REG_OFFSET\t0x43c\n+#define PCI_CLASS_BRIDGE_MASK\t\t0xffff00\n+#define PCI_CLASS_BRIDGE_SHIFT\t\t8\n \tiproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,\n \t\t\t\t 4, &class);\n \tclass &= ~PCI_CLASS_BRIDGE_MASK;\n@@ -751,9 +750,9 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie)\n \n \tif (!link_is_active) {\n \t\t/* try GEN 1 link speed */\n-#define PCI_TARGET_LINK_SPEED_MASK 0xf\n-#define PCI_TARGET_LINK_SPEED_GEN2 0x2\n-#define PCI_TARGET_LINK_SPEED_GEN1 0x1\n+#define PCI_TARGET_LINK_SPEED_MASK\t0xf\n+#define PCI_TARGET_LINK_SPEED_GEN2\t0x2\n+#define PCI_TARGET_LINK_SPEED_GEN1\t0x1\n \t\tiproc_pci_raw_config_read32(pcie, 0,\n \t\t\t\t\t IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,\n \t\t\t\t\t 4, &link_ctrl);\n", "prefixes": [ "2/4" ] }