Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/810072/?format=api
{ "id": 810072, "url": "http://patchwork.ozlabs.org/api/patches/810072/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/CAFULd4aqW0ic2qQ5z+g4Fz92kO-9tr_9onKzoVoCQ6V+kV4sFA@mail.gmail.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<CAFULd4aqW0ic2qQ5z+g4Fz92kO-9tr_9onKzoVoCQ6V+kV4sFA@mail.gmail.com>", "list_archive_url": null, "date": "2017-09-05T10:26:28", "name": "[middle-end] : Introduce memory_blockage named insn pattern", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "150257a2fffd45182d1ef4052d9220f993b5d856", "submitter": { "id": 808, "url": "http://patchwork.ozlabs.org/api/people/808/?format=api", "name": "Uros Bizjak", "email": "ubizjak@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/CAFULd4aqW0ic2qQ5z+g4Fz92kO-9tr_9onKzoVoCQ6V+kV4sFA@mail.gmail.com/mbox/", "series": [ { "id": 1545, "url": "http://patchwork.ozlabs.org/api/series/1545/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=1545", "date": "2017-09-05T10:26:28", "name": "[middle-end] : Introduce memory_blockage named insn pattern", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1545/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810072/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810072/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461477-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461477-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"UwstCGwr\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmjYw5cvMz9s3w\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 5 Sep 2017 20:26:44 +1000 (AEST)", "(qmail 94156 invoked by alias); 5 Sep 2017 10:26:36 -0000", "(qmail 94141 invoked by uid 89); 5 Sep 2017 10:26:35 -0000", "from mail-ua0-f194.google.com (HELO mail-ua0-f194.google.com)\n\t(209.85.217.194) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tTue, 05 Sep 2017 10:26:30 +0000", "by mail-ua0-f194.google.com with SMTP id q29so1090027uaf.4 for\n\t<gcc-patches@gcc.gnu.org>; Tue, 05 Sep 2017 03:26:30 -0700 (PDT)", "by 10.103.55.28 with HTTP; Tue, 5 Sep 2017 03:26:28 -0700 (PDT)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:from:date:message-id:subject:to:content-type; q=\n\tdns; s=default; b=eSb0yTcR3T60W6PvF9YDh4boMOgqfHns2WHixjyM2iHDdk\n\tWK4ZzrRLhIs14INVECgJaFAkhyn8M1BIfsO3/+cEb28yiwHIJh/5TRtTJSOV92/O\n\t1YNyDNVJZktRkLHIR0QapZD27tuWfNDnOKFM0c4GOF/5fCWnJMROw8qdhLJIk=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:from:date:message-id:subject:to:content-type; s=\n\tdefault; bh=R7ZR1SOLvm7DnRxntUgxcq0+9Ms=; b=UwstCGwrASC5kV8yjDRe\n\tslXLH7LBaZBQgKV0IyXiV0xglUjIH7AWknjz5iHwrchAC9fTptSEx5wHT5Ql2UIy\n\tes5IGGiGxiUU5BUqbo2crGxyHbxIki9lfvEFw590j0K9nEdcdkIWSXqU/2I91+Vm\n\tfz31u3IpRrsUJIy5+gPllso=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-24.3 required=5.0 tests=AWL, BAYES_00,\n\tFREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2,\n\tGIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM,\n\tSPF_PASS autolearn=ham version=3.3.2\n\tspammy=Hx-spam-relays-external:209.85.217.194,\n\tH*RU:209.85.217.194, hello!", "X-HELO": "mail-ua0-f194.google.com", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:mime-version:from:date:message-id:subject:to;\n\tbh=fybR4YVG7f8mXxqwE2UmhDeHNAk1dlkKf2EHJnfu/b8=;\n\tb=KFcBSSy8j2McgH5kshqvltv8cVrHlvOWo1RjlPzSAyabv7EI82LQnUN09EruUBcrIS\n\trlMcHF4toLNVG16+WwIxylnAzNzn9BMoTvGN/fnypCXMOcZG4R9ZOHMqN3Hf4pzlsmQX\n\t6pYdHZ30olnEf2/Dc/jfVPHOsjFXvBrJIp4CnaPhen0Gu+wJt98XO2aeLDFElRDpIN2s\n\tg5c66T1A2wBuxxILC/D/vB2AkM9QijejiefZP3h/UVgh6fGWhar4MK/zKSi+QAJbWx8N\n\tjs0ebH+2JA1dmUN2h49gwwg4/YZyIkZxIjEJrIlXmLbYxAI8WyfuoyQzIjU7UP+E/T12\n\tPe3w==", "X-Gm-Message-State": "AHPjjUj9R8bbF3dJaJF+XOH1apIo1A9cY9d5Klyr4f4rYXr/cSFncnUE\tJ5qhnSiEE5AgP8TPBzj0fTb8o0pp82n0", "X-Google-Smtp-Source": "ADKCNb7tCoAAZNkdWYSzXMuZWluMookFAicZHD14dcXrJqWgbSQDYJ+qcorBUuu9O0/ViEUIJ2WDadbsWxxwD3k8kBk=", "X-Received": "by 10.176.69.243 with SMTP id u106mr2295646uau.22.1504607188723;\n\tTue, 05 Sep 2017 03:26:28 -0700 (PDT)", "MIME-Version": "1.0", "From": "Uros Bizjak <ubizjak@gmail.com>", "Date": "Tue, 5 Sep 2017 12:26:28 +0200", "Message-ID": "<CAFULd4aqW0ic2qQ5z+g4Fz92kO-9tr_9onKzoVoCQ6V+kV4sFA@mail.gmail.com>", "Subject": "[PATCH, middle-end]: Introduce memory_blockage named insn pattern", "To": "\"gcc-patches@gcc.gnu.org\" <gcc-patches@gcc.gnu.org>", "Content-Type": "multipart/mixed; boundary=\"94eb2c11be7402c07305586ea973\"" }, "content": "Hello!\n\nThis patch allows to emit memory_blockage pattern instead of default\nasm volatile as a memory blockage. This patch is needed, so targets\n(e.g. x86) can define and emit more optimal memory blockage pseudo\ninsn. And let's call scheduler memory barriers a \"memory blockage\"\npseudo insn, not \"memory barrier\" which should describe real\ninstruction.\n\n2017-09-05 Uros Bizjak <ubizjak@gmail.com>\n\n * optabs.c (expand_memory_blockage): New function.\n (expand_asm_memory_barrier): Rename ...\n (expand_asm_memory_blockage): ... to this.\n (expand_mem_thread_fence): Call expand_memory_blockage\n instead of expand_asm_memory_barrier.\n (expand_mem_singnal_fence): Ditto.\n (expand_atomic_load): Ditto.\n (expand_atomic_store): Ditto.\n * doc/md.texi (Standard Pattern Names For Generation):\n Document memory_blockage instruction pattern.\n\nBootstrapped on x86_64-linux-gnu, regression test (with additional x86\npatch that fixes recent optimization regression with FP atomic loads)\nis in progress.\n\nOK for mainline?\n\nUros.", "diff": "diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi\nindex 14aab9474bc2..df4dc8ccd0e1 100644\n--- a/gcc/doc/md.texi\n+++ b/gcc/doc/md.texi\n@@ -6734,6 +6734,13 @@ scheduler and other passes from moving instructions and using register\n equivalences across the boundary defined by the blockage insn.\n This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.\n \n+@cindex @code{memmory_blockage} instruction pattern\n+@item @samp{memory_blockage}\n+This pattern defines a pseudo insn that prevents the instruction\n+scheduler and other passes from moving instructions accessing memory\n+across the boundary defined by the blockage insn. This instruction\n+needs to read and write volatile BLKmode memory.\n+\n @cindex @code{memory_barrier} instruction pattern\n @item @samp{memory_barrier}\n If the target memory model is not fully synchronous, then this pattern\ndiff --git a/gcc/optabs.c b/gcc/optabs.c\nindex b65707080eee..c3b1bc848bf7 100644\n--- a/gcc/optabs.c\n+++ b/gcc/optabs.c\n@@ -6276,10 +6276,10 @@ expand_atomic_compare_and_swap (rtx *ptarget_bool, rtx *ptarget_oval,\n return true;\n }\n \n-/* Generate asm volatile(\"\" : : : \"memory\") as the memory barrier. */\n+/* Generate asm volatile(\"\" : : : \"memory\") as the memory blockage. */\n \n static void\n-expand_asm_memory_barrier (void)\n+expand_asm_memory_blockage (void)\n {\n rtx asm_op, clob;\n \n@@ -6295,6 +6295,18 @@ expand_asm_memory_barrier (void)\n emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, asm_op, clob)));\n }\n \n+/* Do not schedule instructions accessing memory across this point. */\n+\n+static void\n+expand_memory_blockage (void)\n+{\n+#ifdef HAVE_memory_blockage\n+ emit_insn (gen_memory_blockage ());\n+#else\n+ expand_asm_memory_blockage ();\n+#endif\n+}\n+\n /* This routine will either emit the mem_thread_fence pattern or issue a \n sync_synchronize to generate a fence for memory model MEMMODEL. */\n \n@@ -6306,14 +6318,14 @@ expand_mem_thread_fence (enum memmodel model)\n if (targetm.have_mem_thread_fence ())\n {\n emit_insn (targetm.gen_mem_thread_fence (GEN_INT (model)));\n- expand_asm_memory_barrier ();\n+ expand_memory_blockage ();\n }\n else if (targetm.have_memory_barrier ())\n emit_insn (targetm.gen_memory_barrier ());\n else if (synchronize_libfunc != NULL_RTX)\n emit_library_call (synchronize_libfunc, LCT_NORMAL, VOIDmode);\n else\n- expand_asm_memory_barrier ();\n+ expand_memory_blockage ();\n }\n \n /* Emit a signal fence with given memory model. */\n@@ -6324,7 +6336,7 @@ expand_mem_signal_fence (enum memmodel model)\n /* No machine barrier is required to implement a signal fence, but\n a compiler memory barrier must be issued, except for relaxed MM. */\n if (!is_mm_relaxed (model))\n- expand_asm_memory_barrier ();\n+ expand_memory_blockage ();\n }\n \n /* This function expands the atomic load operation:\n@@ -6346,7 +6358,7 @@ expand_atomic_load (rtx target, rtx mem, enum memmodel model)\n struct expand_operand ops[3];\n rtx_insn *last = get_last_insn ();\n if (is_mm_seq_cst (model))\n-\texpand_asm_memory_barrier ();\n+\texpand_memory_blockage ();\n \n create_output_operand (&ops[0], target, mode);\n create_fixed_operand (&ops[1], mem);\n@@ -6354,7 +6366,7 @@ expand_atomic_load (rtx target, rtx mem, enum memmodel model)\n if (maybe_expand_insn (icode, 3, ops))\n \t{\n \t if (!is_mm_relaxed (model))\n-\t expand_asm_memory_barrier ();\n+\t expand_memory_blockage ();\n \t return ops[0].value;\n \t}\n delete_insns_since (last);\n@@ -6404,14 +6416,14 @@ expand_atomic_store (rtx mem, rtx val, enum memmodel model, bool use_release)\n {\n rtx_insn *last = get_last_insn ();\n if (!is_mm_relaxed (model))\n-\texpand_asm_memory_barrier ();\n+\texpand_memory_blockage ();\n create_fixed_operand (&ops[0], mem);\n create_input_operand (&ops[1], val, mode);\n create_integer_operand (&ops[2], model);\n if (maybe_expand_insn (icode, 3, ops))\n \t{\n \t if (is_mm_seq_cst (model))\n-\t expand_asm_memory_barrier ();\n+\t expand_memory_blockage ();\n \t return const0_rtx;\n \t}\n delete_insns_since (last);\n", "prefixes": [ "middle-end" ] }