Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/810026/?format=api
{ "id": 810026, "url": "http://patchwork.ozlabs.org/api/patches/810026/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504602267-31283-5-git-send-email-patrice.chotard@st.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504602267-31283-5-git-send-email-patrice.chotard@st.com>", "list_archive_url": null, "date": "2017-09-05T09:04:21", "name": "[U-Boot,v10,04/10] usb: phy: Add STi USB2 PHY", "commit_ref": "b7ca56dcda8a2be0e7ca6142448ab4153926aafc", "pull_url": null, "state": "accepted", "archived": false, "hash": "33ff8109f86579b9e1007bcb62fed40b25292065", "submitter": { "id": 63958, "url": "http://patchwork.ozlabs.org/api/people/63958/?format=api", "name": "Patrice CHOTARD", "email": "patrice.chotard@st.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504602267-31283-5-git-send-email-patrice.chotard@st.com/mbox/", "series": [ { "id": 1524, "url": "http://patchwork.ozlabs.org/api/series/1524/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1524", "date": "2017-09-05T09:04:18", "name": "STiH410-B2260: add reset, usb and fastboot support", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/1524/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810026/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810026/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmh125Klfz9s7m\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 5 Sep 2017 19:16:38 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 6D020C21EF3; Tue, 5 Sep 2017 09:09:54 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 72342C21F0B;\n\tTue, 5 Sep 2017 09:09:03 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid E29AEC21F0B; Tue, 5 Sep 2017 09:06:04 +0000 (UTC)", "from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com\n\t[91.207.212.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 536D4C21FB2\n\tfor <u-boot@lists.denx.de>; Tue, 5 Sep 2017 09:04:42 +0000 (UTC)", "from pps.filterd (m0046660.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv857e9Vw012881; Tue, 5 Sep 2017 11:04:34 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2cqhs56wk7-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tTue, 05 Sep 2017 11:04:34 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5F83849;\n\tTue, 5 Sep 2017 09:04:33 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4128D110C;\n\tTue, 5 Sep 2017 09:04:33 +0000 (GMT)", "from localhost (10.75.127.48) by SFHDAG6NODE3.st.com (10.75.127.18)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tTue, 5 Sep 2017 11:04:32 +0200" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "From": "<patrice.chotard@st.com>", "To": "<u-boot@lists.denx.de>, <albert.u.boot@aribaud.net>, <sjg@chromium.org>, \n\t<jh80.chung@samsung.com>, <marex@denx.de>", "Date": "Tue, 5 Sep 2017 11:04:21 +0200", "Message-ID": "<1504602267-31283-5-git-send-email-patrice.chotard@st.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1504602267-31283-1-git-send-email-patrice.chotard@st.com>", "References": "<1504602267-31283-1-git-send-email-patrice.chotard@st.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.75.127.48]", "X-ClientProxiedBy": "SFHDAG4NODE3.st.com (10.75.127.12) To SFHDAG6NODE3.st.com\n\t(10.75.127.18)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-05_03:, , signatures=0", "Subject": "[U-Boot] [PATCH v10 04/10] usb: phy: Add STi USB2 PHY", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Patrice Chotard <patrice.chotard@st.com>\n\nThis is the generic phy driver for the picoPHY ports\nused by USB2/1.1 controllers. It is found on STiH407 SoC\nfamily from STMicroelectronics.\n\nSigned-off-by: Patrice Chotard <patrice.chotard@st.com>\nReviewed-by: Simon Glass <sjg@chromium.org>\n---\nv10:\t_ none\nv9:\t_ update doc/device-tree-bindings/phy/phy-stih407-usb.txt requested by\n\t Marek Vasut \nv8:\t_ add Reviewed-by Simon Glass\nv7:\t_ replace fdtdec_parse_phandle_with_args() by dev_read_phandle_with_args() \n\t_ replace uclass_get_device_by_of_offset() by uclass_get_device_by_ofnode()\nv6:\t_ none\nv5:\t_ add Reviewed-by: Marek Vasut <marex@denx.de>\nv4:\t_ update to use the new PHY uclass currently available on dm-next branch\nv3:\t_ convert driver to USB PHY uclass\nv2:\t_ replace bitfield_replace() by clrsetbits_le32()\n\n doc/device-tree-bindings/phy/phy-stih407-usb.txt | 24 +++\n drivers/phy/Kconfig | 8 +\n drivers/phy/Makefile | 1 +\n drivers/phy/sti_usb_phy.c | 181 +++++++++++++++++++++++\n 4 files changed, 214 insertions(+)\n create mode 100644 doc/device-tree-bindings/phy/phy-stih407-usb.txt\n create mode 100644 drivers/phy/sti_usb_phy.c", "diff": "diff --git a/doc/device-tree-bindings/phy/phy-stih407-usb.txt b/doc/device-tree-bindings/phy/phy-stih407-usb.txt\nnew file mode 100644\nindex 0000000..371a7fe\n--- /dev/null\n+++ b/doc/device-tree-bindings/phy/phy-stih407-usb.txt\n@@ -0,0 +1,24 @@\n+ST STiH407 USB PHY controller\n+\n+This file documents the dt bindings for the usb picoPHY driver which is the PHY for both USB2 and USB3\n+host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC family from STMicroelectronics.\n+\n+Required properties:\n+- compatible\t\t: should be \"st,stih407-usb2-phy\"\n+- st,syscfg\t\t: phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets\n+- resets\t\t: list of phandle and reset specifier pairs. There should be two entries, one\n+\t\t\t for the whole phy and one for the port\n+- reset-names\t\t: list of reset signal names. Should be \"global\" and \"port\"\n+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt\n+See: Documentation/devicetree/bindings/reset/reset.txt\n+\n+Example:\n+\n+usb2_picophy0: usbpicophy {\n+\tcompatible\t= \"st,stih407-usb2-phy\";\n+\t#phy-cells\t= <0>;\n+\tst,syscfg\t= <&syscfg_core 0x100 0xf4>;\n+\tresets\t\t= <&softreset STIH407_PICOPHY_SOFTRESET>,\n+\t\t\t <&picophyreset STIH407_PICOPHY0_RESET>;\n+\treset-names\t= \"global\", \"port\";\n+};\ndiff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig\nindex 98f2a1b..3b9a09c 100644\n--- a/drivers/phy/Kconfig\n+++ b/drivers/phy/Kconfig\n@@ -77,4 +77,12 @@ config SPL_PIPE3_PHY\n \t This PHY is found on omap devices supporting SATA such as dra7, am57x\n \t and omap5\n \n+config STI_USB_PHY\n+\tbool \"STMicroelectronics USB2 picoPHY driver for STiH407 family\"\n+\tdepends on PHY && ARCH_STI\n+\thelp\n+\t This is the generic phy driver for the picoPHY ports\n+\t used by USB2 and USB3 Host controllers available on\n+\t STiH407 SoC families.\n+\n endmenu\ndiff --git a/drivers/phy/Makefile b/drivers/phy/Makefile\nindex ab56c46..668040b 100644\n--- a/drivers/phy/Makefile\n+++ b/drivers/phy/Makefile\n@@ -9,3 +9,4 @@ obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o\n obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o\n obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o\n obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o\n+obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o\ndiff --git a/drivers/phy/sti_usb_phy.c b/drivers/phy/sti_usb_phy.c\nnew file mode 100644\nindex 0000000..0e0b1c0\n--- /dev/null\n+++ b/drivers/phy/sti_usb_phy.c\n@@ -0,0 +1,181 @@\n+/*\n+ * Copyright (c) 2017\n+ * Patrice Chotard <patrice.chotard@st.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/io.h>\n+#include <bitfield.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <fdtdec.h>\n+#include <generic-phy.h>\n+#include <libfdt.h>\n+#include <regmap.h>\n+#include <reset-uclass.h>\n+#include <syscon.h>\n+#include <wait_bit.h>\n+\n+#include <linux/bitops.h>\n+#include <linux/compat.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+/* Default PHY_SEL and REFCLKSEL configuration */\n+#define STIH407_USB_PICOPHY_CTRL_PORT_CONF\t0x6\n+\n+/* ports parameters overriding */\n+#define STIH407_USB_PICOPHY_PARAM_DEF\t\t0x39a4dc\n+\n+#define PHYPARAM_REG\t1\n+#define PHYCTRL_REG\t2\n+#define PHYPARAM_NB\t3\n+\n+struct sti_usb_phy {\n+\tstruct regmap *regmap;\n+\tstruct reset_ctl global_ctl;\n+\tstruct reset_ctl port_ctl;\n+\tint param;\n+\tint ctrl;\n+};\n+\n+static int sti_usb_phy_deassert(struct sti_usb_phy *phy)\n+{\n+\tint ret;\n+\n+\tret = reset_deassert(&phy->global_ctl);\n+\tif (ret < 0) {\n+\t\terror(\"PHY global deassert failed: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = reset_deassert(&phy->port_ctl);\n+\tif (ret < 0)\n+\t\terror(\"PHY port deassert failed: %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int sti_usb_phy_init(struct phy *usb_phy)\n+{\n+\tstruct udevice *dev = usb_phy->dev;\n+\tstruct sti_usb_phy *phy = dev_get_priv(dev);\n+\tvoid __iomem *reg;\n+\n+\t/* set ctrl picophy value */\n+\treg = (void __iomem *)phy->regmap->base + phy->ctrl;\n+\t/* CTRL_PORT mask is 0x1f */\n+\tclrsetbits_le32(reg, 0x1f, STIH407_USB_PICOPHY_CTRL_PORT_CONF);\n+\n+\t/* set ports parameters overriding */\n+\treg = (void __iomem *)phy->regmap->base + phy->param;\n+\t/* PARAM_DEF mask is 0xffffffff */\n+\tclrsetbits_le32(reg, 0xffffffff, STIH407_USB_PICOPHY_PARAM_DEF);\n+\n+\treturn sti_usb_phy_deassert(phy);\n+}\n+\n+static int sti_usb_phy_exit(struct phy *usb_phy)\n+{\n+\tstruct udevice *dev = usb_phy->dev;\n+\tstruct sti_usb_phy *phy = dev_get_priv(dev);\n+\tint ret;\n+\n+\tret = reset_assert(&phy->port_ctl);\n+\tif (ret < 0) {\n+\t\terror(\"PHY port assert failed: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = reset_assert(&phy->global_ctl);\n+\tif (ret < 0)\n+\t\terror(\"PHY global assert failed: %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+struct phy_ops sti_usb_phy_ops = {\n+\t.init = sti_usb_phy_init,\n+\t.exit = sti_usb_phy_exit,\n+};\n+\n+int sti_usb_phy_probe(struct udevice *dev)\n+{\n+\tstruct sti_usb_phy *priv = dev_get_priv(dev);\n+\tstruct udevice *syscon;\n+\tstruct ofnode_phandle_args syscfg_phandle;\n+\tu32 cells[PHYPARAM_NB];\n+\tint ret, count;\n+\n+\t/* get corresponding syscon phandle */\n+\tret = dev_read_phandle_with_args(dev, \"st,syscfg\", NULL, 0, 0,\n+\t\t\t\t\t &syscfg_phandle);\n+\n+\tif (ret < 0) {\n+\t\terror(\"Can't get syscfg phandle: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,\n+\t\t\t\t\t &syscon);\n+\tif (ret) {\n+\t\terror(\"unable to find syscon device (%d)\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tpriv->regmap = syscon_get_regmap(syscon);\n+\tif (!priv->regmap) {\n+\t\terror(\"unable to find regmap\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\t/* get phy param offset */\n+\tcount = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev),\n+\t\t\t\t\t \"st,syscfg\", cells,\n+\t\t\t\t\t ARRAY_SIZE(cells));\n+\n+\tif (count < 0) {\n+\t\terror(\"Bad PHY st,syscfg property %d\\n\", count);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (count > PHYPARAM_NB) {\n+\t\terror(\"Unsupported PHY param count %d\\n\", count);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpriv->param = cells[PHYPARAM_REG];\n+\tpriv->ctrl = cells[PHYCTRL_REG];\n+\n+\t/* get global reset control */\n+\tret = reset_get_by_name(dev, \"global\", &priv->global_ctl);\n+\tif (ret) {\n+\t\terror(\"can't get global reset for %s (%d)\", dev->name, ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* get port reset control */\n+\tret = reset_get_by_name(dev, \"port\", &priv->port_ctl);\n+\tif (ret) {\n+\t\terror(\"can't get port reset for %s (%d)\", dev->name, ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct udevice_id sti_usb_phy_ids[] = {\n+\t{ .compatible = \"st,stih407-usb2-phy\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(sti_usb_phy) = {\n+\t.name = \"sti_usb_phy\",\n+\t.id = UCLASS_PHY,\n+\t.of_match = sti_usb_phy_ids,\n+\t.probe = sti_usb_phy_probe,\n+\t.ops = &sti_usb_phy_ops,\n+\t.priv_auto_alloc_size = sizeof(struct sti_usb_phy),\n+};\n", "prefixes": [ "U-Boot", "v10", "04/10" ] }