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GET /api/patches/810020/?format=api
{ "id": 810020, "url": "http://patchwork.ozlabs.org/api/patches/810020/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504602267-31283-8-git-send-email-patrice.chotard@st.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504602267-31283-8-git-send-email-patrice.chotard@st.com>", "list_archive_url": null, "date": "2017-09-05T09:04:24", "name": "[U-Boot,v10,07/10] usb: dwc3: Add dwc3 glue driver support for STi", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "6a84c5ca6e86f6195f52a3d0a94c433772d07a9d", "submitter": { "id": 63958, "url": "http://patchwork.ozlabs.org/api/people/63958/?format=api", "name": "Patrice CHOTARD", "email": "patrice.chotard@st.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504602267-31283-8-git-send-email-patrice.chotard@st.com/mbox/", "series": [ { "id": 1524, "url": "http://patchwork.ozlabs.org/api/series/1524/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1524", "date": "2017-09-05T09:04:18", "name": "STiH410-B2260: add reset, usb and fastboot support", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/1524/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810020/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810020/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmgtW2v2jz9s03\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 5 Sep 2017 19:10:59 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 04BD9C21DE1; Tue, 5 Sep 2017 09:09:23 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id D5184C21F49;\n\tTue, 5 Sep 2017 09:08:49 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 81ECDC21F2F; Tue, 5 Sep 2017 09:06:07 +0000 (UTC)", "from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com\n\t[91.207.212.93])\n\tby lists.denx.de (Postfix) with ESMTPS id CE8E3C21FA8\n\tfor <u-boot@lists.denx.de>; Tue, 5 Sep 2017 09:04:49 +0000 (UTC)", "from pps.filterd (m0046661.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv857cqA2019865; Tue, 5 Sep 2017 11:04:37 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2crp3j8pa5-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tTue, 05 Sep 2017 11:04:37 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A916E49;\n\tTue, 5 Sep 2017 09:04:35 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8A30B15F0;\n\tTue, 5 Sep 2017 09:04:35 +0000 (GMT)", "from localhost (10.75.127.44) by SFHDAG6NODE3.st.com (10.75.127.18)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tTue, 5 Sep 2017 11:04:34 +0200" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "From": "<patrice.chotard@st.com>", "To": "<u-boot@lists.denx.de>, <albert.u.boot@aribaud.net>, <sjg@chromium.org>, \n\t<jh80.chung@samsung.com>, <marex@denx.de>", "Date": "Tue, 5 Sep 2017 11:04:24 +0200", "Message-ID": "<1504602267-31283-8-git-send-email-patrice.chotard@st.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1504602267-31283-1-git-send-email-patrice.chotard@st.com>", "References": "<1504602267-31283-1-git-send-email-patrice.chotard@st.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.75.127.44]", "X-ClientProxiedBy": "SFHDAG5NODE3.st.com (10.75.127.15) To SFHDAG6NODE3.st.com\n\t(10.75.127.18)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-05_03:, , signatures=0", "Subject": "[U-Boot] [PATCH v10 07/10] usb: dwc3: Add dwc3 glue driver support\n\tfor STi", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Patrice Chotard <patrice.chotard@st.com>\n\nThis patch adds the ST glue logic to manage the DWC3 HC\non STiH407 SoC family. It configures the internal glue\nlogic and syscfg registers.\n\nPart of this code been extracted from kernel.org driver\n(drivers/usb/dwc3/dwc3-st.c)\n\nSigned-off-by: Patrice Chotard <patrice.chotard@st.com>\nReviewed-by: Simon Glass <sjg@chromium.org>\n---\nv10:\t_ none\nv9:\t_ move inclusion of linux/usb/otg.h from include/dwc3-sti-glue.h to \n\t drivers/usb/host/dwc3-sti-glue.c requested by Marek Vasut\nv8:\t_ update failpath label names in sti_dwc3_glue_probe()\nv7:\t_ none\nv6:\t_ add reviewed-by Simon Glass\n\t_ put #define <common.h> first\nv5:\t_ none\nv4:\t_ none\nv3:\t_ rename dwc3-sti.c to dwc3-sti-glue.c\n\t respect device tree hierarchy, this driver is now responsible\n:\t for xhci-sti binding (done in sti_dwc3_glue_bind())\nv2:\t_ use setbits_le32() instead of read, modify, write sequence\n\t add missing parenthesis\n\n\n\n arch/arm/include/asm/arch-stih410/sys_proto.h | 11 ++\n doc/device-tree-bindings/usb/dwc3-st.txt | 60 ++++++\n drivers/usb/host/Kconfig | 9 +\n drivers/usb/host/Makefile | 1 +\n drivers/usb/host/dwc3-sti-glue.c | 257 ++++++++++++++++++++++++++\n include/dwc3-sti-glue.h | 41 ++++\n 6 files changed, 379 insertions(+)\n create mode 100644 arch/arm/include/asm/arch-stih410/sys_proto.h\n create mode 100644 doc/device-tree-bindings/usb/dwc3-st.txt\n create mode 100644 drivers/usb/host/dwc3-sti-glue.c\n create mode 100644 include/dwc3-sti-glue.h", "diff": "diff --git a/arch/arm/include/asm/arch-stih410/sys_proto.h b/arch/arm/include/asm/arch-stih410/sys_proto.h\nnew file mode 100644\nindex 0000000..5c40d3b\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-stih410/sys_proto.h\n@@ -0,0 +1,11 @@\n+/*\n+ * Copyright (c) 2017\n+ * Patrice Chotard <patrice.chotard@st.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef _ASM_ARCH_SYS_PROTO_H\n+#define _ASM_ARCH_SYS_PROTO_H\n+\n+#endif /* _ASM_ARCH_SYS_PROTO_H */\ndiff --git a/doc/device-tree-bindings/usb/dwc3-st.txt b/doc/device-tree-bindings/usb/dwc3-st.txt\nnew file mode 100644\nindex 0000000..a26a139\n--- /dev/null\n+++ b/doc/device-tree-bindings/usb/dwc3-st.txt\n@@ -0,0 +1,60 @@\n+ST DWC3 glue logic\n+\n+This file documents the parameters for the dwc3-st driver.\n+This driver controls the glue logic used to configure the dwc3 core on\n+STiH407 based platforms.\n+\n+Required properties:\n+ - compatible\t: must be \"st,stih407-dwc3\"\n+ - reg\t\t: glue logic base address and USB syscfg ctrl register offset\n+ - reg-names\t: should be \"reg-glue\" and \"syscfg-reg\"\n+ - st,syscon\t: should be phandle to system configuration node which\n+\t\t encompasses the glue registers\n+ - resets\t: list of phandle and reset specifier pairs. There should be two entries, one\n+\t\t for the powerdown and softreset lines of the usb3 IP\n+ - reset-names\t: list of reset signal names. Names should be \"powerdown\" and \"softreset\"\n+\n+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes\n+ with 'reg' property\n+\n+ - pinctl-names\t: A pinctrl state named \"default\" must be defined\n+\n+ - pinctrl-0\t: Pin control group\n+\n+ - ranges\t: allows valid 1:1 translation between child's address space and\n+\t\t parent's address space\n+\n+Sub-nodes:\n+The dwc3 core should be added as subnode to ST DWC3 glue as shown in the\n+example below.\n+\n+NB: The dr_mode property is NOT optional for this driver, as the default value\n+is \"otg\", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are\n+either \"host\" or \"device\".\n+\n+Example:\n+\n+st_dwc3: dwc3@8f94000 {\n+\tstatus\t\t= \"disabled\";\n+\tcompatible\t= \"st,stih407-dwc3\";\n+\treg\t\t= <0x08f94000 0x1000>, <0x110 0x4>;\n+\treg-names\t= \"reg-glue\", \"syscfg-reg\";\n+\tst,syscfg\t= <&syscfg_core>;\n+\tresets\t\t= <&powerdown STIH407_USB3_POWERDOWN>,\n+\t\t\t <&softreset STIH407_MIPHY2_SOFTRESET>;\n+\treset-names\t= \"powerdown\", \"softreset\";\n+\t#address-cells\t= <1>;\n+\t#size-cells\t= <1>;\n+\tpinctrl-names\t= \"default\";\n+\tpinctrl-0\t= <&pinctrl_usb3>;\n+\tranges;\n+\n+\tdwc3: dwc3@9900000 {\n+\t\tcompatible\t= \"snps,dwc3\";\n+\t\treg\t\t= <0x09900000 0x100000>;\n+\t\tinterrupts\t= <GIC_SPI 155 IRQ_TYPE_NONE>;\n+\t\tdr_mode\t\t= \"host\";\n+\t\tphy-names\t= \"usb2-phy\", \"usb3-phy\";\n+\t\tphys\t\t= <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>;\n+\t};\n+};\ndiff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig\nindex eb035a4..f797a25 100644\n--- a/drivers/usb/host/Kconfig\n+++ b/drivers/usb/host/Kconfig\n@@ -47,6 +47,15 @@ config USB_XHCI_ROCKCHIP\n \thelp\n \t Enables support for the on-chip xHCI controller on Rockchip SoCs.\n \n+config USB_XHCI_STI\n+\tbool \"Support for STMicroelectronics STiH407 family on-chip xHCI USB controller\"\n+\tdepends on ARCH_STI\n+\tdefault y\n+\thelp\n+\t Enables support for the on-chip xHCI controller on STMicroelectronics\n+\t STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic\n+\t to configure the controller.\n+\n config USB_XHCI_ZYNQMP\n \tbool \"Support for Xilinx ZynqMP on-chip xHCI USB controller\"\n \tdepends on ARCH_ZYNQMP\ndiff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile\nindex ab5a99f..29afb7c 100644\n--- a/drivers/usb/host/Makefile\n+++ b/drivers/usb/host/Makefile\n@@ -60,6 +60,7 @@ obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o\n obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o\n obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o\n obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o\n+obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o\n \n # designware\n obj-$(CONFIG_USB_DWC2) += dwc2.o\ndiff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c\nnew file mode 100644\nindex 0000000..02ad311\n--- /dev/null\n+++ b/drivers/usb/host/dwc3-sti-glue.c\n@@ -0,0 +1,257 @@\n+/*\n+ * STiH407 family DWC3 specific Glue layer\n+ *\n+ * Copyright (c) 2017\n+ * Patrice Chotard <patrice.chotard@st.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/io.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <fdtdec.h>\n+#include <libfdt.h>\n+#include <dm/lists.h>\n+#include <regmap.h>\n+#include <reset-uclass.h>\n+#include <syscon.h>\n+#include <usb.h>\n+\n+#include <linux/usb/dwc3.h>\n+#include <linux/usb/otg.h>\n+#include <dwc3-sti-glue.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+/*\n+ * struct sti_dwc3_glue_platdata - dwc3 STi glue driver private structure\n+ * @syscfg_base:\taddr for the glue syscfg\n+ * @glue_base:\t\taddr for the glue registers\n+ * @syscfg_offset:\tusb syscfg control offset\n+ * @powerdown_ctl:\trest controller for powerdown signal\n+ * @softreset_ctl:\treset controller for softreset signal\n+ * @mode:\t\tdrd static host/device config\n+ */\n+struct sti_dwc3_glue_platdata {\n+\tphys_addr_t syscfg_base;\n+\tphys_addr_t glue_base;\n+\tphys_addr_t syscfg_offset;\n+\tstruct reset_ctl powerdown_ctl;\n+\tstruct reset_ctl softreset_ctl;\n+\tenum usb_dr_mode mode;\n+};\n+\n+static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_platdata *plat)\n+{\n+\tunsigned long val;\n+\n+\tval = readl(plat->syscfg_base + plat->syscfg_offset);\n+\n+\tval &= USB3_CONTROL_MASK;\n+\n+\tswitch (plat->mode) {\n+\tcase USB_DR_MODE_PERIPHERAL:\n+\t\tval &= ~(USB3_DELAY_VBUSVALID\n+\t\t\t| USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)\n+\t\t\t| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2\n+\t\t\t| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);\n+\n+\t\tval |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;\n+\t\tbreak;\n+\n+\tcase USB_DR_MODE_HOST:\n+\t\tval &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID\n+\t\t\t| USB3_SEL_FORCE_OPMODE\t| USB3_FORCE_OPMODE(0x3)\n+\t\t\t| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2\n+\t\t\t| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);\n+\n+\t\tval |= USB3_DELAY_VBUSVALID;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\terror(\"Unsupported mode of operation %d\\n\", plat->mode);\n+\t\treturn -EINVAL;\n+\t}\n+\twritel(val, plat->syscfg_base + plat->syscfg_offset);\n+\n+\treturn 0;\n+}\n+\n+static void sti_dwc3_glue_init(struct sti_dwc3_glue_platdata *plat)\n+{\n+\tunsigned long reg;\n+\n+\treg = readl(plat->glue_base + CLKRST_CTRL);\n+\n+\treg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;\n+\treg &= ~SW_PIPEW_RESET_N;\n+\n+\twritel(reg, plat->glue_base + CLKRST_CTRL);\n+\n+\t/* configure mux for vbus, powerpresent and bvalid signals */\n+\treg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1);\n+\n+\treg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |\n+\t SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |\n+\t SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG);\n+\n+\twritel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1);\n+\n+\tsetbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);\n+}\n+\n+static int sti_dwc3_glue_ofdata_to_platdata(struct udevice *dev)\n+{\n+\tstruct sti_dwc3_glue_platdata *plat = dev_get_platdata(dev);\n+\tstruct udevice *syscon;\n+\tstruct regmap *regmap;\n+\tint ret;\n+\tu32 reg[4];\n+\n+\tret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),\n+\t\t\t\t \"reg\", reg, ARRAY_SIZE(reg));\n+\tif (ret) {\n+\t\terror(\"unable to find st,stih407-dwc3 reg property(%d)\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tplat->glue_base = reg[0];\n+\tplat->syscfg_offset = reg[2];\n+\n+\t/* get corresponding syscon phandle */\n+\tret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, \"st,syscfg\",\n+\t\t\t\t\t &syscon);\n+\tif (ret) {\n+\t\terror(\"unable to find syscon device (%d)\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* get syscfg-reg base address */\n+\tregmap = syscon_get_regmap(syscon);\n+\tif (!regmap) {\n+\t\terror(\"unable to find regmap\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\tplat->syscfg_base = regmap->base;\n+\n+\t/* get powerdown reset */\n+\tret = reset_get_by_name(dev, \"powerdown\", &plat->powerdown_ctl);\n+\tif (ret) {\n+\t\terror(\"can't get powerdown reset for %s (%d)\", dev->name, ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* get softreset reset */\n+\tret = reset_get_by_name(dev, \"softreset\", &plat->softreset_ctl);\n+\tif (ret)\n+\t\terror(\"can't get soft reset for %s (%d)\", dev->name, ret);\n+\n+\treturn ret;\n+};\n+\n+static int sti_dwc3_glue_bind(struct udevice *dev)\n+{\n+\tstruct sti_dwc3_glue_platdata *plat = dev_get_platdata(dev);\n+\tint dwc3_node;\n+\n+\t/* check if one subnode is present */\n+\tdwc3_node = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));\n+\tif (dwc3_node <= 0) {\n+\t\terror(\"Can't find subnode for %s\\n\", dev->name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\t/* check if the subnode compatible string is the dwc3 one*/\n+\tif (fdt_node_check_compatible(gd->fdt_blob, dwc3_node,\n+\t\t\t\t \"snps,dwc3\") != 0) {\n+\t\terror(\"Can't find dwc3 subnode for %s\\n\", dev->name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\t/* retrieve the DWC3 dual role mode */\n+\tplat->mode = usb_get_dr_mode(dwc3_node);\n+\tif (plat->mode == USB_DR_MODE_UNKNOWN)\n+\t\t/* by default set dual role mode to HOST */\n+\t\tplat->mode = USB_DR_MODE_HOST;\n+\n+\treturn dm_scan_fdt_dev(dev);\n+}\n+\n+static int sti_dwc3_glue_probe(struct udevice *dev)\n+{\n+\tstruct sti_dwc3_glue_platdata *plat = dev_get_platdata(dev);\n+\tint ret;\n+\n+\t/* deassert both powerdown and softreset */\n+\tret = reset_deassert(&plat->powerdown_ctl);\n+\tif (ret < 0) {\n+\t\terror(\"DWC3 powerdown reset deassert failed: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = reset_deassert(&plat->softreset_ctl);\n+\tif (ret < 0) {\n+\t\terror(\"DWC3 soft reset deassert failed: %d\", ret);\n+\t\tgoto softreset_err;\n+\t}\n+\n+\tret = sti_dwc3_glue_drd_init(plat);\n+\tif (ret)\n+\t\tgoto init_err;\n+\n+\tsti_dwc3_glue_init(plat);\n+\n+\treturn 0;\n+\n+init_err:\n+\tret = reset_assert(&plat->softreset_ctl);\n+\tif (ret < 0) {\n+\t\terror(\"DWC3 soft reset deassert failed: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+softreset_err:\n+\tret = reset_assert(&plat->powerdown_ctl);\n+\tif (ret < 0)\n+\t\terror(\"DWC3 powerdown reset deassert failed: %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int sti_dwc3_glue_remove(struct udevice *dev)\n+{\n+\tstruct sti_dwc3_glue_platdata *plat = dev_get_platdata(dev);\n+\tint ret;\n+\n+\t/* assert both powerdown and softreset */\n+\tret = reset_assert(&plat->powerdown_ctl);\n+\tif (ret < 0) {\n+\t\terror(\"DWC3 powerdown reset deassert failed: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = reset_assert(&plat->softreset_ctl);\n+\tif (ret < 0)\n+\t\terror(\"DWC3 soft reset deassert failed: %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static const struct udevice_id sti_dwc3_glue_ids[] = {\n+\t{ .compatible = \"st,stih407-dwc3\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(dwc3_sti_glue) = {\n+\t.name = \"dwc3_sti_glue\",\n+\t.id = UCLASS_MISC,\n+\t.of_match = sti_dwc3_glue_ids,\n+\t.ofdata_to_platdata = sti_dwc3_glue_ofdata_to_platdata,\n+\t.probe = sti_dwc3_glue_probe,\n+\t.remove = sti_dwc3_glue_remove,\n+\t.bind = sti_dwc3_glue_bind,\n+\t.platdata_auto_alloc_size = sizeof(struct sti_dwc3_glue_platdata),\n+\t.flags = DM_FLAG_ALLOC_PRIV_DMA,\n+};\ndiff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h\nnew file mode 100644\nindex 0000000..98e7696\n--- /dev/null\n+++ b/include/dwc3-sti-glue.h\n@@ -0,0 +1,41 @@\n+/*\n+ * Copyright (c) 2017\n+ * Patrice Chotard <patrice.chotard@st.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __DWC3_STI_UBOOT_H_\n+#define __DWC3_STI_UBOOT_H_\n+\n+/* glue registers */\n+#define CLKRST_CTRL\t\t0x00\n+#define AUX_CLK_EN\t\tBIT(0)\n+#define SW_PIPEW_RESET_N\tBIT(4)\n+#define EXT_CFG_RESET_N\t\tBIT(8)\n+\n+#define XHCI_REVISION\t\tBIT(12)\n+\n+#define USB2_VBUS_MNGMNT_SEL1\t0x2C\n+#define USB2_VBUS_UTMIOTG\t0x1\n+\n+#define SEL_OVERRIDE_VBUSVALID(n)\t((n) << 0)\n+#define SEL_OVERRIDE_POWERPRESENT(n)\t((n) << 4)\n+#define SEL_OVERRIDE_BVALID(n)\t\t((n) << 8)\n+\n+/* Static DRD configuration */\n+#define USB3_CONTROL_MASK\t\t0xf77\n+\n+#define USB3_DEVICE_NOT_HOST\t\tBIT(0)\n+#define USB3_FORCE_VBUSVALID\t\tBIT(1)\n+#define USB3_DELAY_VBUSVALID\t\tBIT(2)\n+#define USB3_SEL_FORCE_OPMODE\t\tBIT(4)\n+#define USB3_FORCE_OPMODE(n)\t\t((n) << 5)\n+#define USB3_SEL_FORCE_DPPULLDOWN2\tBIT(8)\n+#define USB3_FORCE_DPPULLDOWN2\t\tBIT(9)\n+#define USB3_SEL_FORCE_DMPULLDOWN2\tBIT(10)\n+#define USB3_FORCE_DMPULLDOWN2\t\tBIT(11)\n+\n+int sti_dwc3_init(enum usb_dr_mode mode);\n+\n+#endif /* __DWC3_STI_UBOOT_H_ */\n", "prefixes": [ "U-Boot", "v10", "07/10" ] }