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{
    "id": 810006,
    "url": "http://patchwork.ozlabs.org/api/patches/810006/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20170905084306.19318-6-mperttunen@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170905084306.19318-6-mperttunen@nvidia.com>",
    "list_archive_url": null,
    "date": "2017-09-05T08:43:05",
    "name": "[v2,5/6] gpu: host1x: Add Tegra186 support",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "4af66001e8c5b9d5a0d5896f99c4d687779738b4",
    "submitter": {
        "id": 26499,
        "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api",
        "name": "Mikko Perttunen",
        "email": "mperttunen@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20170905084306.19318-6-mperttunen@nvidia.com/mbox/",
    "series": [
        {
            "id": 1515,
            "url": "http://patchwork.ozlabs.org/api/series/1515/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=1515",
            "date": "2017-09-05T08:43:06",
            "name": "Host1x and VIC support for Tegra186",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/1515/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/810006/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/810006/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-tegra-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": [
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        ],
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmgJL6Ns7z9sNq\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue,  5 Sep 2017 18:44:50 +1000 (AEST)",
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            "from dsl-hkibng41-567306-181.dhcp.inet.fi ([86.115.6.181]\n\thelo=localhost.localdomain) by mail.kapsi.fi with esmtpsa\n\t(TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2)\n\t(envelope-from <mperttunen@nvidia.com>)\n\tid 1dp9SM-0005vW-Q4; Tue, 05 Sep 2017 11:43:39 +0300"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kapsi.fi;\n\ts=20161220; \n\th=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From;\n\tbh=VenIZjhlM65zJ7zPpZ/HeZFaN8TyZGrhKaeRnszhohs=; \n\tb=DeBjRqm+tQZeeHh4w1yVmrTiLiAZILj2aW0KIq3zXAAcluL1++xGIiCWs5v5ffI4aavBH0tVYwE3nJ1OniCkVwn+wiC82OOpOSnVOjblDVzy3qulmo0JUw3QVzaZHkewK5SLrSGy4A6xn6yXQJNxEl0HmIPIZ1IRM23m9FBxmXsCRwSjdDzLei+LBah4RrSPUgZOTa6eN06FJckC3ouPnaTsPJe8SS1yad7tm/EZjNua4aftrDrPrt72E1EgJtaFu3nPPxF1eRtSL5KWNSpGk2qX1yfwp8VHLJEJyFGPup1aL5Y0ZAurY8dqpXzfZs9koAIDZCsDmgEGNchbe73pAg==;",
        "From": "Mikko Perttunen <mperttunen@nvidia.com>",
        "To": "thierry.reding@gmail.com, jonathanh@nvidia.com, robh+dt@kernel.org,\n\tmark.rutland@arm.com",
        "Cc": "digetx@gmail.com, amerilainen@nvidia.com, dnibade@nvidia.com,\n\tsgurrappadi@nvidia.com, dri-devel@lists.freedesktop.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tMikko Perttunen <mperttunen@nvidia.com>",
        "Subject": "[PATCH v2 5/6] gpu: host1x: Add Tegra186 support",
        "Date": "Tue,  5 Sep 2017 11:43:05 +0300",
        "Message-Id": "<20170905084306.19318-6-mperttunen@nvidia.com>",
        "X-Mailer": "git-send-email 2.14.1",
        "In-Reply-To": "<20170905084306.19318-1-mperttunen@nvidia.com>",
        "References": "<20170905084306.19318-1-mperttunen@nvidia.com>",
        "X-SA-Exim-Connect-IP": "86.115.6.181",
        "X-SA-Exim-Mail-From": "mperttunen@nvidia.com",
        "X-SA-Exim-Scanned": "No (on mail.kapsi.fi); SAEximRunCond expanded to false",
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "Add support for the implementation of Host1x present on the Tegra186.\nThe register space has been shuffled around a little bit, requiring\naddition of some chip-specific code sections. Tegra186 also adds\nseveral new features, most importantly the hypervisor, but those are\nnot yet supported with this commit.\n\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\nReviewed-by: Dmitry Osipenko <digetx@gmail.com>\nTested-by: Dmitry Osipenko <digetx@gmail.com>\n---\n drivers/gpu/host1x/Makefile                    |   3 +-\n drivers/gpu/host1x/dev.c                       |  60 +++++++-\n drivers/gpu/host1x/dev.h                       |   4 +\n drivers/gpu/host1x/hw/cdma_hw.c                |  49 ++++---\n drivers/gpu/host1x/hw/debug_hw.c               | 137 +------------------\n drivers/gpu/host1x/hw/debug_hw_1x01.c          | 154 +++++++++++++++++++++\n drivers/gpu/host1x/hw/debug_hw_1x06.c          | 133 ++++++++++++++++++\n drivers/gpu/host1x/hw/host1x01.c               |   2 +\n drivers/gpu/host1x/hw/host1x02.c               |   2 +\n drivers/gpu/host1x/hw/host1x04.c               |   2 +\n drivers/gpu/host1x/hw/host1x05.c               |   2 +\n drivers/gpu/host1x/hw/host1x06.c               |  44 ++++++\n drivers/gpu/host1x/hw/host1x06.h               |  26 ++++\n drivers/gpu/host1x/hw/host1x06_hardware.h      | 142 +++++++++++++++++++\n drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h |  32 +++++\n drivers/gpu/host1x/hw/hw_host1x06_uclass.h     | 181 +++++++++++++++++++++++++\n drivers/gpu/host1x/hw/hw_host1x06_vm.h         |  47 +++++++\n drivers/gpu/host1x/hw/intr_hw.c                |  29 ++--\n 18 files changed, 880 insertions(+), 169 deletions(-)\n create mode 100644 drivers/gpu/host1x/hw/debug_hw_1x01.c\n create mode 100644 drivers/gpu/host1x/hw/debug_hw_1x06.c\n create mode 100644 drivers/gpu/host1x/hw/host1x06.c\n create mode 100644 drivers/gpu/host1x/hw/host1x06.h\n create mode 100644 drivers/gpu/host1x/hw/host1x06_hardware.h\n create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h\n create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_uclass.h\n create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_vm.h",
    "diff": "diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile\nindex a1d9974cfcb5..4fb61bd57aee 100644\n--- a/drivers/gpu/host1x/Makefile\n+++ b/drivers/gpu/host1x/Makefile\n@@ -11,6 +11,7 @@ host1x-y = \\\n \thw/host1x01.o \\\n \thw/host1x02.o \\\n \thw/host1x04.o \\\n-\thw/host1x05.o\n+\thw/host1x05.o \\\n+\thw/host1x06.o\n \n obj-$(CONFIG_TEGRA_HOST1X) += host1x.o\ndiff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c\nindex 2c58a390123a..6a4ff2d59496 100644\n--- a/drivers/gpu/host1x/dev.c\n+++ b/drivers/gpu/host1x/dev.c\n@@ -39,6 +39,17 @@\n #include \"hw/host1x02.h\"\n #include \"hw/host1x04.h\"\n #include \"hw/host1x05.h\"\n+#include \"hw/host1x06.h\"\n+\n+void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)\n+{\n+\twritel(v, host1x->hv_regs + r);\n+}\n+\n+u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)\n+{\n+\treturn readl(host1x->hv_regs + r);\n+}\n \n void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)\n {\n@@ -104,7 +115,19 @@ static const struct host1x_info host1x05_info = {\n \t.dma_mask = DMA_BIT_MASK(34),\n };\n \n+static const struct host1x_info host1x06_info = {\n+\t.nb_channels = 63,\n+\t.nb_pts = 576,\n+\t.nb_mlocks = 24,\n+\t.nb_bases = 16,\n+\t.init = host1x06_init,\n+\t.sync_offset = 0x0,\n+\t.dma_mask = DMA_BIT_MASK(34),\n+\t.has_hypervisor = true,\n+};\n+\n static const struct of_device_id host1x_of_match[] = {\n+\t{ .compatible = \"nvidia,tegra186-host1x\", .data = &host1x06_info, },\n \t{ .compatible = \"nvidia,tegra210-host1x\", .data = &host1x05_info, },\n \t{ .compatible = \"nvidia,tegra124-host1x\", .data = &host1x04_info, },\n \t{ .compatible = \"nvidia,tegra114-host1x\", .data = &host1x02_info, },\n@@ -117,8 +140,9 @@ MODULE_DEVICE_TABLE(of, host1x_of_match);\n static int host1x_probe(struct platform_device *pdev)\n {\n \tconst struct of_device_id *id;\n+\tconst struct host1x_info *info;\n \tstruct host1x *host;\n-\tstruct resource *regs;\n+\tstruct resource *regs, *hv_regs = NULL;\n \tint syncpt_irq;\n \tint err;\n \n@@ -126,10 +150,28 @@ static int host1x_probe(struct platform_device *pdev)\n \tif (!id)\n \t\treturn -EINVAL;\n \n-\tregs = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n-\tif (!regs) {\n-\t\tdev_err(&pdev->dev, \"failed to get registers\\n\");\n-\t\treturn -ENXIO;\n+\tinfo = id->data;\n+\n+\tif (info->has_hypervisor) {\n+\t\tregs = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"vm\");\n+\t\tif (!regs) {\n+\t\t\tdev_err(&pdev->dev, \"failed to get vm registers\\n\");\n+\t\t\treturn -ENXIO;\n+\t\t}\n+\n+\t\thv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n+\t\t\t\t\t\t       \"hypervisor\");\n+\t\tif (!hv_regs) {\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"failed to get hypervisor registers\\n\");\n+\t\t\treturn -ENXIO;\n+\t\t}\n+\t} else {\n+\t\tregs = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\t\tif (!regs) {\n+\t\t\tdev_err(&pdev->dev, \"failed to get registers\\n\");\n+\t\t\treturn -ENXIO;\n+\t\t}\n \t}\n \n \tsyncpt_irq = platform_get_irq(pdev, 0);\n@@ -146,7 +188,7 @@ static int host1x_probe(struct platform_device *pdev)\n \tINIT_LIST_HEAD(&host->devices);\n \tINIT_LIST_HEAD(&host->list);\n \thost->dev = &pdev->dev;\n-\thost->info = id->data;\n+\thost->info = info;\n \n \t/* set common host1x device data */\n \tplatform_set_drvdata(pdev, host);\n@@ -155,6 +197,12 @@ static int host1x_probe(struct platform_device *pdev)\n \tif (IS_ERR(host->regs))\n \t\treturn PTR_ERR(host->regs);\n \n+\tif (info->has_hypervisor) {\n+\t\thost->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);\n+\t\tif (IS_ERR(host->hv_regs))\n+\t\t\treturn PTR_ERR(host->hv_regs);\n+\t}\n+\n \tdma_set_mask_and_coherent(host->dev, host->info->dma_mask);\n \n \tif (host->info->init) {\ndiff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h\nindex ffdbc15b749b..def802c0a6bf 100644\n--- a/drivers/gpu/host1x/dev.h\n+++ b/drivers/gpu/host1x/dev.h\n@@ -100,12 +100,14 @@ struct host1x_info {\n \tint (*init)(struct host1x *host1x); /* initialize per SoC ops */\n \tunsigned int sync_offset; /* offset of syncpoint registers */\n \tu64 dma_mask; /* mask of addressable memory */\n+\tbool has_hypervisor; /* has hypervisor registers */\n };\n \n struct host1x {\n \tconst struct host1x_info *info;\n \n \tvoid __iomem *regs;\n+\tvoid __iomem *hv_regs; /* hypervisor region */\n \tstruct host1x_syncpt *syncpt;\n \tstruct host1x_syncpt_base *bases;\n \tstruct device *dev;\n@@ -140,6 +142,8 @@ struct host1x {\n \tstruct list_head list;\n };\n \n+void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v);\n+u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r);\n void host1x_sync_writel(struct host1x *host1x, u32 r, u32 v);\n u32 host1x_sync_readl(struct host1x *host1x, u32 r);\n void host1x_ch_writel(struct host1x_channel *ch, u32 r, u32 v);\ndiff --git a/drivers/gpu/host1x/hw/cdma_hw.c b/drivers/gpu/host1x/hw/cdma_hw.c\nindex 6b231119193e..ce320534cbed 100644\n--- a/drivers/gpu/host1x/hw/cdma_hw.c\n+++ b/drivers/gpu/host1x/hw/cdma_hw.c\n@@ -172,6 +172,30 @@ static void cdma_stop(struct host1x_cdma *cdma)\n \tmutex_unlock(&cdma->lock);\n }\n \n+static void cdma_hw_cmdproc_stop(struct host1x *host, struct host1x_channel *ch,\n+\t\t\t\t bool stop)\n+{\n+#if HOST1X_HW >= 6\n+\thost1x_ch_writel(ch, stop ? 0x1 : 0x0, HOST1X_CHANNEL_CMDPROC_STOP);\n+#else\n+\tu32 cmdproc_stop = host1x_sync_readl(host, HOST1X_SYNC_CMDPROC_STOP);\n+\tif (stop)\n+\t\tcmdproc_stop |= BIT(ch->id);\n+\telse\n+\t\tcmdproc_stop &= ~BIT(ch->id);\n+\thost1x_sync_writel(host, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP);\n+#endif\n+}\n+\n+static void cdma_hw_teardown(struct host1x *host, struct host1x_channel *ch)\n+{\n+#if HOST1X_HW >= 6\n+\thost1x_ch_writel(ch, 0x1, HOST1X_CHANNEL_TEARDOWN);\n+#else\n+\thost1x_sync_writel(host, BIT(ch->id), HOST1X_SYNC_CH_TEARDOWN);\n+#endif\n+}\n+\n /*\n  * Stops both channel's command processor and CDMA immediately.\n  * Also, tears down the channel and resets corresponding module.\n@@ -180,7 +204,6 @@ static void cdma_freeze(struct host1x_cdma *cdma)\n {\n \tstruct host1x *host = cdma_to_host1x(cdma);\n \tstruct host1x_channel *ch = cdma_to_channel(cdma);\n-\tu32 cmdproc_stop;\n \n \tif (cdma->torndown && !cdma->running) {\n \t\tdev_warn(host->dev, \"Already torn down\\n\");\n@@ -189,9 +212,7 @@ static void cdma_freeze(struct host1x_cdma *cdma)\n \n \tdev_dbg(host->dev, \"freezing channel (id %d)\\n\", ch->id);\n \n-\tcmdproc_stop = host1x_sync_readl(host, HOST1X_SYNC_CMDPROC_STOP);\n-\tcmdproc_stop |= BIT(ch->id);\n-\thost1x_sync_writel(host, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP);\n+\tcdma_hw_cmdproc_stop(host, ch, true);\n \n \tdev_dbg(host->dev, \"%s: DMA GET 0x%x, PUT HW 0x%x / shadow 0x%x\\n\",\n \t\t__func__, host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET),\n@@ -201,7 +222,7 @@ static void cdma_freeze(struct host1x_cdma *cdma)\n \thost1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP,\n \t\t\t HOST1X_CHANNEL_DMACTRL);\n \n-\thost1x_sync_writel(host, BIT(ch->id), HOST1X_SYNC_CH_TEARDOWN);\n+\tcdma_hw_teardown(host, ch);\n \n \tcdma->running = false;\n \tcdma->torndown = true;\n@@ -211,15 +232,12 @@ static void cdma_resume(struct host1x_cdma *cdma, u32 getptr)\n {\n \tstruct host1x *host1x = cdma_to_host1x(cdma);\n \tstruct host1x_channel *ch = cdma_to_channel(cdma);\n-\tu32 cmdproc_stop;\n \n \tdev_dbg(host1x->dev,\n \t\t\"resuming channel (id %u, DMAGET restart = 0x%x)\\n\",\n \t\tch->id, getptr);\n \n-\tcmdproc_stop = host1x_sync_readl(host1x, HOST1X_SYNC_CMDPROC_STOP);\n-\tcmdproc_stop &= ~BIT(ch->id);\n-\thost1x_sync_writel(host1x, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP);\n+\tcdma_hw_cmdproc_stop(host1x, ch, false);\n \n \tcdma->torndown = false;\n \tcdma_timeout_restart(cdma, getptr);\n@@ -232,7 +250,7 @@ static void cdma_resume(struct host1x_cdma *cdma, u32 getptr)\n  */\n static void cdma_timeout_handler(struct work_struct *work)\n {\n-\tu32 prev_cmdproc, cmdproc_stop, syncpt_val;\n+\tu32 syncpt_val;\n \tstruct host1x_cdma *cdma;\n \tstruct host1x *host1x;\n \tstruct host1x_channel *ch;\n@@ -254,12 +272,7 @@ static void cdma_timeout_handler(struct work_struct *work)\n \t}\n \n \t/* stop processing to get a clean snapshot */\n-\tprev_cmdproc = host1x_sync_readl(host1x, HOST1X_SYNC_CMDPROC_STOP);\n-\tcmdproc_stop = prev_cmdproc | BIT(ch->id);\n-\thost1x_sync_writel(host1x, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP);\n-\n-\tdev_dbg(host1x->dev, \"cdma_timeout: cmdproc was 0x%x is 0x%x\\n\",\n-\t\tprev_cmdproc, cmdproc_stop);\n+\tcdma_hw_cmdproc_stop(host1x, ch, true);\n \n \tsyncpt_val = host1x_syncpt_load(cdma->timeout.syncpt);\n \n@@ -268,9 +281,7 @@ static void cdma_timeout_handler(struct work_struct *work)\n \t\tdev_dbg(host1x->dev,\n \t\t\t\"cdma_timeout: expired, but buffer had completed\\n\");\n \t\t/* restore */\n-\t\tcmdproc_stop = prev_cmdproc & ~(BIT(ch->id));\n-\t\thost1x_sync_writel(host1x, cmdproc_stop,\n-\t\t\t\t   HOST1X_SYNC_CMDPROC_STOP);\n+\t\tcdma_hw_cmdproc_stop(host1x, ch, false);\n \t\tmutex_unlock(&cdma->lock);\n \t\treturn;\n \t}\ndiff --git a/drivers/gpu/host1x/hw/debug_hw.c b/drivers/gpu/host1x/hw/debug_hw.c\nindex 7a4a3286e4a7..770d92e62d69 100644\n--- a/drivers/gpu/host1x/hw/debug_hw.c\n+++ b/drivers/gpu/host1x/hw/debug_hw.c\n@@ -174,138 +174,11 @@ static void show_channel_gathers(struct output *o, struct host1x_cdma *cdma)\n \t}\n }\n \n-static void host1x_debug_show_channel_cdma(struct host1x *host,\n-\t\t\t\t\t   struct host1x_channel *ch,\n-\t\t\t\t\t   struct output *o)\n-{\n-\tstruct host1x_cdma *cdma = &ch->cdma;\n-\tu32 dmaput, dmaget, dmactrl;\n-\tu32 cbstat, cbread;\n-\tu32 val, base, baseval;\n-\n-\tdmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);\n-\tdmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);\n-\tdmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);\n-\tcbread = host1x_sync_readl(host, HOST1X_SYNC_CBREAD(ch->id));\n-\tcbstat = host1x_sync_readl(host, HOST1X_SYNC_CBSTAT(ch->id));\n-\n-\thost1x_debug_output(o, \"%u-%s: \", ch->id, dev_name(ch->dev));\n-\n-\tif (HOST1X_CHANNEL_DMACTRL_DMASTOP_V(dmactrl) ||\n-\t    !ch->cdma.push_buffer.mapped) {\n-\t\thost1x_debug_output(o, \"inactive\\n\\n\");\n-\t\treturn;\n-\t}\n-\n-\tif (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) == HOST1X_CLASS_HOST1X &&\n-\t    HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==\n-\t\t\tHOST1X_UCLASS_WAIT_SYNCPT)\n-\t\thost1x_debug_output(o, \"waiting on syncpt %d val %d\\n\",\n-\t\t\t\t    cbread >> 24, cbread & 0xffffff);\n-\telse if (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) ==\n-\t\t\t\tHOST1X_CLASS_HOST1X &&\n-\t\t HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==\n-\t\t\t\tHOST1X_UCLASS_WAIT_SYNCPT_BASE) {\n-\t\tbase = (cbread >> 16) & 0xff;\n-\t\tbaseval =\n-\t\t\thost1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(base));\n-\t\tval = cbread & 0xffff;\n-\t\thost1x_debug_output(o, \"waiting on syncpt %d val %d (base %d = %d; offset = %d)\\n\",\n-\t\t\t\t    cbread >> 24, baseval + val, base,\n-\t\t\t\t    baseval, val);\n-\t} else\n-\t\thost1x_debug_output(o, \"active class %02x, offset %04x, val %08x\\n\",\n-\t\t\t\t    HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat),\n-\t\t\t\t    HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat),\n-\t\t\t\t    cbread);\n-\n-\thost1x_debug_output(o, \"DMAPUT %08x, DMAGET %08x, DMACTL %08x\\n\",\n-\t\t\t    dmaput, dmaget, dmactrl);\n-\thost1x_debug_output(o, \"CBREAD %08x, CBSTAT %08x\\n\", cbread, cbstat);\n-\n-\tshow_channel_gathers(o, cdma);\n-\thost1x_debug_output(o, \"\\n\");\n-}\n-\n-static void host1x_debug_show_channel_fifo(struct host1x *host,\n-\t\t\t\t\t   struct host1x_channel *ch,\n-\t\t\t\t\t   struct output *o)\n-{\n-\tu32 val, rd_ptr, wr_ptr, start, end;\n-\tunsigned int data_count = 0;\n-\n-\thost1x_debug_output(o, \"%u: fifo:\\n\", ch->id);\n-\n-\tval = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT);\n-\thost1x_debug_output(o, \"FIFOSTAT %08x\\n\", val);\n-\tif (HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(val)) {\n-\t\thost1x_debug_output(o, \"[empty]\\n\");\n-\t\treturn;\n-\t}\n-\n-\thost1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);\n-\thost1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |\n-\t\t\t   HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id),\n-\t\t\t   HOST1X_SYNC_CFPEEK_CTRL);\n-\n-\tval = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_PTRS);\n-\trd_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(val);\n-\twr_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(val);\n-\n-\tval = host1x_sync_readl(host, HOST1X_SYNC_CF_SETUP(ch->id));\n-\tstart = HOST1X_SYNC_CF_SETUP_BASE_V(val);\n-\tend = HOST1X_SYNC_CF_SETUP_LIMIT_V(val);\n-\n-\tdo {\n-\t\thost1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);\n-\t\thost1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |\n-\t\t\t\t   HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id) |\n-\t\t\t\t   HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(rd_ptr),\n-\t\t\t\t   HOST1X_SYNC_CFPEEK_CTRL);\n-\t\tval = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ);\n-\n-\t\tif (!data_count) {\n-\t\t\thost1x_debug_output(o, \"%08x:\", val);\n-\t\t\tdata_count = show_channel_command(o, val);\n-\t\t} else {\n-\t\t\thost1x_debug_output(o, \"%08x%s\", val,\n-\t\t\t\t\t    data_count > 0 ? \", \" : \"])\\n\");\n-\t\t\tdata_count--;\n-\t\t}\n-\n-\t\tif (rd_ptr == end)\n-\t\t\trd_ptr = start;\n-\t\telse\n-\t\t\trd_ptr++;\n-\t} while (rd_ptr != wr_ptr);\n-\n-\tif (data_count)\n-\t\thost1x_debug_output(o, \", ...])\\n\");\n-\thost1x_debug_output(o, \"\\n\");\n-\n-\thost1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);\n-}\n-\n-static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)\n-{\n-\tunsigned int i;\n-\n-\thost1x_debug_output(o, \"---- mlocks ----\\n\");\n-\n-\tfor (i = 0; i < host1x_syncpt_nb_mlocks(host); i++) {\n-\t\tu32 owner =\n-\t\t\thost1x_sync_readl(host, HOST1X_SYNC_MLOCK_OWNER(i));\n-\t\tif (HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(owner))\n-\t\t\thost1x_debug_output(o, \"%u: locked by channel %u\\n\",\n-\t\t\t\ti, HOST1X_SYNC_MLOCK_OWNER_CHID_V(owner));\n-\t\telse if (HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(owner))\n-\t\t\thost1x_debug_output(o, \"%u: locked by cpu\\n\", i);\n-\t\telse\n-\t\t\thost1x_debug_output(o, \"%u: unlocked\\n\", i);\n-\t}\n-\n-\thost1x_debug_output(o, \"\\n\");\n-}\n+#if HOST1X_HW >= 6\n+#include \"debug_hw_1x06.c\"\n+#else\n+#include \"debug_hw_1x01.c\"\n+#endif\n \n static const struct host1x_debug_ops host1x_debug_ops = {\n \t.show_channel_cdma = host1x_debug_show_channel_cdma,\ndiff --git a/drivers/gpu/host1x/hw/debug_hw_1x01.c b/drivers/gpu/host1x/hw/debug_hw_1x01.c\nnew file mode 100644\nindex 000000000000..8f243903cc7f\n--- /dev/null\n+++ b/drivers/gpu/host1x/hw/debug_hw_1x01.c\n@@ -0,0 +1,154 @@\n+/*\n+ * Copyright (C) 2010 Google, Inc.\n+ * Author: Erik Gilling <konkers@android.com>\n+ *\n+ * Copyright (C) 2011-2013 NVIDIA Corporation\n+ *\n+ * This software is licensed under the terms of the GNU General Public\n+ * License version 2, as published by the Free Software Foundation, and\n+ * may be copied, distributed, and modified under those terms.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ */\n+\n+#include \"../dev.h\"\n+#include \"../debug.h\"\n+#include \"../cdma.h\"\n+#include \"../channel.h\"\n+\n+static void host1x_debug_show_channel_cdma(struct host1x *host,\n+\t\t\t\t\t   struct host1x_channel *ch,\n+\t\t\t\t\t   struct output *o)\n+{\n+\tstruct host1x_cdma *cdma = &ch->cdma;\n+\tu32 dmaput, dmaget, dmactrl;\n+\tu32 cbstat, cbread;\n+\tu32 val, base, baseval;\n+\n+\tdmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);\n+\tdmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);\n+\tdmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);\n+\tcbread = host1x_sync_readl(host, HOST1X_SYNC_CBREAD(ch->id));\n+\tcbstat = host1x_sync_readl(host, HOST1X_SYNC_CBSTAT(ch->id));\n+\n+\thost1x_debug_output(o, \"%u-%s: \", ch->id, dev_name(ch->dev));\n+\n+\tif (HOST1X_CHANNEL_DMACTRL_DMASTOP_V(dmactrl) ||\n+\t    !ch->cdma.push_buffer.mapped) {\n+\t\thost1x_debug_output(o, \"inactive\\n\\n\");\n+\t\treturn;\n+\t}\n+\n+\tif (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) == HOST1X_CLASS_HOST1X &&\n+\t    HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==\n+\t\t\tHOST1X_UCLASS_WAIT_SYNCPT)\n+\t\thost1x_debug_output(o, \"waiting on syncpt %d val %d\\n\",\n+\t\t\t\t    cbread >> 24, cbread & 0xffffff);\n+\telse if (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) ==\n+\t\t\t\tHOST1X_CLASS_HOST1X &&\n+\t\t HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==\n+\t\t\t\tHOST1X_UCLASS_WAIT_SYNCPT_BASE) {\n+\t\tbase = (cbread >> 16) & 0xff;\n+\t\tbaseval =\n+\t\t\thost1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(base));\n+\t\tval = cbread & 0xffff;\n+\t\thost1x_debug_output(o, \"waiting on syncpt %d val %d (base %d = %d; offset = %d)\\n\",\n+\t\t\t\t    cbread >> 24, baseval + val, base,\n+\t\t\t\t    baseval, val);\n+\t} else\n+\t\thost1x_debug_output(o, \"active class %02x, offset %04x, val %08x\\n\",\n+\t\t\t\t    HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat),\n+\t\t\t\t    HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat),\n+\t\t\t\t    cbread);\n+\n+\thost1x_debug_output(o, \"DMAPUT %08x, DMAGET %08x, DMACTL %08x\\n\",\n+\t\t\t    dmaput, dmaget, dmactrl);\n+\thost1x_debug_output(o, \"CBREAD %08x, CBSTAT %08x\\n\", cbread, cbstat);\n+\n+\tshow_channel_gathers(o, cdma);\n+\thost1x_debug_output(o, \"\\n\");\n+}\n+\n+static void host1x_debug_show_channel_fifo(struct host1x *host,\n+\t\t\t\t\t   struct host1x_channel *ch,\n+\t\t\t\t\t   struct output *o)\n+{\n+\tu32 val, rd_ptr, wr_ptr, start, end;\n+\tunsigned int data_count = 0;\n+\n+\thost1x_debug_output(o, \"%u: fifo:\\n\", ch->id);\n+\n+\tval = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT);\n+\thost1x_debug_output(o, \"FIFOSTAT %08x\\n\", val);\n+\tif (HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(val)) {\n+\t\thost1x_debug_output(o, \"[empty]\\n\");\n+\t\treturn;\n+\t}\n+\n+\thost1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);\n+\thost1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |\n+\t\t\t   HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id),\n+\t\t\t   HOST1X_SYNC_CFPEEK_CTRL);\n+\n+\tval = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_PTRS);\n+\trd_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(val);\n+\twr_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(val);\n+\n+\tval = host1x_sync_readl(host, HOST1X_SYNC_CF_SETUP(ch->id));\n+\tstart = HOST1X_SYNC_CF_SETUP_BASE_V(val);\n+\tend = HOST1X_SYNC_CF_SETUP_LIMIT_V(val);\n+\n+\tdo {\n+\t\thost1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);\n+\t\thost1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |\n+\t\t\t\t   HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id) |\n+\t\t\t\t   HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(rd_ptr),\n+\t\t\t\t   HOST1X_SYNC_CFPEEK_CTRL);\n+\t\tval = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ);\n+\n+\t\tif (!data_count) {\n+\t\t\thost1x_debug_output(o, \"%08x:\", val);\n+\t\t\tdata_count = show_channel_command(o, val);\n+\t\t} else {\n+\t\t\thost1x_debug_output(o, \"%08x%s\", val,\n+\t\t\t\t\t    data_count > 0 ? \", \" : \"])\\n\");\n+\t\t\tdata_count--;\n+\t\t}\n+\n+\t\tif (rd_ptr == end)\n+\t\t\trd_ptr = start;\n+\t\telse\n+\t\t\trd_ptr++;\n+\t} while (rd_ptr != wr_ptr);\n+\n+\tif (data_count)\n+\t\thost1x_debug_output(o, \", ...])\\n\");\n+\thost1x_debug_output(o, \"\\n\");\n+\n+\thost1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);\n+}\n+\n+static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)\n+{\n+\tunsigned int i;\n+\n+\thost1x_debug_output(o, \"---- mlocks ----\\n\");\n+\n+\tfor (i = 0; i < host1x_syncpt_nb_mlocks(host); i++) {\n+\t\tu32 owner =\n+\t\t\thost1x_sync_readl(host, HOST1X_SYNC_MLOCK_OWNER(i));\n+\t\tif (HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(owner))\n+\t\t\thost1x_debug_output(o, \"%u: locked by channel %u\\n\",\n+\t\t\t\ti, HOST1X_SYNC_MLOCK_OWNER_CHID_V(owner));\n+\t\telse if (HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(owner))\n+\t\t\thost1x_debug_output(o, \"%u: locked by cpu\\n\", i);\n+\t\telse\n+\t\t\thost1x_debug_output(o, \"%u: unlocked\\n\", i);\n+\t}\n+\n+\thost1x_debug_output(o, \"\\n\");\n+}\ndiff --git a/drivers/gpu/host1x/hw/debug_hw_1x06.c b/drivers/gpu/host1x/hw/debug_hw_1x06.c\nnew file mode 100644\nindex 000000000000..9cdee657fb46\n--- /dev/null\n+++ b/drivers/gpu/host1x/hw/debug_hw_1x06.c\n@@ -0,0 +1,133 @@\n+/*\n+ * Copyright (C) 2010 Google, Inc.\n+ * Author: Erik Gilling <konkers@android.com>\n+ *\n+ * Copyright (C) 2011-2017 NVIDIA Corporation\n+ *\n+ * This software is licensed under the terms of the GNU General Public\n+ * License version 2, as published by the Free Software Foundation, and\n+ * may be copied, distributed, and modified under those terms.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ */\n+\n+#include \"../dev.h\"\n+#include \"../debug.h\"\n+#include \"../cdma.h\"\n+#include \"../channel.h\"\n+\n+static void host1x_debug_show_channel_cdma(struct host1x *host,\n+\t\t\t\t\t   struct host1x_channel *ch,\n+\t\t\t\t\t   struct output *o)\n+{\n+\tstruct host1x_cdma *cdma = &ch->cdma;\n+\tu32 dmaput, dmaget, dmactrl;\n+\tu32 offset, class;\n+\tu32 ch_stat;\n+\n+\tdmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);\n+\tdmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);\n+\tdmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);\n+\toffset = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_OFFSET);\n+\tclass = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_CLASS);\n+\tch_stat = host1x_ch_readl(ch, HOST1X_CHANNEL_CHANNELSTAT);\n+\n+\thost1x_debug_output(o, \"%u-%s: \", ch->id, dev_name(ch->dev));\n+\n+\tif (dmactrl & HOST1X_CHANNEL_DMACTRL_DMASTOP ||\n+\t    !ch->cdma.push_buffer.mapped) {\n+\t\thost1x_debug_output(o, \"inactive\\n\\n\");\n+\t\treturn;\n+\t}\n+\n+\tif (class == HOST1X_CLASS_HOST1X && offset == HOST1X_UCLASS_WAIT_SYNCPT)\n+\t\thost1x_debug_output(o, \"waiting on syncpt\\n\");\n+\telse\n+\t\thost1x_debug_output(o, \"active class %02x, offset %04x\\n\",\n+\t\t\t\t    class, offset);\n+\n+\thost1x_debug_output(o, \"DMAPUT %08x, DMAGET %08x, DMACTL %08x\\n\",\n+\t\t\t    dmaput, dmaget, dmactrl);\n+\thost1x_debug_output(o, \"CHANNELSTAT %02x\\n\", ch_stat);\n+\n+\tshow_channel_gathers(o, cdma);\n+\thost1x_debug_output(o, \"\\n\");\n+}\n+\n+static void host1x_debug_show_channel_fifo(struct host1x *host,\n+\t\t\t\t\t   struct host1x_channel *ch,\n+\t\t\t\t\t   struct output *o)\n+{\n+\tu32 val, rd_ptr, wr_ptr, start, end;\n+\tunsigned int data_count = 0;\n+\n+\thost1x_debug_output(o, \"%u: fifo:\\n\", ch->id);\n+\n+\tval = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_STAT);\n+\thost1x_debug_output(o, \"CMDFIFO_STAT %08x\\n\", val);\n+\tif (val & HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY) {\n+\t\thost1x_debug_output(o, \"[empty]\\n\");\n+\t\treturn;\n+\t}\n+\n+\tval = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_RDATA);\n+\thost1x_debug_output(o, \"CMDFIFO_RDATA %08x\\n\", val);\n+\n+\t/* Peek pointer values are invalid during SLCG, so disable it */\n+\thost1x_hypervisor_writel(host, 0x1, HOST1X_HV_ICG_EN_OVERRIDE);\n+\n+\tval = 0;\n+\tval |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;\n+\tval |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);\n+\thost1x_hypervisor_writel(host, val, HOST1X_HV_CMDFIFO_PEEK_CTRL);\n+\n+\tval = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_PEEK_PTRS);\n+\trd_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(val);\n+\twr_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(val);\n+\n+\tval = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_SETUP(ch->id));\n+\tstart = HOST1X_HV_CMDFIFO_SETUP_BASE_V(val);\n+\tend = HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(val);\n+\n+\tdo {\n+\t\tval = 0;\n+\t\tval |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;\n+\t\tval |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);\n+\t\tval |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(rd_ptr);\n+\t\thost1x_hypervisor_writel(host, val,\n+\t\t\t\t\t HOST1X_HV_CMDFIFO_PEEK_CTRL);\n+\n+\t\tval = host1x_hypervisor_readl(host,\n+\t\t\t\t\t      HOST1X_HV_CMDFIFO_PEEK_READ);\n+\n+\t\tif (!data_count) {\n+\t\t\thost1x_debug_output(o, \"%08x:\", val);\n+\t\t\tdata_count = show_channel_command(o, val);\n+\t\t} else {\n+\t\t\thost1x_debug_output(o, \"%08x%s\", val,\n+\t\t\t\t\t    data_count > 0 ? \", \" : \"])\\n\");\n+\t\t\tdata_count--;\n+\t\t}\n+\n+\t\tif (rd_ptr == end)\n+\t\t\trd_ptr = start;\n+\t\telse\n+\t\t\trd_ptr++;\n+\t} while (rd_ptr != wr_ptr);\n+\n+\tif (data_count)\n+\t\thost1x_debug_output(o, \", ...])\\n\");\n+\thost1x_debug_output(o, \"\\n\");\n+\n+\thost1x_hypervisor_writel(host, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL);\n+\thost1x_hypervisor_writel(host, 0x0, HOST1X_HV_ICG_EN_OVERRIDE);\n+}\n+\n+static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)\n+{\n+\t/* TODO */\n+}\ndiff --git a/drivers/gpu/host1x/hw/host1x01.c b/drivers/gpu/host1x/hw/host1x01.c\nindex 859b73beb4d0..bb124f8b4af8 100644\n--- a/drivers/gpu/host1x/hw/host1x01.c\n+++ b/drivers/gpu/host1x/hw/host1x01.c\n@@ -21,6 +21,8 @@\n #include \"host1x01_hardware.h\"\n \n /* include code */\n+#define HOST1X_HW 1\n+\n #include \"cdma_hw.c\"\n #include \"channel_hw.c\"\n #include \"debug_hw.c\"\ndiff --git a/drivers/gpu/host1x/hw/host1x02.c b/drivers/gpu/host1x/hw/host1x02.c\nindex 928946c2144b..c5f85dbedb98 100644\n--- a/drivers/gpu/host1x/hw/host1x02.c\n+++ b/drivers/gpu/host1x/hw/host1x02.c\n@@ -21,6 +21,8 @@\n #include \"host1x02_hardware.h\"\n \n /* include code */\n+#define HOST1X_HW 2\n+\n #include \"cdma_hw.c\"\n #include \"channel_hw.c\"\n #include \"debug_hw.c\"\ndiff --git a/drivers/gpu/host1x/hw/host1x04.c b/drivers/gpu/host1x/hw/host1x04.c\nindex 8007c70fa9c4..f102a1a7743f 100644\n--- a/drivers/gpu/host1x/hw/host1x04.c\n+++ b/drivers/gpu/host1x/hw/host1x04.c\n@@ -21,6 +21,8 @@\n #include \"host1x04_hardware.h\"\n \n /* include code */\n+#define HOST1X_HW 4\n+\n #include \"cdma_hw.c\"\n #include \"channel_hw.c\"\n #include \"debug_hw.c\"\ndiff --git a/drivers/gpu/host1x/hw/host1x05.c b/drivers/gpu/host1x/hw/host1x05.c\nindex 047097ce3bad..2b1239d6ec67 100644\n--- a/drivers/gpu/host1x/hw/host1x05.c\n+++ b/drivers/gpu/host1x/hw/host1x05.c\n@@ -21,6 +21,8 @@\n #include \"host1x05_hardware.h\"\n \n /* include code */\n+#define HOST1X_HW 5\n+\n #include \"cdma_hw.c\"\n #include \"channel_hw.c\"\n #include \"debug_hw.c\"\ndiff --git a/drivers/gpu/host1x/hw/host1x06.c b/drivers/gpu/host1x/hw/host1x06.c\nnew file mode 100644\nindex 000000000000..a66230827c59\n--- /dev/null\n+++ b/drivers/gpu/host1x/hw/host1x06.c\n@@ -0,0 +1,44 @@\n+/*\n+ * Host1x init for Tegra186 SoCs\n+ *\n+ * Copyright (c) 2017 NVIDIA Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+/* include hw specification */\n+#include \"host1x06.h\"\n+#include \"host1x06_hardware.h\"\n+\n+/* include code */\n+#define HOST1X_HW 6\n+\n+#include \"cdma_hw.c\"\n+#include \"channel_hw.c\"\n+#include \"debug_hw.c\"\n+#include \"intr_hw.c\"\n+#include \"syncpt_hw.c\"\n+\n+#include \"../dev.h\"\n+\n+int host1x06_init(struct host1x *host)\n+{\n+\thost->channel_op = &host1x_channel_ops;\n+\thost->cdma_op = &host1x_cdma_ops;\n+\thost->cdma_pb_op = &host1x_pushbuffer_ops;\n+\thost->syncpt_op = &host1x_syncpt_ops;\n+\thost->intr_op = &host1x_intr_ops;\n+\thost->debug_op = &host1x_debug_ops;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/gpu/host1x/hw/host1x06.h b/drivers/gpu/host1x/hw/host1x06.h\nnew file mode 100644\nindex 000000000000..d9abe1489241\n--- /dev/null\n+++ b/drivers/gpu/host1x/hw/host1x06.h\n@@ -0,0 +1,26 @@\n+/*\n+ * Host1x init for Tegra186 SoCs\n+ *\n+ * Copyright (c) 2017 NVIDIA Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef HOST1X_HOST1X06_H\n+#define HOST1X_HOST1X06_H\n+\n+struct host1x;\n+\n+int host1x06_init(struct host1x *host);\n+\n+#endif\ndiff --git a/drivers/gpu/host1x/hw/host1x06_hardware.h b/drivers/gpu/host1x/hw/host1x06_hardware.h\nnew file mode 100644\nindex 000000000000..3039c92ea605\n--- /dev/null\n+++ b/drivers/gpu/host1x/hw/host1x06_hardware.h\n@@ -0,0 +1,142 @@\n+/*\n+ * Tegra host1x Register Offsets for Tegra186\n+ *\n+ * Copyright (c) 2017 NVIDIA Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef __HOST1X_HOST1X06_HARDWARE_H\n+#define __HOST1X_HOST1X06_HARDWARE_H\n+\n+#include <linux/types.h>\n+#include <linux/bitops.h>\n+\n+#include \"hw_host1x06_uclass.h\"\n+#include \"hw_host1x06_vm.h\"\n+#include \"hw_host1x06_hypervisor.h\"\n+\n+static inline u32 host1x_class_host_wait_syncpt(\n+\tunsigned indx, unsigned threshold)\n+{\n+\treturn host1x_uclass_wait_syncpt_indx_f(indx)\n+\t\t| host1x_uclass_wait_syncpt_thresh_f(threshold);\n+}\n+\n+static inline u32 host1x_class_host_load_syncpt_base(\n+\tunsigned indx, unsigned threshold)\n+{\n+\treturn host1x_uclass_load_syncpt_base_base_indx_f(indx)\n+\t\t| host1x_uclass_load_syncpt_base_value_f(threshold);\n+}\n+\n+static inline u32 host1x_class_host_wait_syncpt_base(\n+\tunsigned indx, unsigned base_indx, unsigned offset)\n+{\n+\treturn host1x_uclass_wait_syncpt_base_indx_f(indx)\n+\t\t| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)\n+\t\t| host1x_uclass_wait_syncpt_base_offset_f(offset);\n+}\n+\n+static inline u32 host1x_class_host_incr_syncpt_base(\n+\tunsigned base_indx, unsigned offset)\n+{\n+\treturn host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)\n+\t\t| host1x_uclass_incr_syncpt_base_offset_f(offset);\n+}\n+\n+static inline u32 host1x_class_host_incr_syncpt(\n+\tunsigned cond, unsigned indx)\n+{\n+\treturn host1x_uclass_incr_syncpt_cond_f(cond)\n+\t\t| host1x_uclass_incr_syncpt_indx_f(indx);\n+}\n+\n+static inline u32 host1x_class_host_indoff_reg_write(\n+\tunsigned mod_id, unsigned offset, bool auto_inc)\n+{\n+\tu32 v = host1x_uclass_indoff_indbe_f(0xf)\n+\t\t| host1x_uclass_indoff_indmodid_f(mod_id)\n+\t\t| host1x_uclass_indoff_indroffset_f(offset);\n+\tif (auto_inc)\n+\t\tv |= host1x_uclass_indoff_autoinc_f(1);\n+\treturn v;\n+}\n+\n+static inline u32 host1x_class_host_indoff_reg_read(\n+\tunsigned mod_id, unsigned offset, bool auto_inc)\n+{\n+\tu32 v = host1x_uclass_indoff_indmodid_f(mod_id)\n+\t\t| host1x_uclass_indoff_indroffset_f(offset)\n+\t\t| host1x_uclass_indoff_rwn_read_v();\n+\tif (auto_inc)\n+\t\tv |= host1x_uclass_indoff_autoinc_f(1);\n+\treturn v;\n+}\n+\n+/* cdma opcodes */\n+static inline u32 host1x_opcode_setclass(\n+\tunsigned class_id, unsigned offset, unsigned mask)\n+{\n+\treturn (0 << 28) | (offset << 16) | (class_id << 6) | mask;\n+}\n+\n+static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)\n+{\n+\treturn (1 << 28) | (offset << 16) | count;\n+}\n+\n+static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)\n+{\n+\treturn (2 << 28) | (offset << 16) | count;\n+}\n+\n+static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)\n+{\n+\treturn (3 << 28) | (offset << 16) | mask;\n+}\n+\n+static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)\n+{\n+\treturn (4 << 28) | (offset << 16) | value;\n+}\n+\n+static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)\n+{\n+\treturn host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),\n+\t\thost1x_class_host_incr_syncpt(cond, indx));\n+}\n+\n+static inline u32 host1x_opcode_restart(unsigned address)\n+{\n+\treturn (5 << 28) | (address >> 4);\n+}\n+\n+static inline u32 host1x_opcode_gather(unsigned count)\n+{\n+\treturn (6 << 28) | count;\n+}\n+\n+static inline u32 host1x_opcode_gather_nonincr(unsigned offset,\tunsigned count)\n+{\n+\treturn (6 << 28) | (offset << 16) | BIT(15) | count;\n+}\n+\n+static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)\n+{\n+\treturn (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;\n+}\n+\n+#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)\n+\n+#endif\ndiff --git a/drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h b/drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h\nnew file mode 100644\nindex 000000000000..c05dab8a178b\n--- /dev/null\n+++ b/drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h\n@@ -0,0 +1,32 @@\n+/*\n+ * Copyright (c) 2017 NVIDIA Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ *\n+ */\n+\n+#define HOST1X_HV_SYNCPT_PROT_EN\t\t\t0x1ac4\n+#define HOST1X_HV_SYNCPT_PROT_EN_CH_EN\t\t\tBIT(1)\n+#define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x)\t\t(0x2020 + (x * 4))\n+#define HOST1X_HV_CMDFIFO_PEEK_CTRL\t\t\t0x233c\n+#define HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(x)\t\t(x)\n+#define HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(x)\t\t((x) << 16)\n+#define HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE\t\tBIT(31)\n+#define HOST1X_HV_CMDFIFO_PEEK_READ\t\t\t0x2340\n+#define HOST1X_HV_CMDFIFO_PEEK_PTRS\t\t\t0x2344\n+#define HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(x)\t\t(((x) >> 16) & 0xfff)\n+#define HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(x)\t\t((x) & 0xfff)\n+#define HOST1X_HV_CMDFIFO_SETUP(x)\t\t\t(0x2588 + (x * 4))\n+#define HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(x)\t\t(((x) >> 16) & 0xfff)\n+#define HOST1X_HV_CMDFIFO_SETUP_BASE_V(x)\t\t((x) & 0xfff)\n+#define HOST1X_HV_ICG_EN_OVERRIDE\t\t\t0x2aa8\ndiff --git a/drivers/gpu/host1x/hw/hw_host1x06_uclass.h b/drivers/gpu/host1x/hw/hw_host1x06_uclass.h\nnew file mode 100644\nindex 000000000000..4457486c72b0\n--- /dev/null\n+++ b/drivers/gpu/host1x/hw/hw_host1x06_uclass.h\n@@ -0,0 +1,181 @@\n+/*\n+ * Copyright (c) 2017 NVIDIA Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ *\n+ */\n+\n+ /*\n+  * Function naming determines intended use:\n+  *\n+  *     <x>_r(void) : Returns the offset for register <x>.\n+  *\n+  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.\n+  *\n+  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.\n+  *\n+  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted\n+  *         and masked to place it at field <y> of register <x>.  This value\n+  *         can be |'d with others to produce a full register value for\n+  *         register <x>.\n+  *\n+  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This\n+  *         value can be ~'d and then &'d to clear the value of field <y> for\n+  *         register <x>.\n+  *\n+  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted\n+  *         to place it at field <y> of register <x>.  This value can be |'d\n+  *         with others to produce a full register value for <x>.\n+  *\n+  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register\n+  *         <x> value 'r' after being shifted to place its LSB at bit 0.\n+  *         This value is suitable for direct comparison with other unshifted\n+  *         values appropriate for use in field <y> of register <x>.\n+  *\n+  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for\n+  *         field <y> of register <x>.  This value is suitable for direct\n+  *         comparison with unshifted values appropriate for use in field <y>\n+  *         of register <x>.\n+  */\n+\n+#ifndef HOST1X_HW_HOST1X06_UCLASS_H\n+#define HOST1X_HW_HOST1X06_UCLASS_H\n+\n+static inline u32 host1x_uclass_incr_syncpt_r(void)\n+{\n+\treturn 0x0;\n+}\n+#define HOST1X_UCLASS_INCR_SYNCPT \\\n+\thost1x_uclass_incr_syncpt_r()\n+static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)\n+{\n+\treturn (v & 0xff) << 8;\n+}\n+#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \\\n+\thost1x_uclass_incr_syncpt_cond_f(v)\n+static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)\n+{\n+\treturn (v & 0xff) << 0;\n+}\n+#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \\\n+\thost1x_uclass_incr_syncpt_indx_f(v)\n+static inline u32 host1x_uclass_wait_syncpt_r(void)\n+{\n+\treturn 0x8;\n+}\n+#define HOST1X_UCLASS_WAIT_SYNCPT \\\n+\thost1x_uclass_wait_syncpt_r()\n+static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)\n+{\n+\treturn (v & 0xff) << 24;\n+}\n+#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \\\n+\thost1x_uclass_wait_syncpt_indx_f(v)\n+static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)\n+{\n+\treturn (v & 0xffffff) << 0;\n+}\n+#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \\\n+\thost1x_uclass_wait_syncpt_thresh_f(v)\n+static inline u32 host1x_uclass_wait_syncpt_base_r(void)\n+{\n+\treturn 0x9;\n+}\n+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \\\n+\thost1x_uclass_wait_syncpt_base_r()\n+static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)\n+{\n+\treturn (v & 0xff) << 24;\n+}\n+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \\\n+\thost1x_uclass_wait_syncpt_base_indx_f(v)\n+static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)\n+{\n+\treturn (v & 0xff) << 16;\n+}\n+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \\\n+\thost1x_uclass_wait_syncpt_base_base_indx_f(v)\n+static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)\n+{\n+\treturn (v & 0xffff) << 0;\n+}\n+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \\\n+\thost1x_uclass_wait_syncpt_base_offset_f(v)\n+static inline u32 host1x_uclass_load_syncpt_base_r(void)\n+{\n+\treturn 0xb;\n+}\n+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \\\n+\thost1x_uclass_load_syncpt_base_r()\n+static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)\n+{\n+\treturn (v & 0xff) << 24;\n+}\n+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \\\n+\thost1x_uclass_load_syncpt_base_base_indx_f(v)\n+static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)\n+{\n+\treturn (v & 0xffffff) << 0;\n+}\n+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \\\n+\thost1x_uclass_load_syncpt_base_value_f(v)\n+static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)\n+{\n+\treturn (v & 0xff) << 24;\n+}\n+#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \\\n+\thost1x_uclass_incr_syncpt_base_base_indx_f(v)\n+static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)\n+{\n+\treturn (v & 0xffffff) << 0;\n+}\n+#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \\\n+\thost1x_uclass_incr_syncpt_base_offset_f(v)\n+static inline u32 host1x_uclass_indoff_r(void)\n+{\n+\treturn 0x2d;\n+}\n+#define HOST1X_UCLASS_INDOFF \\\n+\thost1x_uclass_indoff_r()\n+static inline u32 host1x_uclass_indoff_indbe_f(u32 v)\n+{\n+\treturn (v & 0xf) << 28;\n+}\n+#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \\\n+\thost1x_uclass_indoff_indbe_f(v)\n+static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)\n+{\n+\treturn (v & 0x1) << 27;\n+}\n+#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \\\n+\thost1x_uclass_indoff_autoinc_f(v)\n+static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)\n+{\n+\treturn (v & 0xff) << 18;\n+}\n+#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \\\n+\thost1x_uclass_indoff_indmodid_f(v)\n+static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)\n+{\n+\treturn (v & 0xffff) << 2;\n+}\n+#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \\\n+\thost1x_uclass_indoff_indroffset_f(v)\n+static inline u32 host1x_uclass_indoff_rwn_read_v(void)\n+{\n+\treturn 1;\n+}\n+#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \\\n+\thost1x_uclass_indoff_indroffset_f(v)\n+\n+#endif\ndiff --git a/drivers/gpu/host1x/hw/hw_host1x06_vm.h b/drivers/gpu/host1x/hw/hw_host1x06_vm.h\nnew file mode 100644\nindex 000000000000..e54b33902332\n--- /dev/null\n+++ b/drivers/gpu/host1x/hw/hw_host1x06_vm.h\n@@ -0,0 +1,47 @@\n+/*\n+ * Copyright (c) 2017 NVIDIA Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ *\n+ */\n+\n+#define HOST1X_CHANNEL_DMASTART\t\t\t\t0x0000\n+#define HOST1X_CHANNEL_DMASTART_HI\t\t\t0x0004\n+#define HOST1X_CHANNEL_DMAPUT\t\t\t\t0x0008\n+#define HOST1X_CHANNEL_DMAPUT_HI\t\t\t0x000c\n+#define HOST1X_CHANNEL_DMAGET\t\t\t\t0x0010\n+#define HOST1X_CHANNEL_DMAGET_HI\t\t\t0x0014\n+#define HOST1X_CHANNEL_DMAEND\t\t\t\t0x0018\n+#define HOST1X_CHANNEL_DMAEND_HI\t\t\t0x001c\n+#define HOST1X_CHANNEL_DMACTRL\t\t\t\t0x0020\n+#define HOST1X_CHANNEL_DMACTRL_DMASTOP\t\t\tBIT(0)\n+#define HOST1X_CHANNEL_DMACTRL_DMAGETRST\t\tBIT(1)\n+#define HOST1X_CHANNEL_DMACTRL_DMAINITGET\t\tBIT(2)\n+#define HOST1X_CHANNEL_CMDFIFO_STAT\t\t\t0x0024\n+#define HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY\t\tBIT(13)\n+#define HOST1X_CHANNEL_CMDFIFO_RDATA\t\t\t0x0028\n+#define HOST1X_CHANNEL_CMDP_OFFSET\t\t\t0x0030\n+#define HOST1X_CHANNEL_CMDP_CLASS\t\t\t0x0034\n+#define HOST1X_CHANNEL_CHANNELSTAT\t\t\t0x0038\n+#define HOST1X_CHANNEL_CMDPROC_STOP\t\t\t0x0048\n+#define HOST1X_CHANNEL_TEARDOWN\t\t\t\t0x004c\n+\n+#define HOST1X_SYNC_SYNCPT_CPU_INCR(x)\t\t\t(0x6400 + 4*(x))\n+#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(x)\t(0x6464 + 4*(x))\n+#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(x)\t(0x652c + 4*(x))\n+#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(x)\t(0x6590 + 4*(x))\n+#define HOST1X_SYNC_SYNCPT_BASE(x)\t\t\t(0x8000 + 4*(x))\n+#define HOST1X_SYNC_SYNCPT(x)\t\t\t\t(0x8080 + 4*(x))\n+#define HOST1X_SYNC_SYNCPT_INT_THRESH(x)\t\t(0x8a00 + 4*(x))\n+#define HOST1X_SYNC_SYNCPT_CH_APP(x)\t\t\t(0x9384 + 4*(x))\n+#define HOST1X_SYNC_SYNCPT_CH_APP_CH(v)\t\t\t(((v) & 0x3f) << 8)\ndiff --git a/drivers/gpu/host1x/hw/intr_hw.c b/drivers/gpu/host1x/hw/intr_hw.c\nindex 37ebb51703fa..329239237090 100644\n--- a/drivers/gpu/host1x/hw/intr_hw.c\n+++ b/drivers/gpu/host1x/hw/intr_hw.c\n@@ -72,6 +72,23 @@ static void _host1x_intr_disable_all_syncpt_intrs(struct host1x *host)\n \t}\n }\n \n+static void intr_hw_init(struct host1x *host, u32 cpm)\n+{\n+#if HOST1X_HW < 6\n+\t/* disable the ip_busy_timeout. this prevents write drops */\n+\thost1x_sync_writel(host, 0, HOST1X_SYNC_IP_BUSY_TIMEOUT);\n+\n+\t/*\n+\t * increase the auto-ack timout to the maximum value. 2d will hang\n+\t * otherwise on Tegra2.\n+\t */\n+\thost1x_sync_writel(host, 0xff, HOST1X_SYNC_CTXSW_TIMEOUT_CFG);\n+\n+\t/* update host clocks per usec */\n+\thost1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK);\n+#endif\n+}\n+\n static int\n _host1x_intr_init_host_sync(struct host1x *host, u32 cpm,\n \t\t\t    void (*syncpt_thresh_work)(struct work_struct *))\n@@ -92,17 +109,7 @@ _host1x_intr_init_host_sync(struct host1x *host, u32 cpm,\n \t\treturn err;\n \t}\n \n-\t/* disable the ip_busy_timeout. this prevents write drops */\n-\thost1x_sync_writel(host, 0, HOST1X_SYNC_IP_BUSY_TIMEOUT);\n-\n-\t/*\n-\t * increase the auto-ack timout to the maximum value. 2d will hang\n-\t * otherwise on Tegra2.\n-\t */\n-\thost1x_sync_writel(host, 0xff, HOST1X_SYNC_CTXSW_TIMEOUT_CFG);\n-\n-\t/* update host clocks per usec */\n-\thost1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK);\n+\tintr_hw_init(host, cpm);\n \n \treturn 0;\n }\n",
    "prefixes": [
        "v2",
        "5/6"
    ]
}