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GET /api/patches/809986/?format=api
{ "id": 809986, "url": "http://patchwork.ozlabs.org/api/patches/809986/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20170905081029.19769-4-mperttunen@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170905081029.19769-4-mperttunen@nvidia.com>", "list_archive_url": null, "date": "2017-09-05T08:10:26", "name": "[v2,3/6] gpu: host1x: Improve debug disassembly formatting", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "51943eeebd9381b1d661221dba04e457e4f862c1", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20170905081029.19769-4-mperttunen@nvidia.com/mbox/", "series": [ { "id": 1506, "url": "http://patchwork.ozlabs.org/api/series/1506/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=1506", "date": "2017-09-05T08:10:29", "name": "Miscellaneous improvements to Host1x and TegraDRM", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/1506/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809986/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809986/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tsecure) header.d=kapsi.fi header.i=@kapsi.fi header.b=\"mpg9xwGO\";\n\tdkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmfZz0Q2Mz9s0g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 5 Sep 2017 18:12:27 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751507AbdIEIMZ (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 5 Sep 2017 04:12:25 -0400", "from mail.kapsi.fi ([91.232.154.25]:33553 \"EHLO mail.kapsi.fi\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751317AbdIEIKl (ORCPT <rfc822;linux-tegra@vger.kernel.org>);\n\tTue, 5 Sep 2017 04:10:41 -0400", "from dsl-hkibng41-567306-181.dhcp.inet.fi ([86.115.6.181]\n\thelo=localhost.localdomain) by mail.kapsi.fi with esmtpsa\n\t(TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2)\n\t(envelope-from <mperttunen@nvidia.com>)\n\tid 1dp8wN-0001nH-IL; Tue, 05 Sep 2017 11:10:35 +0300" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kapsi.fi;\n\ts=20161220; \n\th=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From;\n\tbh=C3cM25rveq+kQfzLSVOs33fiV0dBhjRE5scbxAtnGSg=; \n\tb=mpg9xwGOWhUMwiH0XBZVheRrYxRvQ3X+yihHDNQkKUbge9En4Pvm5HEMY00TGw0KF+CXWFGx4c9lHxyCt4HDFU18YTRv8Iiqj/CKPTztYIEvByPmqNeX8DlsB8gi2MlQgVIM/VOn7G/D/KtCmmSHpgKgLeB0bCmkmozop+JCAeb/9G1l1WFemfqPzvNUAt475UeCMKqhd8Tz4R7358rcegpaym07CI3Eg4agRgtRAoBi+5XEDuBYHJRQAxvKMHm4hx4GGlcHqVCGiAJHR8UL/fmyDTOytM28Gvb0pzcx4kqknIxsQHPRS7kStit3ZqCgnO8XZVO5zLbFcpxNpU/xHg==;", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "To": "thierry.reding@gmail.com, jonathanh@nvidia.com", "Cc": "digetx@gmail.com, dri-devel@lists.freedesktop.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tMikko Perttunen <mperttunen@nvidia.com>", "Subject": "[PATCH v2 3/6] gpu: host1x: Improve debug disassembly formatting", "Date": "Tue, 5 Sep 2017 11:10:26 +0300", "Message-Id": "<20170905081029.19769-4-mperttunen@nvidia.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170905081029.19769-1-mperttunen@nvidia.com>", "References": "<20170905081029.19769-1-mperttunen@nvidia.com>", "X-SA-Exim-Connect-IP": "86.115.6.181", "X-SA-Exim-Mail-From": "mperttunen@nvidia.com", "X-SA-Exim-Scanned": "No (on mail.kapsi.fi); SAEximRunCond expanded to false", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "The host1x driver prints out \"disassembly\" dumps of the command FIFO\nand gather contents on submission timeouts. However, the output has\nbeen quite difficult to read with unnecessary newlines and occasional\nmissing parentheses.\n\nFix these problems by using pr_cont to remove unnecessary newlines\nand by fixing other small issues.\n\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\nReviewed-by: Dmitry Osipenko <digetx@gmail.com>\nTested-by: Dmitry Osipenko <digetx@gmail.com>\n---\nThis uses pr_cont, which there are currently talks of being replaced\nwith something better. I kept using it here for now until there is\nsome conclusion of what's the best way to replace it.\n\n drivers/gpu/host1x/debug.c | 14 ++++++++++-\n drivers/gpu/host1x/debug.h | 14 ++++++++---\n drivers/gpu/host1x/hw/debug_hw.c | 46 ++++++++++++++++++++++-------------\n drivers/gpu/host1x/hw/debug_hw_1x01.c | 8 +++---\n drivers/gpu/host1x/hw/debug_hw_1x06.c | 9 ++++---\n 5 files changed, 61 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/gpu/host1x/debug.c b/drivers/gpu/host1x/debug.c\nindex 2aae0e63214c..dc77ec452ffc 100644\n--- a/drivers/gpu/host1x/debug.c\n+++ b/drivers/gpu/host1x/debug.c\n@@ -40,7 +40,19 @@ void host1x_debug_output(struct output *o, const char *fmt, ...)\n \tlen = vsnprintf(o->buf, sizeof(o->buf), fmt, args);\n \tva_end(args);\n \n-\to->fn(o->ctx, o->buf, len);\n+\to->fn(o->ctx, o->buf, len, false);\n+}\n+\n+void host1x_debug_cont(struct output *o, const char *fmt, ...)\n+{\n+\tva_list args;\n+\tint len;\n+\n+\tva_start(args, fmt);\n+\tlen = vsnprintf(o->buf, sizeof(o->buf), fmt, args);\n+\tva_end(args);\n+\n+\to->fn(o->ctx, o->buf, len, true);\n }\n \n static int show_channel(struct host1x_channel *ch, void *data, bool show_fifo)\ndiff --git a/drivers/gpu/host1x/debug.h b/drivers/gpu/host1x/debug.h\nindex 4595b2e0799f..990cce47e737 100644\n--- a/drivers/gpu/host1x/debug.h\n+++ b/drivers/gpu/host1x/debug.h\n@@ -24,22 +24,28 @@\n struct host1x;\n \n struct output {\n-\tvoid (*fn)(void *ctx, const char *str, size_t len);\n+\tvoid (*fn)(void *ctx, const char *str, size_t len, bool cont);\n \tvoid *ctx;\n \tchar buf[256];\n };\n \n-static inline void write_to_seqfile(void *ctx, const char *str, size_t len)\n+static inline void write_to_seqfile(void *ctx, const char *str, size_t len,\n+\t\t\t\t bool cont)\n {\n \tseq_write((struct seq_file *)ctx, str, len);\n }\n \n-static inline void write_to_printk(void *ctx, const char *str, size_t len)\n+static inline void write_to_printk(void *ctx, const char *str, size_t len,\n+\t\t\t\t bool cont)\n {\n-\tpr_info(\"%s\", str);\n+\tif (cont)\n+\t\tpr_cont(\"%s\", str);\n+\telse\n+\t\tpr_info(\"%s\", str);\n }\n \n void __printf(2, 3) host1x_debug_output(struct output *o, const char *fmt, ...);\n+void __printf(2, 3) host1x_debug_cont(struct output *o, const char *fmt, ...);\n \n extern unsigned int host1x_debug_trace_cmdbuf;\n \ndiff --git a/drivers/gpu/host1x/hw/debug_hw.c b/drivers/gpu/host1x/hw/debug_hw.c\nindex 770d92e62d69..1e67667e308c 100644\n--- a/drivers/gpu/host1x/hw/debug_hw.c\n+++ b/drivers/gpu/host1x/hw/debug_hw.c\n@@ -40,48 +40,59 @@ enum {\n \n static unsigned int show_channel_command(struct output *o, u32 val)\n {\n-\tunsigned int mask, subop;\n+\tunsigned int mask, subop, num;\n \n \tswitch (val >> 28) {\n \tcase HOST1X_OPCODE_SETCLASS:\n \t\tmask = val & 0x3f;\n \t\tif (mask) {\n-\t\t\thost1x_debug_output(o, \"SETCL(class=%03x, offset=%03x, mask=%02x, [\",\n+\t\t\thost1x_debug_cont(o, \"SETCL(class=%03x, offset=%03x, mask=%02x, [\",\n \t\t\t\t\t val >> 6 & 0x3ff,\n \t\t\t\t\t val >> 16 & 0xfff, mask);\n \t\t\treturn hweight8(mask);\n \t\t}\n \n-\t\thost1x_debug_output(o, \"SETCL(class=%03x)\\n\", val >> 6 & 0x3ff);\n+\t\thost1x_debug_cont(o, \"SETCL(class=%03x)\\n\", val >> 6 & 0x3ff);\n \t\treturn 0;\n \n \tcase HOST1X_OPCODE_INCR:\n-\t\thost1x_debug_output(o, \"INCR(offset=%03x, [\",\n+\t\tnum = val & 0xffff;\n+\t\thost1x_debug_cont(o, \"INCR(offset=%03x, [\",\n \t\t\t\t val >> 16 & 0xfff);\n-\t\treturn val & 0xffff;\n+\t\tif (!num)\n+\t\t\thost1x_debug_cont(o, \"])\\n\");\n+\n+\t\treturn num;\n \n \tcase HOST1X_OPCODE_NONINCR:\n-\t\thost1x_debug_output(o, \"NONINCR(offset=%03x, [\",\n+\t\tnum = val & 0xffff;\n+\t\thost1x_debug_cont(o, \"NONINCR(offset=%03x, [\",\n \t\t\t\t val >> 16 & 0xfff);\n-\t\treturn val & 0xffff;\n+\t\tif (!num)\n+\t\t\thost1x_debug_cont(o, \"])\\n\");\n+\n+\t\treturn num;\n \n \tcase HOST1X_OPCODE_MASK:\n \t\tmask = val & 0xffff;\n-\t\thost1x_debug_output(o, \"MASK(offset=%03x, mask=%03x, [\",\n+\t\thost1x_debug_cont(o, \"MASK(offset=%03x, mask=%03x, [\",\n \t\t\t\t val >> 16 & 0xfff, mask);\n+\t\tif (!mask)\n+\t\t\thost1x_debug_cont(o, \"])\\n\");\n+\n \t\treturn hweight16(mask);\n \n \tcase HOST1X_OPCODE_IMM:\n-\t\thost1x_debug_output(o, \"IMM(offset=%03x, data=%03x)\\n\",\n+\t\thost1x_debug_cont(o, \"IMM(offset=%03x, data=%03x)\\n\",\n \t\t\t\t val >> 16 & 0xfff, val & 0xffff);\n \t\treturn 0;\n \n \tcase HOST1X_OPCODE_RESTART:\n-\t\thost1x_debug_output(o, \"RESTART(offset=%08x)\\n\", val << 4);\n+\t\thost1x_debug_cont(o, \"RESTART(offset=%08x)\\n\", val << 4);\n \t\treturn 0;\n \n \tcase HOST1X_OPCODE_GATHER:\n-\t\thost1x_debug_output(o, \"GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[\",\n+\t\thost1x_debug_cont(o, \"GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[\",\n \t\t\t\t val >> 16 & 0xfff, val >> 15 & 0x1,\n \t\t\t\t val >> 14 & 0x1, val & 0x3fff);\n \t\treturn 1;\n@@ -89,16 +100,17 @@ static unsigned int show_channel_command(struct output *o, u32 val)\n \tcase HOST1X_OPCODE_EXTEND:\n \t\tsubop = val >> 24 & 0xf;\n \t\tif (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)\n-\t\t\thost1x_debug_output(o, \"ACQUIRE_MLOCK(index=%d)\\n\",\n+\t\t\thost1x_debug_cont(o, \"ACQUIRE_MLOCK(index=%d)\\n\",\n \t\t\t\t\t val & 0xff);\n \t\telse if (subop == HOST1X_OPCODE_EXTEND_RELEASE_MLOCK)\n-\t\t\thost1x_debug_output(o, \"RELEASE_MLOCK(index=%d)\\n\",\n+\t\t\thost1x_debug_cont(o, \"RELEASE_MLOCK(index=%d)\\n\",\n \t\t\t\t\t val & 0xff);\n \t\telse\n-\t\t\thost1x_debug_output(o, \"EXTEND_UNKNOWN(%08x)\\n\", val);\n+\t\t\thost1x_debug_cont(o, \"EXTEND_UNKNOWN(%08x)\\n\", val);\n \t\treturn 0;\n \n \tdefault:\n+\t\thost1x_debug_cont(o, \"UNKNOWN\\n\");\n \t\treturn 0;\n \t}\n }\n@@ -126,11 +138,11 @@ static void show_gather(struct output *o, phys_addr_t phys_addr,\n \t\tu32 val = *(map_addr + offset / 4 + i);\n \n \t\tif (!data_count) {\n-\t\t\thost1x_debug_output(o, \"%08x: %08x:\", addr, val);\n+\t\t\thost1x_debug_output(o, \"%08x: %08x: \", addr, val);\n \t\t\tdata_count = show_channel_command(o, val);\n \t\t} else {\n-\t\t\thost1x_debug_output(o, \"%08x%s\", val,\n-\t\t\t\t\t data_count > 0 ? \", \" : \"])\\n\");\n+\t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n+\t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\n \t\t\tdata_count--;\n \t\t}\n \t}\ndiff --git a/drivers/gpu/host1x/hw/debug_hw_1x01.c b/drivers/gpu/host1x/hw/debug_hw_1x01.c\nindex 8f243903cc7f..09e1aa7bb5dd 100644\n--- a/drivers/gpu/host1x/hw/debug_hw_1x01.c\n+++ b/drivers/gpu/host1x/hw/debug_hw_1x01.c\n@@ -111,11 +111,11 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n \t\tval = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ);\n \n \t\tif (!data_count) {\n-\t\t\thost1x_debug_output(o, \"%08x:\", val);\n+\t\t\thost1x_debug_output(o, \"%08x: \", val);\n \t\t\tdata_count = show_channel_command(o, val);\n \t\t} else {\n-\t\t\thost1x_debug_output(o, \"%08x%s\", val,\n-\t\t\t\t\t data_count > 0 ? \", \" : \"])\\n\");\n+\t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n+\t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\n \t\t\tdata_count--;\n \t\t}\n \n@@ -126,7 +126,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n \t} while (rd_ptr != wr_ptr);\n \n \tif (data_count)\n-\t\thost1x_debug_output(o, \", ...])\\n\");\n+\t\thost1x_debug_cont(o, \", ...])\\n\");\n \thost1x_debug_output(o, \"\\n\");\n \n \thost1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);\ndiff --git a/drivers/gpu/host1x/hw/debug_hw_1x06.c b/drivers/gpu/host1x/hw/debug_hw_1x06.c\nindex 9cdee657fb46..bd89da5dc64c 100644\n--- a/drivers/gpu/host1x/hw/debug_hw_1x06.c\n+++ b/drivers/gpu/host1x/hw/debug_hw_1x06.c\n@@ -105,11 +105,12 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n \t\t\t\t\t HOST1X_HV_CMDFIFO_PEEK_READ);\n \n \t\tif (!data_count) {\n-\t\t\thost1x_debug_output(o, \"%08x:\", val);\n+\t\t\thost1x_debug_output(o, \"%03x 0x%08x: \",\n+\t\t\t\t\t rd_ptr - start, val);\n \t\t\tdata_count = show_channel_command(o, val);\n \t\t} else {\n-\t\t\thost1x_debug_output(o, \"%08x%s\", val,\n-\t\t\t\t\t data_count > 0 ? \", \" : \"])\\n\");\n+\t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n+\t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\n \t\t\tdata_count--;\n \t\t}\n \n@@ -120,7 +121,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n \t} while (rd_ptr != wr_ptr);\n \n \tif (data_count)\n-\t\thost1x_debug_output(o, \", ...])\\n\");\n+\t\thost1x_debug_cont(o, \", ...])\\n\");\n \thost1x_debug_output(o, \"\\n\");\n \n \thost1x_hypervisor_writel(host, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL);\n", "prefixes": [ "v2", "3/6" ] }