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GET /api/patches/809661/?format=api
{ "id": 809661, "url": "http://patchwork.ozlabs.org/api/patches/809661/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-29-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504527967-29248-29-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-04T12:25:59", "name": "[PULL,28/36] boards.h: Define new flag ignore_memory_transaction_failures", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "153f7030b5dadd74001caba3291b0c1ad26ef03f", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-29-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 1366, "url": "http://patchwork.ozlabs.org/api/series/1366/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366", "date": "2017-09-04T12:25:36", "name": "[PULL,01/36] target/arm: Use MMUAccessType enum rather than int", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1366/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809661/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809661/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8qp1mzBz9sNr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 4 Sep 2017 22:51:49 +1000 (AEST)", "from localhost ([::1]:59664 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1doqqw-0007WK-KV\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:51:46 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52854)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSf-0005DW-Ta\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:51 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSR-0004wM-UB\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:41 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37132)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1doqSR-0004v8-Mk\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:27 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSQ-0005bM-GQ\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:26 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 4 Sep 2017 13:25:59 +0100", "Message-Id": "<1504527967-29248-29-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "References": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PULL 28/36] boards.h: Define new flag\n\tignore_memory_transaction_failures", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Define a new MachineClass field ignore_memory_transaction_failures.\nIf this is flag is true then the CPU will ignore memory transaction\nfailures which should cause the CPU to take an exception due to an\naccess to an unassigned physical address; the transaction will\ninstead return zero (for a read) or be ignored (for a write). This\nshould be set only by legacy board models which rely on the old\nRAZ/WI behaviour for handling devices that QEMU does not yet model.\nNew board models should instead use \"unimplemented-device\" for all\nmemory ranges where the guest will attempt to probe for a device that\nQEMU doesn't implement and a stub device is required.\n\nWe need this for ARM boards, where we're about to implement support for\ngenerating external aborts on memory transaction failures. Too many\nof our legacy board models rely on the RAZ/WI behaviour and we\nwould break currently working guests when their \"probe for device\"\ncode provoked an external abort rather than a RAZ.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n include/hw/boards.h | 11 +++++++++++\n include/qom/cpu.h | 7 ++++++-\n qom/cpu.c | 7 +++++++\n 3 files changed, 24 insertions(+), 1 deletion(-)", "diff": "diff --git a/include/hw/boards.h b/include/hw/boards.h\nindex 3363dd1..7f044d1 100644\n--- a/include/hw/boards.h\n+++ b/include/hw/boards.h\n@@ -131,6 +131,16 @@ typedef struct {\n * size than the target architecture's minimum. (Attempting to create\n * such a CPU will fail.) Note that changing this is a migration\n * compatibility break for the machine.\n+ * @ignore_memory_transaction_failures:\n+ * If this is flag is true then the CPU will ignore memory transaction\n+ * failures which should cause the CPU to take an exception due to an\n+ * access to an unassigned physical address; the transaction will instead\n+ * return zero (for a read) or be ignored (for a write). This should be\n+ * set only by legacy board models which rely on the old RAZ/WI behaviour\n+ * for handling devices that QEMU does not yet model. New board models\n+ * should instead use \"unimplemented-device\" for all memory ranges where\n+ * the guest will attempt to probe for a device that QEMU doesn't\n+ * implement and a stub device is required.\n */\n struct MachineClass {\n /*< private >*/\n@@ -171,6 +181,7 @@ struct MachineClass {\n bool rom_file_has_mr;\n int minimum_page_bits;\n bool has_hotpluggable_cpus;\n+ bool ignore_memory_transaction_failures;\n int numa_mem_align_shift;\n void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes,\n int nb_nodes, ram_addr_t size);\ndiff --git a/include/qom/cpu.h b/include/qom/cpu.h\nindex 08bd868..995a7be 100644\n--- a/include/qom/cpu.h\n+++ b/include/qom/cpu.h\n@@ -312,6 +312,9 @@ struct qemu_work_item;\n * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes\n * to @trace_dstate).\n * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).\n+ * @ignore_memory_transaction_failures: Cached copy of the MachineState\n+ * flag of the same name: allows the board to suppress calling of the\n+ * CPU do_transaction_failed hook function.\n *\n * State of one CPU core or thread.\n */\n@@ -398,6 +401,8 @@ struct CPUState {\n */\n bool throttle_thread_scheduled;\n \n+ bool ignore_memory_transaction_failures;\n+\n /* Note that this is accessed at the start of every TB via a negative\n offset from AREG0. Leave this field at the end so as to make the\n (absolute value) offset as small as possible. This reduces code\n@@ -864,7 +869,7 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,\n {\n CPUClass *cc = CPU_GET_CLASS(cpu);\n \n- if (cc->do_transaction_failed) {\n+ if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) {\n cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,\n mmu_idx, attrs, response, retaddr);\n }\ndiff --git a/qom/cpu.c b/qom/cpu.c\nindex deb8880..33f865c 100644\n--- a/qom/cpu.c\n+++ b/qom/cpu.c\n@@ -29,6 +29,7 @@\n #include \"exec/cpu-common.h\"\n #include \"qemu/error-report.h\"\n #include \"sysemu/sysemu.h\"\n+#include \"hw/boards.h\"\n #include \"hw/qdev-properties.h\"\n #include \"trace-root.h\"\n \n@@ -363,6 +364,12 @@ static void cpu_common_parse_features(const char *typename, char *features,\n static void cpu_common_realizefn(DeviceState *dev, Error **errp)\n {\n CPUState *cpu = CPU(dev);\n+ Object *machine = qdev_get_machine();\n+ ObjectClass *oc = object_get_class(machine);\n+ MachineClass *mc = MACHINE_CLASS(oc);\n+\n+ cpu->ignore_memory_transaction_failures =\n+ mc->ignore_memory_transaction_failures;\n \n if (dev->hotplugged) {\n cpu_synchronize_post_init(cpu);\n", "prefixes": [ "PULL", "28/36" ] }