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GET /api/patches/809649/?format=api
{ "id": 809649, "url": "http://patchwork.ozlabs.org/api/patches/809649/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-24-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504527967-29248-24-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-04T12:25:54", "name": "[PULL,23/36] watchdog: wdt_aspeed: Add support for the reset width register", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "731342151a3593a9184a0b9d6cc837199c03ca73", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-24-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 1366, "url": "http://patchwork.ozlabs.org/api/series/1366/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366", "date": "2017-09-04T12:25:36", "name": "[PULL,01/36] target/arm: Use MMUAccessType enum rather than int", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1366/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809649/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809649/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8hS66h1z9t2Z\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 4 Sep 2017 22:45:28 +1000 (AEST)", "from localhost ([::1]:59631 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1doqko-0002KO-SB\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:45:26 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52755)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSb-00058m-4g\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:48 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSL-0004sQ-Hu\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:37 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37128)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1doqSL-0004ru-7c\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:21 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSK-0005ZA-88\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:20 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 4 Sep 2017 13:25:54 +0100", "Message-Id": "<1504527967-29248-24-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "References": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PULL 23/36] watchdog: wdt_aspeed: Add support for the\n\treset width register", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Andrew Jeffery <andrew@aj.id.au>\n\nThe reset width register controls how the pulse on the SoC's WDTRST{1,2}\npins behaves. A pulse is emitted if the external reset bit is set in\nWDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns\nto configure push-pull/open-drain and active-high/active-low\nbehaviours and thus needs some special handling in the write path.\n\nAs some of the capabilities depend on the SoC version a silicon-rev\nproperty is introduced, which is used to guard version-specific\nbehaviour.\n\nSigned-off-by: Andrew Jeffery <andrew@aj.id.au>\nReviewed-by: Cédric Le Goater <clg@kaod.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n include/hw/watchdog/wdt_aspeed.h | 2 +\n hw/watchdog/wdt_aspeed.c | 93 +++++++++++++++++++++++++++++++++++-----\n 2 files changed, 84 insertions(+), 11 deletions(-)", "diff": "diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h\nindex 080c223..7de3e5c 100644\n--- a/include/hw/watchdog/wdt_aspeed.h\n+++ b/include/hw/watchdog/wdt_aspeed.h\n@@ -27,6 +27,8 @@ typedef struct AspeedWDTState {\n uint32_t regs[ASPEED_WDT_REGS_MAX];\n \n uint32_t pclk_freq;\n+ uint32_t silicon_rev;\n+ uint32_t ext_pulse_width_mask;\n } AspeedWDTState;\n \n #endif /* ASPEED_WDT_H */\ndiff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c\nindex 8bbe579..22bce36 100644\n--- a/hw/watchdog/wdt_aspeed.c\n+++ b/hw/watchdog/wdt_aspeed.c\n@@ -8,16 +8,19 @@\n */\n \n #include \"qemu/osdep.h\"\n+\n+#include \"qapi/error.h\"\n #include \"qemu/log.h\"\n+#include \"qemu/timer.h\"\n #include \"sysemu/watchdog.h\"\n+#include \"hw/misc/aspeed_scu.h\"\n #include \"hw/sysbus.h\"\n-#include \"qemu/timer.h\"\n #include \"hw/watchdog/wdt_aspeed.h\"\n \n-#define WDT_STATUS (0x00 / 4)\n-#define WDT_RELOAD_VALUE (0x04 / 4)\n-#define WDT_RESTART (0x08 / 4)\n-#define WDT_CTRL (0x0C / 4)\n+#define WDT_STATUS (0x00 / 4)\n+#define WDT_RELOAD_VALUE (0x04 / 4)\n+#define WDT_RESTART (0x08 / 4)\n+#define WDT_CTRL (0x0C / 4)\n #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)\n #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)\n #define WDT_CTRL_1MHZ_CLK BIT(4)\n@@ -25,18 +28,41 @@\n #define WDT_CTRL_WDT_INTR BIT(2)\n #define WDT_CTRL_RESET_SYSTEM BIT(1)\n #define WDT_CTRL_ENABLE BIT(0)\n+#define WDT_RESET_WIDTH (0x18 / 4)\n+#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)\n+#define WDT_POLARITY_MASK (0xFF << 24)\n+#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)\n+#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)\n+#define WDT_RESET_WIDTH_PUSH_PULL BIT(30)\n+#define WDT_DRIVE_TYPE_MASK (0xFF << 24)\n+#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)\n+#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)\n \n-#define WDT_TIMEOUT_STATUS (0x10 / 4)\n-#define WDT_TIMEOUT_CLEAR (0x14 / 4)\n-#define WDT_RESET_WDITH (0x18 / 4)\n+#define WDT_TIMEOUT_STATUS (0x10 / 4)\n+#define WDT_TIMEOUT_CLEAR (0x14 / 4)\n \n-#define WDT_RESTART_MAGIC 0x4755\n+#define WDT_RESTART_MAGIC 0x4755\n \n static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)\n {\n return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;\n }\n \n+static bool is_ast2500(const AspeedWDTState *s)\n+{\n+ switch (s->silicon_rev) {\n+ case AST2500_A0_SILICON_REV:\n+ case AST2500_A1_SILICON_REV:\n+ return true;\n+ case AST2400_A0_SILICON_REV:\n+ case AST2400_A1_SILICON_REV:\n+ default:\n+ break;\n+ }\n+\n+ return false;\n+}\n+\n static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)\n {\n AspeedWDTState *s = ASPEED_WDT(opaque);\n@@ -55,9 +81,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)\n return 0;\n case WDT_CTRL:\n return s->regs[WDT_CTRL];\n+ case WDT_RESET_WIDTH:\n+ return s->regs[WDT_RESET_WIDTH];\n case WDT_TIMEOUT_STATUS:\n case WDT_TIMEOUT_CLEAR:\n- case WDT_RESET_WDITH:\n qemu_log_mask(LOG_UNIMP,\n \"%s: uninmplemented read at offset 0x%\" HWADDR_PRIx \"\\n\",\n __func__, offset);\n@@ -119,9 +146,27 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,\n timer_del(s->timer);\n }\n break;\n+ case WDT_RESET_WIDTH:\n+ {\n+ uint32_t property = data & WDT_POLARITY_MASK;\n+\n+ if (property && is_ast2500(s)) {\n+ if (property == WDT_ACTIVE_HIGH_MAGIC) {\n+ s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH;\n+ } else if (property == WDT_ACTIVE_LOW_MAGIC) {\n+ s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH;\n+ } else if (property == WDT_PUSH_PULL_MAGIC) {\n+ s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL;\n+ } else if (property == WDT_OPEN_DRAIN_MAGIC) {\n+ s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL;\n+ }\n+ }\n+ s->regs[WDT_RESET_WIDTH] &= ~s->ext_pulse_width_mask;\n+ s->regs[WDT_RESET_WIDTH] |= data & s->ext_pulse_width_mask;\n+ break;\n+ }\n case WDT_TIMEOUT_STATUS:\n case WDT_TIMEOUT_CLEAR:\n- case WDT_RESET_WDITH:\n qemu_log_mask(LOG_UNIMP,\n \"%s: uninmplemented write at offset 0x%\" HWADDR_PRIx \"\\n\",\n __func__, offset);\n@@ -167,6 +212,7 @@ static void aspeed_wdt_reset(DeviceState *dev)\n s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;\n s->regs[WDT_RESTART] = 0;\n s->regs[WDT_CTRL] = 0;\n+ s->regs[WDT_RESET_WIDTH] = 0xFF;\n \n timer_del(s->timer);\n }\n@@ -187,6 +233,25 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)\n SysBusDevice *sbd = SYS_BUS_DEVICE(dev);\n AspeedWDTState *s = ASPEED_WDT(dev);\n \n+ if (!is_supported_silicon_rev(s->silicon_rev)) {\n+ error_setg(errp, \"Unknown silicon revision: 0x%\" PRIx32,\n+ s->silicon_rev);\n+ return;\n+ }\n+\n+ switch (s->silicon_rev) {\n+ case AST2400_A0_SILICON_REV:\n+ case AST2400_A1_SILICON_REV:\n+ s->ext_pulse_width_mask = 0xff;\n+ break;\n+ case AST2500_A0_SILICON_REV:\n+ case AST2500_A1_SILICON_REV:\n+ s->ext_pulse_width_mask = 0xfffff;\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);\n \n /* FIXME: This setting should be derived from the SCU hw strapping\n@@ -199,6 +264,11 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)\n sysbus_init_mmio(sbd, &s->iomem);\n }\n \n+static Property aspeed_wdt_properties[] = {\n+ DEFINE_PROP_UINT32(\"silicon-rev\", AspeedWDTState, silicon_rev, 0),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n static void aspeed_wdt_class_init(ObjectClass *klass, void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(klass);\n@@ -207,6 +277,7 @@ static void aspeed_wdt_class_init(ObjectClass *klass, void *data)\n dc->reset = aspeed_wdt_reset;\n set_bit(DEVICE_CATEGORY_MISC, dc->categories);\n dc->vmsd = &vmstate_aspeed_wdt;\n+ dc->props = aspeed_wdt_properties;\n }\n \n static const TypeInfo aspeed_wdt_info = {\n", "prefixes": [ "PULL", "23/36" ] }