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GET /api/patches/809642/?format=api
{ "id": 809642, "url": "http://patchwork.ozlabs.org/api/patches/809642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-11-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504527967-29248-11-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-04T12:25:41", "name": "[PULL,10/36] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d95f1596978651bd4adbb9d93a397281121a6fe9", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-11-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 1366, "url": "http://patchwork.ozlabs.org/api/series/1366/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366", "date": "2017-09-04T12:25:36", "name": "[PULL,01/36] target/arm: Use MMUAccessType enum rather than int", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1366/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809642/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809642/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8YP1h4dz9t2R\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 4 Sep 2017 22:39:21 +1000 (AEST)", "from localhost ([::1]:59605 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1doqet-0005wp-9D\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:39:19 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52354)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSG-0004sW-Kt\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:29 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqS6-0004gD-8K\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:16 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37110)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1doqS5-0004ej-W5\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:06 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqS5-0005TQ-18\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:05 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 4 Sep 2017 13:25:41 +0100", "Message-Id": "<1504527967-29248-11-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "References": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PULL 10/36] target/arm: Don't use\n\tcpsr_write/cpsr_read to transfer M profile XPSR", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "For M profile the XPSR is a similar but not identical format to the\nA profile CPSR/SPSR. (For instance the Thumb bit is in a different\nplace.) For guest accesses we make the M profile code go through\nxpsr_read() and xpsr_write() which handle the different layout.\nHowever for migration we use cpsr_read() and cpsr_write() to\nmarshal state into and out of the migration data stream. This\nis pretty confusing and works more by luck than anything else.\nMake M profile migration use xpsr_read() and xpsr_write() instead.\n\nThe most complicated part of this is handling the possibility\nthat the migration source is an older QEMU which hands us a\nCPSR format value; helpfully we can always tell the two apart.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-id: 1501692241-23310-11-git-send-email-peter.maydell@linaro.org\n---\n target/arm/machine.c | 49 ++++++++++++++++++++++++++++++++++---------------\n 1 file changed, 34 insertions(+), 15 deletions(-)", "diff": "diff --git a/target/arm/machine.c b/target/arm/machine.c\nindex 2fb4b762..3193b00 100644\n--- a/target/arm/machine.c\n+++ b/target/arm/machine.c\n@@ -217,21 +217,37 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size,\n uint32_t val = qemu_get_be32(f);\n \n if (arm_feature(env, ARM_FEATURE_M)) {\n- /* If the I or F bits are set then this is a migration from\n- * an old QEMU which still stored the M profile FAULTMASK\n- * and PRIMASK in env->daif. Set v7m.faultmask and v7m.primask\n- * accordingly, and then clear the bits so they don't confuse\n- * cpsr_write(). For a new QEMU, the bits here will always be\n- * clear, and the data is transferred using the\n- * vmstate_m_faultmask_primask subsection.\n- */\n- if (val & CPSR_F) {\n- env->v7m.faultmask = 1;\n- }\n- if (val & CPSR_I) {\n- env->v7m.primask = 1;\n+ if (val & XPSR_EXCP) {\n+ /* This is a CPSR format value from an older QEMU. (We can tell\n+ * because values transferred in XPSR format always have zero\n+ * for the EXCP field, and CPSR format will always have bit 4\n+ * set in CPSR_M.) Rearrange it into XPSR format. The significant\n+ * differences are that the T bit is not in the same place, the\n+ * primask/faultmask info may be in the CPSR I and F bits, and\n+ * we do not want the mode bits.\n+ */\n+ uint32_t newval = val;\n+\n+ newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE);\n+ if (val & CPSR_T) {\n+ newval |= XPSR_T;\n+ }\n+ /* If the I or F bits are set then this is a migration from\n+ * an old QEMU which still stored the M profile FAULTMASK\n+ * and PRIMASK in env->daif. For a new QEMU, the data is\n+ * transferred using the vmstate_m_faultmask_primask subsection.\n+ */\n+ if (val & CPSR_F) {\n+ env->v7m.faultmask = 1;\n+ }\n+ if (val & CPSR_I) {\n+ env->v7m.primask = 1;\n+ }\n+ val = newval;\n }\n- val &= ~(CPSR_F | CPSR_I);\n+ /* Ignore the low bits, they are handled by vmstate_m. */\n+ xpsr_write(env, val, ~XPSR_EXCP);\n+ return 0;\n }\n \n env->aarch64 = ((val & PSTATE_nRW) == 0);\n@@ -252,7 +268,10 @@ static int put_cpsr(QEMUFile *f, void *opaque, size_t size,\n CPUARMState *env = &cpu->env;\n uint32_t val;\n \n- if (is_a64(env)) {\n+ if (arm_feature(env, ARM_FEATURE_M)) {\n+ /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */\n+ val = xpsr_read(env) & ~XPSR_EXCP;\n+ } else if (is_a64(env)) {\n val = pstate_read(env);\n } else {\n val = cpsr_read(env);\n", "prefixes": [ "PULL", "10/36" ] }