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GET /api/patches/809636/?format=api
{ "id": 809636, "url": "http://patchwork.ozlabs.org/api/patches/809636/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-10-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504527967-29248-10-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-04T12:25:40", "name": "[PULL,09/36] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4e313fda92433c2088368b17cabe5366c0f41183", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-10-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 1366, "url": "http://patchwork.ozlabs.org/api/series/1366/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366", "date": "2017-09-04T12:25:36", "name": "[PULL,01/36] target/arm: Use MMUAccessType enum rather than int", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1366/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809636/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809636/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8Qb6f2cz9t2c\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 4 Sep 2017 22:33:27 +1000 (AEST)", "from localhost ([::1]:59564 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1doqZC-0001V1-0Q\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:33:26 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52329)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSE-0004rN-WD\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:29 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqS5-0004eV-5b\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:14 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37108)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1doqS4-0004cC-RX\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:05 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqS3-0005Sl-Ru\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:03 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 4 Sep 2017 13:25:40 +0100", "Message-Id": "<1504527967-29248-10-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "References": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PULL 09/36] target/arm: Don't store M profile PRIMASK\n\tand FAULTMASK in daif", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "We currently store the M profile CPU register state PRIMASK and\nFAULTMASK in the daif field of the CPU state in its I and F\nbits. This is a legacy from the original implementation, which\ntried to share the cpu_exec_interrupt code between A profile\nand M profile. We've since separated out the two cases because\nthey are significantly different, so now there is no common\ncode between M and A profile which looks at env->daif: all the\nuses are either in A-only or M-only code paths. Sharing the state\nfields now is just confusing, and will make things awkward\nwhen we implement v8M, where the PRIMASK and FAULTMASK\nregisters are banked between security states.\n\nSwitch M profile over to using v7m.faultmask and v7m.primask\nfields for these registers.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-id: 1501692241-23310-10-git-send-email-peter.maydell@linaro.org\n---\n target/arm/cpu.h | 4 +++-\n hw/intc/armv7m_nvic.c | 4 ++--\n target/arm/cpu.c | 5 -----\n target/arm/helper.c | 18 +++++-------------\n target/arm/machine.c | 33 +++++++++++++++++++++++++++++++++\n 5 files changed, 43 insertions(+), 21 deletions(-)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 0b9f937..8ef552a 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -418,6 +418,8 @@ typedef struct CPUARMState {\n uint32_t bfar; /* BusFault Address */\n unsigned mpu_ctrl; /* MPU_CTRL */\n int exception;\n+ uint32_t primask;\n+ uint32_t faultmask;\n } v7m;\n \n /* Information associated with an exception about to be taken:\n@@ -2178,7 +2180,7 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)\n * we're in a HardFault or NMI handler.\n */\n if ((env->v7m.exception > 0 && env->v7m.exception <= 3)\n- || env->daif & PSTATE_F) {\n+ || env->v7m.faultmask) {\n return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri);\n }\n \ndiff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 2e8166a..343bc16 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -167,9 +167,9 @@ static inline int nvic_exec_prio(NVICState *s)\n CPUARMState *env = &s->cpu->env;\n int running;\n \n- if (env->daif & PSTATE_F) { /* FAULTMASK */\n+ if (env->v7m.faultmask) {\n running = -1;\n- } else if (env->daif & PSTATE_I) { /* PRIMASK */\n+ } else if (env->v7m.primask) {\n running = 0;\n } else if (env->v7m.basepri > 0) {\n running = env->v7m.basepri & nvic_gprio_mask(s);\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 05c038b..b241a63 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -185,11 +185,6 @@ static void arm_cpu_reset(CPUState *s)\n uint32_t initial_pc; /* Loaded from 0x4 */\n uint8_t *rom;\n \n- /* For M profile we store FAULTMASK and PRIMASK in the\n- * PSTATE F and I bits; these are both clear at reset.\n- */\n- env->daif &= ~(PSTATE_I | PSTATE_F);\n-\n /* The reset value of this bit is IMPDEF, but ARM recommends\n * that it resets to 1, so QEMU always does that rather than making\n * it dependent on CPU model.\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 439ad86..9410856 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6167,7 +6167,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n \n if (env->v7m.exception != ARMV7M_EXCP_NMI) {\n /* Auto-clear FAULTMASK on return from other than NMI */\n- env->daif &= ~PSTATE_F;\n+ env->v7m.faultmask = 0;\n }\n \n switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) {\n@@ -8713,12 +8713,12 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)\n return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ?\n env->regs[13] : env->v7m.other_sp;\n case 16: /* PRIMASK */\n- return (env->daif & PSTATE_I) != 0;\n+ return env->v7m.primask;\n case 17: /* BASEPRI */\n case 18: /* BASEPRI_MAX */\n return env->v7m.basepri;\n case 19: /* FAULTMASK */\n- return (env->daif & PSTATE_F) != 0;\n+ return env->v7m.faultmask;\n default:\n qemu_log_mask(LOG_GUEST_ERROR, \"Attempt to read unknown special\"\n \" register %d\\n\", reg);\n@@ -8773,11 +8773,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)\n }\n break;\n case 16: /* PRIMASK */\n- if (val & 1) {\n- env->daif |= PSTATE_I;\n- } else {\n- env->daif &= ~PSTATE_I;\n- }\n+ env->v7m.primask = val & 1;\n break;\n case 17: /* BASEPRI */\n env->v7m.basepri = val & 0xff;\n@@ -8788,11 +8784,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)\n env->v7m.basepri = val;\n break;\n case 19: /* FAULTMASK */\n- if (val & 1) {\n- env->daif |= PSTATE_F;\n- } else {\n- env->daif &= ~PSTATE_F;\n- }\n+ env->v7m.faultmask = val & 1;\n break;\n case 20: /* CONTROL */\n /* Writing to the SPSEL bit only has an effect if we are in\ndiff --git a/target/arm/machine.c b/target/arm/machine.c\nindex 1f66da4..2fb4b762 100644\n--- a/target/arm/machine.c\n+++ b/target/arm/machine.c\n@@ -97,6 +97,17 @@ static bool m_needed(void *opaque)\n return arm_feature(env, ARM_FEATURE_M);\n }\n \n+static const VMStateDescription vmstate_m_faultmask_primask = {\n+ .name = \"cpu/m/faultmask-primask\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_UINT32(env.v7m.faultmask, ARMCPU),\n+ VMSTATE_UINT32(env.v7m.primask, ARMCPU),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n static const VMStateDescription vmstate_m = {\n .name = \"cpu/m\",\n .version_id = 4,\n@@ -115,6 +126,10 @@ static const VMStateDescription vmstate_m = {\n VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU),\n VMSTATE_INT32(env.v7m.exception, ARMCPU),\n VMSTATE_END_OF_LIST()\n+ },\n+ .subsections = (const VMStateDescription*[]) {\n+ &vmstate_m_faultmask_primask,\n+ NULL\n }\n };\n \n@@ -201,6 +216,24 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size,\n CPUARMState *env = &cpu->env;\n uint32_t val = qemu_get_be32(f);\n \n+ if (arm_feature(env, ARM_FEATURE_M)) {\n+ /* If the I or F bits are set then this is a migration from\n+ * an old QEMU which still stored the M profile FAULTMASK\n+ * and PRIMASK in env->daif. Set v7m.faultmask and v7m.primask\n+ * accordingly, and then clear the bits so they don't confuse\n+ * cpsr_write(). For a new QEMU, the bits here will always be\n+ * clear, and the data is transferred using the\n+ * vmstate_m_faultmask_primask subsection.\n+ */\n+ if (val & CPSR_F) {\n+ env->v7m.faultmask = 1;\n+ }\n+ if (val & CPSR_I) {\n+ env->v7m.primask = 1;\n+ }\n+ val &= ~(CPSR_F | CPSR_I);\n+ }\n+\n env->aarch64 = ((val & PSTATE_nRW) == 0);\n \n if (is_a64(env)) {\n", "prefixes": [ "PULL", "09/36" ] }