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GET /api/patches/809628/?format=api
{ "id": 809628, "url": "http://patchwork.ozlabs.org/api/patches/809628/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-4-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504527967-29248-4-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-04T12:25:34", "name": "[PULL,03/36] target/arm: Consolidate PMSA handling in get_phys_addr()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "36272f0c77b13f74935bf9cc827189b9a507ec1c", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-4-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 1366, "url": "http://patchwork.ozlabs.org/api/series/1366/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366", "date": "2017-09-04T12:25:36", "name": "[PULL,01/36] target/arm: Use MMUAccessType enum rather than int", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1366/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809628/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809628/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8Lt6Pz4z9t2S\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 4 Sep 2017 22:30:13 +1000 (AEST)", "from localhost ([::1]:59542 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1doqW2-0007Id-Sv\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:30:10 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52196)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqS9-0004o7-H9\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:21 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqS2-0004bM-Mg\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:09 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37106)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1doqS2-0004Yp-Bf\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:02 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqRv-0005QN-5d\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:25:55 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 4 Sep 2017 13:25:34 +0100", "Message-Id": "<1504527967-29248-4-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "References": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PULL 03/36] target/arm: Consolidate PMSA handling in\n\tget_phys_addr()", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Currently get_phys_addr() has PMSAv7 handling before the\n\"is translation disabled?\" check, and then PMSAv5 after it.\nTidy this up by making the PMSAv5 code handle the \"MPU disabled\"\ncase itself, so that we have all the PMSA code in one place.\nThis will make adding the PMSAv8 code slightly cleaner, and\nalso means that pre-v7 PMSA cores benefit from the MPU lookup\nlogging that the PMSAv7 codepath had.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-id: 1501692241-23310-4-git-send-email-peter.maydell@linaro.org\n---\n target/arm/helper.c | 38 ++++++++++++++++++++++----------------\n 1 file changed, 22 insertions(+), 16 deletions(-)", "diff": "diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 8e148be..8190682 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -8418,6 +8418,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,\n uint32_t base;\n bool is_user = regime_is_user(env, mmu_idx);\n \n+ if (regime_translation_disabled(env, mmu_idx)) {\n+ /* MPU disabled. */\n+ *phys_ptr = address;\n+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n+ return false;\n+ }\n+\n *phys_ptr = address;\n for (n = 7; n >= 0; n--) {\n base = env->cp15.c6_region[n];\n@@ -8567,16 +8574,20 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,\n }\n }\n \n- /* pmsav7 has special handling for when MPU is disabled so call it before\n- * the common MMU/MPU disabled check below.\n- */\n- if (arm_feature(env, ARM_FEATURE_PMSA) &&\n- arm_feature(env, ARM_FEATURE_V7)) {\n+ if (arm_feature(env, ARM_FEATURE_PMSA)) {\n bool ret;\n *page_size = TARGET_PAGE_SIZE;\n- ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,\n- phys_ptr, prot, fsr);\n- qemu_log_mask(CPU_LOG_MMU, \"PMSAv7 MPU lookup for %s at 0x%08\" PRIx32\n+\n+ if (arm_feature(env, ARM_FEATURE_V7)) {\n+ /* PMSAv7 */\n+ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,\n+ phys_ptr, prot, fsr);\n+ } else {\n+ /* Pre-v7 MPU */\n+ ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,\n+ phys_ptr, prot, fsr);\n+ }\n+ qemu_log_mask(CPU_LOG_MMU, \"PMSA MPU lookup for %s at 0x%08\" PRIx32\n \" mmu_idx %u -> %s (prot %c%c%c)\\n\",\n access_type == MMU_DATA_LOAD ? \"reading\" :\n (access_type == MMU_DATA_STORE ? \"writing\" : \"execute\"),\n@@ -8589,21 +8600,16 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,\n return ret;\n }\n \n+ /* Definitely a real MMU, not an MPU */\n+\n if (regime_translation_disabled(env, mmu_idx)) {\n- /* MMU/MPU disabled. */\n+ /* MMU disabled. */\n *phys_ptr = address;\n *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n *page_size = TARGET_PAGE_SIZE;\n return 0;\n }\n \n- if (arm_feature(env, ARM_FEATURE_PMSA)) {\n- /* Pre-v7 MPU */\n- *page_size = TARGET_PAGE_SIZE;\n- return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,\n- phys_ptr, prot, fsr);\n- }\n-\n if (regime_using_lpae_format(env, mmu_idx)) {\n return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,\n attrs, prot, page_size, fsr, fi);\n", "prefixes": [ "PULL", "03/36" ] }