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GET /api/patches/809627/?format=api
{ "id": 809627, "url": "http://patchwork.ozlabs.org/api/patches/809627/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-5-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504527967-29248-5-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-04T12:25:35", "name": "[PULL,04/36] target/arm: Tighten up Thumb decode where new v8M insns will be", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9eccec6cd1900f6d8bb6b6490aaa78d9a66f71d8", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-5-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 1366, "url": "http://patchwork.ozlabs.org/api/series/1366/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366", "date": "2017-09-04T12:25:36", "name": "[PULL,01/36] target/arm: Use MMUAccessType enum rather than int", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1366/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809627/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809627/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8LD5qp3z9t2S\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 4 Sep 2017 22:29:40 +1000 (AEST)", "from localhost ([::1]:59540 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1doqVW-0006tV-OJ\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:29:38 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52159)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqS7-0004mx-Mw\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:19 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqS2-0004ad-3B\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:07 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37104)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1doqS1-0004RY-PM\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:01 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqRx-0005Qd-4H\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:25:57 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 4 Sep 2017 13:25:35 +0100", "Message-Id": "<1504527967-29248-5-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "References": "<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PULL 04/36] target/arm: Tighten up Thumb decode where\n\tnew v8M insns will be", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Tighten up the T32 decoder in the places where new v8M instructions\nwill be:\n * TT/TTT/TTA/TTAT are in what was nominally LDREX/STREX r15, ...\n which is UNPREDICTABLE:\n make the UNPREDICTABLE behaviour be to UNDEF\n * BXNS/BLXNS are distinguished from BX/BLX via the low 3 bits,\n which in previous architectural versions are SBZ:\n enforce the SBZ via UNDEF rather than ignoring it, and move\n the \"ARCH(5)\" UNDEF case up so we don't leak a TCG temporary\n * SG is in the encoding which would be LDRD/STRD with rn = r15;\n this is UNPREDICTABLE and we currently UNDEF:\n move this check further up the code so that we don't leak\n TCG temporaries in the UNDEF case and have a better place\n to put the SG decode.\n\nThis means that if a v8M binary is accidentally run on v7M\nor if a test case hits something that we haven't implemented\nyet the behaviour will be obvious (UNDEF) rather than obscure\n(plough on treating it as a different instruction).\n\nIn the process, add some comments about the instruction patterns\nat these points in the decode. Our Thumb and ARM decoders are\nvery difficult to understand currently, but gradually adding\ncomments like this should help to clarify what exactly has\nbeen decoded when.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-id: 1501692241-23310-5-git-send-email-peter.maydell@linaro.org\n---\n target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++---------\n 1 file changed, 39 insertions(+), 9 deletions(-)", "diff": "diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex d1a5f56..3c14cb0 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -9735,10 +9735,23 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw\n abort();\n case 4:\n if (insn & (1 << 22)) {\n- /* Other load/store, table branch. */\n+ /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx\n+ * - load/store doubleword, load/store exclusive, ldacq/strel,\n+ * table branch.\n+ */\n if (insn & 0x01200000) {\n- /* Load/store doubleword. */\n+ /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx\n+ * - load/store dual (post-indexed)\n+ * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx\n+ * - load/store dual (literal and immediate)\n+ * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx\n+ * - load/store dual (pre-indexed)\n+ */\n if (rn == 15) {\n+ if (insn & (1 << 21)) {\n+ /* UNPREDICTABLE */\n+ goto illegal_op;\n+ }\n addr = tcg_temp_new_i32();\n tcg_gen_movi_i32(addr, s->pc & ~3);\n } else {\n@@ -9772,15 +9785,18 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw\n }\n if (insn & (1 << 21)) {\n /* Base writeback. */\n- if (rn == 15)\n- goto illegal_op;\n tcg_gen_addi_i32(addr, addr, offset - 4);\n store_reg(s, rn, addr);\n } else {\n tcg_temp_free_i32(addr);\n }\n } else if ((insn & (1 << 23)) == 0) {\n- /* Load/store exclusive word. */\n+ /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx\n+ * - load/store exclusive word\n+ */\n+ if (rs == 15) {\n+ goto illegal_op;\n+ }\n addr = tcg_temp_local_new_i32();\n load_reg_var(s, addr, rn);\n tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);\n@@ -11137,7 +11153,9 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)\n break;\n }\n if (insn & (1 << 10)) {\n- /* data processing extended or blx */\n+ /* 0b0100_01xx_xxxx_xxxx\n+ * - data processing extended, branch and exchange\n+ */\n rd = (insn & 7) | ((insn >> 4) & 8);\n rm = (insn >> 3) & 0xf;\n op = (insn >> 8) & 3;\n@@ -11160,10 +11178,21 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)\n tmp = load_reg(s, rm);\n store_reg(s, rd, tmp);\n break;\n- case 3:/* branch [and link] exchange thumb register */\n- tmp = load_reg(s, rm);\n- if (insn & (1 << 7)) {\n+ case 3:\n+ {\n+ /* 0b0100_0111_xxxx_xxxx\n+ * - branch [and link] exchange thumb register\n+ */\n+ bool link = insn & (1 << 7);\n+\n+ if (insn & 7) {\n+ goto undef;\n+ }\n+ if (link) {\n ARCH(5);\n+ }\n+ tmp = load_reg(s, rm);\n+ if (link) {\n val = (uint32_t)s->pc | 1;\n tmp2 = tcg_temp_new_i32();\n tcg_gen_movi_i32(tmp2, val);\n@@ -11175,6 +11204,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)\n }\n break;\n }\n+ }\n break;\n }\n \n", "prefixes": [ "PULL", "04/36" ] }