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{ "id": 809608, "url": "http://patchwork.ozlabs.org/api/patches/809608/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/87lgluittz.fsf@linaro.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<87lgluittz.fsf@linaro.org>", "list_archive_url": null, "date": "2017-09-04T11:31:04", "name": "[2/9] Make more use of int_mode_for_size", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fb69bf5508faad479c22c8e41c8550b320fbb6a7", "submitter": { "id": 5450, "url": "http://patchwork.ozlabs.org/api/people/5450/?format=api", "name": "Richard Sandiford", "email": "richard.sandiford@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/87lgluittz.fsf@linaro.org/mbox/", "series": [ { "id": 1357, "url": "http://patchwork.ozlabs.org/api/series/1357/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=1357", "date": "2017-09-04T11:24:26", "name": "Make more use of opt_mode", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1357/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809608/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809608/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461404-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461404-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"xNU+JpwS\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm73C6047z9s8J\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 4 Sep 2017 21:31:34 +1000 (AEST)", "(qmail 87198 invoked by alias); 4 Sep 2017 11:31:18 -0000", "(qmail 87122 invoked by uid 89); 4 Sep 2017 11:31:17 -0000", "from mail-wm0-f45.google.com (HELO mail-wm0-f45.google.com)\n\t(74.125.82.45) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tMon, 04 Sep 2017 11:31:10 +0000", "by mail-wm0-f45.google.com with SMTP id u26so1663732wma.0 for\n\t<gcc-patches@gcc.gnu.org>; Mon, 04 Sep 2017 04:31:09 -0700 (PDT)", "from localhost (94.197.120.41.threembb.co.uk. [94.197.120.41]) by\n\tsmtp.gmail.com with ESMTPSA id\n\tm128sm286215wmd.23.2017.09.04.04.31.05 for\n\t<gcc-patches@gcc.gnu.org> (version=TLS1_2\n\tcipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tMon, 04 Sep 2017 04:31:06 -0700 (PDT)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:subject:references:date:in-reply-to:message-id:mime-version\n\t:content-type; q=dns; s=default; b=qElkDamepYWj0tustPNX4zU46kSsG\n\tQBbrR03UT7DXBf+KHUDF+ZDxDB+z6YnUsALI1kedXTOH4+Eou+nZIMsWk5uFtJ3m\n\tACza/rGItjVVuNnmV7pVmZeo+wKLFwv7PaQ0LhOx733HwuhbdVrAv7qIN2Aq0Pan\n\tB8u0dmcyCmFsdc=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:subject:references:date:in-reply-to:message-id:mime-version\n\t:content-type; s=default; bh=WOXzyqgMDTbtmptJi3T/V0Lrqfg=; b=xNU\n\t+JpwSFSC2wWoqGVkCKIu1SWjSK25OwM327PKNPKm+EJ6GyvxCzs5n8CJ2dSWqYBW\n\tCpmvxzs4UIhqQ/T5KPwSpdotbGJDY4C8tCATd0sbEExtKQ1Fr7WboHM5YI7/pO/N\n\tLIZfB/ssWCxRZ2uP/4sxzUuZdh85rhYaK1qy38Xo=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-10.6 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=occasions", "X-HELO": "mail-wm0-f45.google.com", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:from:to:mail-followup-to:subject:references:date\n\t:in-reply-to:message-id:user-agent:mime-version;\n\tbh=ejrVS63Ax8EKPFvg7vXJbD6VlVZwP2Gk8JGHGPtNoVw=;\n\tb=eTVI0InQwCRDkSl18YAS1iFrQ/wPoUXZTIjm/eSD5fOLe1PZehpK3jg2C+/KATyG2a\n\tHAMweg80jWNhRCIj8R7aPnaNyDOYOsHIlRFEsKgoAaWDWUlRg0zOuiYTkdlLIBj3MjDz\n\tBw9c3ru3o3nWRK9XqNZoZgynK8+WWzr9KxO96gJZytJUrEU3pxvgHCAtxfWLM09uDlZN\n\tSQQpjhbXvDq5rj/PI5oWMv11UAGmbYI8o2u8/XqXdrrI+RmvGjDXqUImBE/yA0im47Ez\n\tN5rThWpTpsQU9cYAVy3a2YOsaq4b9jAxgqDd2ydgKaYZ0nZsLiBbV1u4CAdJxrxkpcnj\n\tK/rg==", "X-Gm-Message-State": "AHPjjUixWGdrT9tz7Aw0lW5PlRn4D3c/BFvaxVdjR12cQx8C2nMHP7hi\tD4KRlOsCcVgrro9W4VVlkQ==", "X-Google-Smtp-Source": "ADKCNb6WDPxlcyDCxst272NxJwN57obIi4NpeIzptvlGir9R5ZfVa9hGidHmdLciwG+qXqVrdKrsBA==", "X-Received": "by 10.28.148.75 with SMTP id w72mr353274wmd.132.1504524667108;\n\tMon, 04 Sep 2017 04:31:07 -0700 (PDT)", "From": "Richard Sandiford <richard.sandiford@linaro.org>", "To": "gcc-patches@gcc.gnu.org", "Mail-Followup-To": "gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org", "Subject": "[2/9] Make more use of int_mode_for_size", "References": "<87tw0iiu51.fsf@linaro.org>", "Date": "Mon, 04 Sep 2017 12:31:04 +0100", "In-Reply-To": "<87tw0iiu51.fsf@linaro.org> (Richard Sandiford's message of\n\t\"Mon, 04 Sep 2017 12:24:26 +0100\")", "Message-ID": "<87lgluittz.fsf@linaro.org>", "User-Agent": "Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux)", "MIME-Version": "1.0", "Content-Type": "text/plain" }, "content": "This patch converts more places that could use int_mode_for_size instead\nof mode_for_size. This is in preparation for an upcoming patch that\nmakes mode_for_size itself return an opt_mode.\n\nrequire () seems like the right choice in expand_builtin_powi\nbecause we have got past the point of backing out. We go on to do:\n\n op1 = expand_expr (arg1, NULL_RTX, mode2, EXPAND_NORMAL);\n if (GET_MODE (op1) != mode2)\n op1 = convert_to_mode (mode2, op1, 0);\n\nwhich would be invalid for (and have failed for) BLKmode.\n\nIn get_builtin_sync_mode and expand_ifn_atomic_compare_exchange,\nthe possible bitsizes are {8, 16, 32, 64, 128}, all of which give\ntarget-independent integer modes (up to TImode). The comment above\nthe call in get_builtin_sync_mode makes clear that an integer mode\nmust be found.\n\nWe can use require () in expand_builtin_atomic_clear and\nexpand_builtin_atomic_test_and_set because there's always an integer\nmode for the boolean type. The same goes for the POINTER_SIZE request\nin layout_type. Similarly we can use require () in combine_instructions\nand gen_lowpart_common because there's always an integer mode for\nHOST_BITS_PER_WIDE_INT (DImode when BITS_PER_UNIT == 8), and\nHOST_BITS_PER_DOUBLE_INT (TImode).\n\nThe calls in aarch64_function_value, arm_function_value,\naapcs_allocate_return_reg and mips_function_value_1 are handling\ncases in which a big-endian target passes or returns values at\nthe most significant end of a register. In each case the ABI\nconstrains the size to a small amount and does not handle\nnon-power-of-2 sizes wider than a word.\n\nThe calls in c6x_expand_movmem, i386.c:emit_memset,\nlm32_block_move_inline, microblaze_block_move_straight and\nmips_block_move_straight are dealing with expansions of\nblock memory operations using register-wise operations,\nand those registers must have non-BLK mode.\n\nThe reason for using require () in ix86_expand_sse_cmp,\nmips_expand_ins_as_unaligned_store, spu.c:adjust_operand and\nspu_emit_branch_and_set is that we go on to emit non-call\ninstructions that use registers of that mode, which wouldn't\nbe valid for BLKmode.\n\n2017-09-04 Richard Sandiford <richard.sandiford@linaro.org>\n\ngcc/\n\t* builtins.c (expand_builtin_powi): Use int_mode_for_size.\n\t(get_builtin_sync_mode): Likewise.\n\t(expand_ifn_atomic_compare_exchange): Likewise.\n\t(expand_builtin_atomic_clear): Likewise.\n\t(expand_builtin_atomic_test_and_set): Likewise.\n\t(fold_builtin_atomic_always_lock_free): Likewise.\n\t* calls.c (compute_argument_addresses): Likewise.\n\t(emit_library_call_value_1): Likewise.\n\t(store_one_arg): Likewise.\n\t* combine.c (combine_instructions): Likewise.\n\t* config/aarch64/aarch64.c (aarch64_function_value): Likewise.\n\t* config/arm/arm.c (arm_function_value): Likewise.\n\t(aapcs_allocate_return_reg): Likewise.\n\t* config/c6x/c6x.c (c6x_expand_movmem): Likewise.\n\t* config/i386/i386.c (construct_container): Likewise.\n\t(ix86_gimplify_va_arg): Likewise.\n\t(ix86_expand_sse_cmp): Likewise.\n\t(emit_memmov): Likewise.\n\t(emit_memset): Likewise.\n\t(expand_small_movmem_or_setmem): Likewise.\n\t(ix86_expand_pextr): Likewise.\n\t(ix86_expand_pinsr): Likewise.\n\t* config/lm32/lm32.c (lm32_block_move_inline): Likewise.\n\t* config/microblaze/microblaze.c (microblaze_block_move_straight):\n\tLikewise.\n\t* config/mips/mips.c (mips_function_value_1) Likewise.\n\t(mips_block_move_straight): Likewise.\n\t(mips_expand_ins_as_unaligned_store): Likewise.\n\t* config/powerpcspe/powerpcspe.c\n\t(rs6000_darwin64_record_arg_advance_flush): Likewise.\n\t(rs6000_darwin64_record_arg_flush): Likewise.\n\t* config/rs6000/rs6000.c\n\t(rs6000_darwin64_record_arg_advance_flush): Likewise.\n\t(rs6000_darwin64_record_arg_flush): Likewise.\n\t* config/sparc/sparc.c (sparc_function_arg_1): Likewise.\n\t(sparc_function_value_1): Likewise.\n\t* config/spu/spu.c (adjust_operand): Likewise.\n\t(spu_emit_branch_or_set): Likewise.\n\t(arith_immediate_p): Likewise.\n\t* emit-rtl.c (gen_lowpart_common): Likewise.\n\t* expr.c (expand_expr_real_1): Likewise.\n\t* function.c (assign_parm_setup_block): Likewise.\n\t* gimple-ssa-store-merging.c (encode_tree_to_bitpos): Likewise.\n\t* reload1.c (alter_reg): Likewise.\n\t* stor-layout.c (mode_for_vector): Likewise.\n\t(layout_type): Likewise.\n\ngcc/ada/\n\t* gcc-interface/utils2.c (build_load_modify_store):\n\tUse int_mode_for_size.", "diff": "Index: gcc/builtins.c\n===================================================================\n--- gcc/builtins.c\t2017-09-04 08:30:09.328308115 +0100\n+++ gcc/builtins.c\t2017-09-04 12:18:44.865115639 +0100\n@@ -2755,7 +2755,7 @@ expand_builtin_powi (tree exp, rtx targe\n /* Emit a libcall to libgcc. */\n \n /* Mode of the 2nd argument must match that of an int. */\n- mode2 = mode_for_size (INT_TYPE_SIZE, MODE_INT, 0);\n+ mode2 = int_mode_for_size (INT_TYPE_SIZE, 0).require ();\n \n if (target == NULL_RTX)\n target = gen_reg_rtx (mode);\n@@ -5477,7 +5477,7 @@ get_builtin_sync_mode (int fcode_diff)\n {\n /* The size is not negotiable, so ask not to get BLKmode in return\n if the target indicates that a smaller size would be better. */\n- return mode_for_size (BITS_PER_UNIT << fcode_diff, MODE_INT, 0);\n+ return int_mode_for_size (BITS_PER_UNIT << fcode_diff, 0).require ();\n }\n \n /* Expand the memory expression LOC and return the appropriate memory operand\n@@ -5858,7 +5858,7 @@ expand_ifn_atomic_compare_exchange (gcal\n {\n int size = tree_to_shwi (gimple_call_arg (call, 3)) & 255;\n gcc_assert (size == 1 || size == 2 || size == 4 || size == 8 || size == 16);\n- machine_mode mode = mode_for_size (BITS_PER_UNIT * size, MODE_INT, 0);\n+ machine_mode mode = int_mode_for_size (BITS_PER_UNIT * size, 0).require ();\n rtx expect, desired, mem, oldval, boolret;\n enum memmodel success, failure;\n tree lhs;\n@@ -6154,7 +6154,7 @@ expand_builtin_atomic_clear (tree exp)\n rtx mem, ret;\n enum memmodel model;\n \n- mode = mode_for_size (BOOL_TYPE_SIZE, MODE_INT, 0);\n+ mode = int_mode_for_size (BOOL_TYPE_SIZE, 0).require ();\n mem = get_builtin_sync_mem (CALL_EXPR_ARG (exp, 0), mode);\n model = get_memmodel (CALL_EXPR_ARG (exp, 1));\n \n@@ -6189,7 +6189,7 @@ expand_builtin_atomic_test_and_set (tree\n enum memmodel model;\n machine_mode mode;\n \n- mode = mode_for_size (BOOL_TYPE_SIZE, MODE_INT, 0);\n+ mode = int_mode_for_size (BOOL_TYPE_SIZE, 0).require ();\n mem = get_builtin_sync_mem (CALL_EXPR_ARG (exp, 0), mode);\n model = get_memmodel (CALL_EXPR_ARG (exp, 1));\n \n@@ -6210,8 +6210,11 @@ fold_builtin_atomic_always_lock_free (tr\n if (TREE_CODE (arg0) != INTEGER_CST)\n return NULL_TREE;\n \n+ /* We need a corresponding integer mode for the access to be lock-free. */\n size = INTVAL (expand_normal (arg0)) * BITS_PER_UNIT;\n- mode = mode_for_size (size, MODE_INT, 0);\n+ if (!int_mode_for_size (size, 0).exists (&mode))\n+ return boolean_false_node;\n+\n mode_align = GET_MODE_ALIGNMENT (mode);\n \n if (TREE_CODE (arg1) == INTEGER_CST)\nIndex: gcc/calls.c\n===================================================================\n--- gcc/calls.c\t2017-09-04 11:50:24.542663572 +0100\n+++ gcc/calls.c\t2017-09-04 12:18:44.866121179 +0100\n@@ -2209,8 +2209,8 @@ compute_argument_addresses (struct arg_d\n \t /* Only part of the parameter is being passed on the stack.\n \t\t Generate a simple memory reference of the correct size. */\n \t units_on_stack = args[i].locate.size.constant;\n-\t partial_mode = mode_for_size (units_on_stack * BITS_PER_UNIT,\n-\t\t\t\t\t MODE_INT, 1);\n+\t unsigned int bits_on_stack = units_on_stack * BITS_PER_UNIT;\n+\t partial_mode = int_mode_for_size (bits_on_stack, 1).else_blk ();\n \t args[i].stack = gen_rtx_MEM (partial_mode, addr);\n \t set_mem_size (args[i].stack, units_on_stack);\n \t }\n@@ -4818,7 +4818,7 @@ emit_library_call_value_1 (int retval, r\n \t\t unsigned int size\n \t\t = argvec[argnum].locate.size.constant * BITS_PER_UNIT;\n \t\t machine_mode save_mode\n-\t\t = mode_for_size (size, MODE_INT, 1);\n+\t\t = int_mode_for_size (size, 1).else_blk ();\n \t\t rtx adr\n \t\t = plus_constant (Pmode, argblock,\n \t\t\t\t argvec[argnum].locate.offset.constant);\n@@ -5271,7 +5271,8 @@ store_one_arg (struct arg_data *arg, rtx\n \t {\n \t /* We need to make a save area. */\n \t unsigned int size = arg->locate.size.constant * BITS_PER_UNIT;\n-\t machine_mode save_mode = mode_for_size (size, MODE_INT, 1);\n+\t machine_mode save_mode\n+\t\t= int_mode_for_size (size, 1).else_blk ();\n \t rtx adr = memory_address (save_mode, XEXP (arg->stack_slot, 0));\n \t rtx stack_area = gen_rtx_MEM (save_mode, adr);\n \nIndex: gcc/combine.c\n===================================================================\n--- gcc/combine.c\t2017-09-04 11:50:08.502225206 +0100\n+++ gcc/combine.c\t2017-09-04 12:18:44.871148881 +0100\n@@ -370,7 +370,7 @@ alloc_insn_link (rtx_insn *insn, unsigne\n /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the\n largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */\n \n-static machine_mode nonzero_bits_mode;\n+static scalar_int_mode nonzero_bits_mode;\n \n /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can\n be safely used. It is zero while computing them and after combine has\n@@ -1157,7 +1157,7 @@ combine_instructions (rtx_insn *f, unsig\n uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);\n gcc_obstack_init (&insn_link_obstack);\n \n- nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);\n+ nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();\n \n /* Don't use reg_stat[].nonzero_bits when computing it. This can cause\n problems when, for example, we have j <<= 1 in a loop. */\nIndex: gcc/config/aarch64/aarch64.c\n===================================================================\n--- gcc/config/aarch64/aarch64.c\t2017-09-04 11:50:24.544464351 +0100\n+++ gcc/config/aarch64/aarch64.c\t2017-09-04 12:18:44.874165502 +0100\n@@ -2235,7 +2235,7 @@ aarch64_function_value (const_tree type,\n if (size % UNITS_PER_WORD != 0)\n \t{\n \t size += UNITS_PER_WORD - size % UNITS_PER_WORD;\n-\t mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);\n+\t mode = int_mode_for_size (size * BITS_PER_UNIT, 0).require ();\n \t}\n }\n \nIndex: gcc/config/arm/arm.c\n===================================================================\n--- gcc/config/arm/arm.c\t2017-09-04 11:50:24.546265130 +0100\n+++ gcc/config/arm/arm.c\t2017-09-04 12:18:44.886231985 +0100\n@@ -5358,7 +5358,7 @@ arm_function_value(const_tree type, cons\n if (size % UNITS_PER_WORD != 0)\n \t{\n \t size += UNITS_PER_WORD - size % UNITS_PER_WORD;\n-\t mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);\n+\t mode = int_mode_for_size (size * BITS_PER_UNIT, 0).require ();\n \t}\n }\n \n@@ -6315,7 +6315,7 @@ aapcs_allocate_return_reg (machine_mode\n if (size % UNITS_PER_WORD != 0)\n \t{\n \t size += UNITS_PER_WORD - size % UNITS_PER_WORD;\n-\t mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);\n+\t mode = int_mode_for_size (size * BITS_PER_UNIT, 0).require ();\n \t}\n }\n \nIndex: gcc/config/c6x/c6x.c\n===================================================================\n--- gcc/config/c6x/c6x.c\t2017-09-04 11:50:08.509428322 +0100\n+++ gcc/config/c6x/c6x.c\t2017-09-04 12:18:44.887237526 +0100\n@@ -1758,8 +1758,8 @@ c6x_expand_movmem (rtx dst, rtx src, rtx\n if (dst_size > src_size)\n \tdst_size = src_size;\n \n- srcmode = mode_for_size (src_size * BITS_PER_UNIT, MODE_INT, 0);\n- dstmode = mode_for_size (dst_size * BITS_PER_UNIT, MODE_INT, 0);\n+ srcmode = int_mode_for_size (src_size * BITS_PER_UNIT, 0).require ();\n+ dstmode = int_mode_for_size (dst_size * BITS_PER_UNIT, 0).require ();\n if (src_size >= 4)\n \treg_lowpart = reg = gen_reg_rtx (srcmode);\n else\nIndex: gcc/config/i386/i386.c\n===================================================================\n--- gcc/config/i386/i386.c\t2017-09-04 11:50:08.515731048 +0100\n+++ gcc/config/i386/i386.c\t2017-09-04 12:18:44.903326171 +0100\n@@ -9892,16 +9892,17 @@ construct_container (machine_mode mode,\n \t case X86_64_INTEGERSI_CLASS:\n \t /* Merge TImodes on aligned occasions here too. */\n \t if (i * 8 + 8 > bytes)\n-\t tmpmode\n-\t\t= mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);\n+\t {\n+\t\tunsigned int tmpbits = (bytes - i * 8) * BITS_PER_UNIT;\n+\t\tif (!int_mode_for_size (tmpbits, 0).exists (&tmpmode))\n+\t\t /* We've requested 24 bytes we\n+\t\t don't have mode for. Use DImode. */\n+\t\t tmpmode = DImode;\n+\t }\n \t else if (regclass[i] == X86_64_INTEGERSI_CLASS)\n \t tmpmode = SImode;\n \t else\n \t tmpmode = DImode;\n-\t /* We've requested 24 bytes we\n-\t don't have mode for. Use DImode. */\n-\t if (tmpmode == BLKmode)\n-\t tmpmode = DImode;\n \t exp [nexps++]\n \t = gen_rtx_EXPR_LIST (VOIDmode,\n \t\t\t\t gen_rtx_REG (tmpmode, *intreg),\n@@ -11880,8 +11881,8 @@ ix86_gimplify_va_arg (tree valist, tree\n \t if (prev_size + cur_size > size)\n \t\t{\n \t\t cur_size = size - prev_size;\n-\t\t mode = mode_for_size (cur_size * BITS_PER_UNIT, MODE_INT, 1);\n-\t\t if (mode == BLKmode)\n+\t\t unsigned int nbits = cur_size * BITS_PER_UNIT;\n+\t\t if (!int_mode_for_size (nbits, 1).exists (&mode))\n \t\t mode = QImode;\n \t\t}\n \t piece_type = lang_hooks.types.type_for_mode (mode, 1);\n@@ -24807,9 +24808,8 @@ ix86_expand_sse_cmp (rtx dest, enum rtx_\n \n if (GET_MODE_SIZE (cmp_ops_mode) == 64)\n {\n- cmp_mode = mode_for_size (GET_MODE_NUNITS (cmp_ops_mode), MODE_INT, 0);\n- gcc_assert (cmp_mode != BLKmode);\n-\n+ unsigned int nbits = GET_MODE_NUNITS (cmp_ops_mode);\n+ cmp_mode = int_mode_for_size (nbits, 0).require ();\n maskcmp = true;\n }\n else\n@@ -27408,13 +27408,11 @@ emit_memmov (rtx destmem, rtx *srcmem, r\n Start with the biggest power of 2 less than SIZE_TO_MOVE and half\n it until move of such size is supported. */\n piece_size = 1 << floor_log2 (size_to_move);\n- move_mode = mode_for_size (piece_size * BITS_PER_UNIT, MODE_INT, 0);\n- code = optab_handler (mov_optab, move_mode);\n- while (code == CODE_FOR_nothing && piece_size > 1)\n+ while (!int_mode_for_size (piece_size * BITS_PER_UNIT, 0).exists (&move_mode)\n+\t || (code = optab_handler (mov_optab, move_mode)) == CODE_FOR_nothing)\n {\n+ gcc_assert (piece_size > 1);\n piece_size >>= 1;\n- move_mode = mode_for_size (piece_size * BITS_PER_UNIT, MODE_INT, 0);\n- code = optab_handler (mov_optab, move_mode);\n }\n \n /* Find the corresponding vector mode with the same size as MOVE_MODE.\n@@ -27597,7 +27595,8 @@ emit_memset (rtx destmem, rtx destptr, r\n move_mode = QImode;\n if (size_to_move < GET_MODE_SIZE (move_mode))\n {\n- move_mode = mode_for_size (size_to_move * BITS_PER_UNIT, MODE_INT, 0);\n+ unsigned int move_bits = size_to_move * BITS_PER_UNIT;\n+ move_mode = int_mode_for_size (move_bits, 0).require ();\n promoted_val = gen_lowpart (move_mode, promoted_val);\n }\n piece_size = GET_MODE_SIZE (move_mode);\n@@ -27792,7 +27791,7 @@ expand_small_movmem_or_setmem (rtx destm\n \t\t\t rtx done_label, bool issetmem)\n {\n rtx_code_label *label = ix86_expand_aligntest (count, size, false);\n- machine_mode mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 1);\n+ machine_mode mode = int_mode_for_size (size * BITS_PER_UNIT, 1).else_blk ();\n rtx modesize;\n int n;\n \n@@ -50453,7 +50452,8 @@ ix86_expand_pextr (rtx *operands)\n \tmachine_mode srcmode, dstmode;\n \trtx d, pat;\n \n-\tdstmode = mode_for_size (size, MODE_INT, 0);\n+\tif (!int_mode_for_size (size, 0).exists (&dstmode))\n+\t return false;\n \n \tswitch (dstmode)\n \t {\n@@ -50549,7 +50549,8 @@ ix86_expand_pinsr (rtx *operands)\n \trtx (*pinsr)(rtx, rtx, rtx, rtx);\n \trtx d;\n \n-\tsrcmode = mode_for_size (size, MODE_INT, 0);\n+\tif (!int_mode_for_size (size, 0).exists (&srcmode))\n+\t return false;\n \n \tswitch (srcmode)\n \t {\nIndex: gcc/config/lm32/lm32.c\n===================================================================\n--- gcc/config/lm32/lm32.c\t2017-09-04 11:50:08.517531827 +0100\n+++ gcc/config/lm32/lm32.c\t2017-09-04 12:18:44.903326171 +0100\n@@ -836,7 +836,7 @@ lm32_block_move_inline (rtx dest, rtx sr\n break;\n }\n \n- mode = mode_for_size (bits, MODE_INT, 0);\n+ mode = int_mode_for_size (bits, 0).require ();\n delta = bits / BITS_PER_UNIT;\n \n /* Allocate a buffer for the temporary registers. */\nIndex: gcc/config/microblaze/microblaze.c\n===================================================================\n--- gcc/config/microblaze/microblaze.c\t2017-09-04 11:50:08.520232996 +0100\n+++ gcc/config/microblaze/microblaze.c\t2017-09-04 12:18:44.904331711 +0100\n@@ -1087,7 +1087,7 @@ microblaze_block_move_straight (rtx dest\n rtx *regs;\n \n bits = BITS_PER_WORD;\n- mode = mode_for_size (bits, MODE_INT, 0);\n+ mode = int_mode_for_size (bits, 0).require ();\n delta = bits / BITS_PER_UNIT;\n \n /* Allocate a buffer for the temporary registers. */\nIndex: gcc/config/mips/mips.c\n===================================================================\n--- gcc/config/mips/mips.c\t2017-09-04 11:50:24.550767077 +0100\n+++ gcc/config/mips/mips.c\t2017-09-04 12:18:44.906342792 +0100\n@@ -6384,7 +6384,7 @@ mips_function_value_1 (const_tree valtyp\n \t if (size % UNITS_PER_WORD != 0)\n \t {\n \t size += UNITS_PER_WORD - size % UNITS_PER_WORD;\n-\t mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);\n+\t mode = int_mode_for_size (size * BITS_PER_UNIT, 0).require ();\n \t }\n \t}\n \n@@ -7992,7 +7992,7 @@ mips_block_move_straight (rtx dest, rtx\n \tbits = BITS_PER_WORD;\n }\n \n- mode = mode_for_size (bits, MODE_INT, 0);\n+ mode = int_mode_for_size (bits, 0).require ();\n delta = bits / BITS_PER_UNIT;\n \n /* Allocate a buffer for the temporary registers. */\n@@ -8397,7 +8397,7 @@ mips_expand_ins_as_unaligned_store (rtx\n if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))\n return false;\n \n- mode = mode_for_size (width, MODE_INT, 0);\n+ mode = int_mode_for_size (width, 0).require ();\n src = gen_lowpart (mode, src);\n if (mode == DImode)\n {\nIndex: gcc/config/powerpcspe/powerpcspe.c\n===================================================================\n--- gcc/config/powerpcspe/powerpcspe.c\t2017-09-04 11:50:24.557069804 +0100\n+++ gcc/config/powerpcspe/powerpcspe.c\t2017-09-04 12:18:44.919414816 +0100\n@@ -12222,7 +12222,6 @@ rs6000_darwin64_record_arg_advance_flush\n {\n unsigned int startbit, endbit;\n int intregs, intoffset;\n- machine_mode mode;\n \n /* Handle the situations where a float is taking up the first half\n of the GPR, and the other half is empty (typically due to\n@@ -12246,9 +12245,8 @@ rs6000_darwin64_record_arg_advance_flush\n \n if (intoffset % BITS_PER_WORD != 0)\n {\n- mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,\n-\t\t\t MODE_INT, 0);\n- if (mode == BLKmode)\n+ unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;\n+ if (!int_mode_for_size (bits, 0).exists ())\n \t{\n \t /* We couldn't find an appropriate mode, which happens,\n \t e.g., in packed structs when there are 3 bytes to load.\n@@ -12714,9 +12712,8 @@ rs6000_darwin64_record_arg_flush (CUMULA\n \n if (intoffset % BITS_PER_WORD != 0)\n {\n- mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,\n-\t\t\t MODE_INT, 0);\n- if (mode == BLKmode)\n+ unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;\n+ if (!int_mode_for_size (bits, 0).exists (&mode))\n \t{\n \t /* We couldn't find an appropriate mode, which happens,\n \t e.g., in packed structs when there are 3 bytes to load.\nIndex: gcc/config/rs6000/rs6000.c\n===================================================================\n--- gcc/config/rs6000/rs6000.c\t2017-09-04 11:50:24.560671361 +0100\n+++ gcc/config/rs6000/rs6000.c\t2017-09-04 12:18:44.929470219 +0100\n@@ -11654,7 +11654,6 @@ rs6000_darwin64_record_arg_advance_flush\n {\n unsigned int startbit, endbit;\n int intregs, intoffset;\n- machine_mode mode;\n \n /* Handle the situations where a float is taking up the first half\n of the GPR, and the other half is empty (typically due to\n@@ -11678,9 +11677,8 @@ rs6000_darwin64_record_arg_advance_flush\n \n if (intoffset % BITS_PER_WORD != 0)\n {\n- mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,\n-\t\t\t MODE_INT, 0);\n- if (mode == BLKmode)\n+ unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;\n+ if (!int_mode_for_size (bits, 0).exists ())\n \t{\n \t /* We couldn't find an appropriate mode, which happens,\n \t e.g., in packed structs when there are 3 bytes to load.\n@@ -12049,9 +12047,8 @@ rs6000_darwin64_record_arg_flush (CUMULA\n \n if (intoffset % BITS_PER_WORD != 0)\n {\n- mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,\n-\t\t\t MODE_INT, 0);\n- if (mode == BLKmode)\n+ unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;\n+ if (!int_mode_for_size (bits, 0).exists (&mode))\n \t{\n \t /* We couldn't find an appropriate mode, which happens,\n \t e.g., in packed structs when there are 3 bytes to load.\nIndex: gcc/config/sparc/sparc.c\n===================================================================\n--- gcc/config/sparc/sparc.c\t2017-09-04 11:50:24.562472140 +0100\n+++ gcc/config/sparc/sparc.c\t2017-09-04 12:18:44.932486840 +0100\n@@ -7123,7 +7123,7 @@ sparc_function_arg_1 (cumulative_args_t\n HOST_WIDE_INT size = int_size_in_bytes (type);\n gcc_assert (size <= 16);\n \n- mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);\n+ mode = int_mode_for_size (size * BITS_PER_UNIT, 0).else_blk ();\n }\n \n return gen_rtx_REG (mode, regno);\n@@ -7499,7 +7499,7 @@ sparc_function_value_1 (const_tree type,\n \t HOST_WIDE_INT size = int_size_in_bytes (type);\n \t gcc_assert (size <= 32);\n \n-\t mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);\n+\t mode = int_mode_for_size (size * BITS_PER_UNIT, 0).else_blk ();\n \n \t /* ??? We probably should have made the same ABI change in\n \t 3.4.0 as the one we made for unions. The latter was\nIndex: gcc/config/spu/spu.c\n===================================================================\n--- gcc/config/spu/spu.c\t2017-09-04 12:18:41.572976650 +0100\n+++ gcc/config/spu/spu.c\t2017-09-04 12:18:44.934497920 +0100\n@@ -368,7 +368,7 @@ adjust_operand (rtx op, HOST_WIDE_INT *\n op_size = 32;\n }\n /* If it is not a MODE_INT (and/or it is smaller than SI) add a SUBREG. */\n- mode = mode_for_size (op_size, MODE_INT, 0);\n+ mode = int_mode_for_size (op_size, 0).require ();\n if (mode != GET_MODE (op))\n op = gen_rtx_SUBREG (mode, op, 0);\n return op;\n@@ -935,7 +935,7 @@ spu_emit_branch_or_set (int is_set, rtx\n rtx target = operands[0];\n int compare_size = GET_MODE_BITSIZE (comp_mode);\n int target_size = GET_MODE_BITSIZE (GET_MODE (target));\n- machine_mode mode = mode_for_size (target_size, MODE_INT, 0);\n+ machine_mode mode = int_mode_for_size (target_size, 0).require ();\n rtx select_mask;\n rtx op_t = operands[2];\n rtx op_f = operands[3];\nIndex: gcc/emit-rtl.c\n===================================================================\n--- gcc/emit-rtl.c\t2017-09-04 11:48:27.399539901 +0100\n+++ gcc/emit-rtl.c\t2017-09-04 12:18:44.935503461 +0100\n@@ -1430,9 +1430,9 @@ gen_lowpart_common (machine_mode mode, r\n innermode = GET_MODE (x);\n if (CONST_INT_P (x)\n && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT)\n- innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);\n+ innermode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();\n else if (innermode == VOIDmode)\n- innermode = mode_for_size (HOST_BITS_PER_DOUBLE_INT, MODE_INT, 0);\n+ innermode = int_mode_for_size (HOST_BITS_PER_DOUBLE_INT, 0).require ();\n \n xsize = GET_MODE_SIZE (innermode);\n \nIndex: gcc/expr.c\n===================================================================\n--- gcc/expr.c\t2017-09-04 11:50:24.566974088 +0100\n+++ gcc/expr.c\t2017-09-04 12:18:44.938520082 +0100\n@@ -10680,7 +10680,7 @@ expand_expr_real_1 (tree exp, rtx target\n \t\t&& ! (target != 0 && MEM_P (op0)\n \t\t && MEM_P (target)\n \t\t && bitpos % BITS_PER_UNIT == 0))\n-\t ext_mode = mode_for_size (bitsize, MODE_INT, 1);\n+\t ext_mode = int_mode_for_size (bitsize, 1).else_blk ();\n \n \t if (ext_mode == BLKmode)\n \t {\nIndex: gcc/function.c\n===================================================================\n--- gcc/function.c\t2017-09-04 11:50:24.567874477 +0100\n+++ gcc/function.c\t2017-09-04 12:18:44.940531162 +0100\n@@ -2978,8 +2978,8 @@ assign_parm_setup_block (struct assign_p\n \t that mode's store operation. */\n else if (size <= UNITS_PER_WORD)\n \t{\n-\t machine_mode mode\n-\t = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);\n+\t unsigned int bits = size * BITS_PER_UNIT;\n+\t machine_mode mode = int_mode_for_size (bits, 0).else_blk ();\n \n \t if (mode != BLKmode\n #ifdef BLOCK_REG_PADDING\nIndex: gcc/gimple-ssa-store-merging.c\n===================================================================\n--- gcc/gimple-ssa-store-merging.c\t2017-07-27 10:37:56.776048721 +0100\n+++ gcc/gimple-ssa-store-merging.c\t2017-09-04 12:18:44.941536703 +0100\n@@ -354,7 +354,7 @@ encode_tree_to_bitpos (tree expr, unsign\n tree tmp_int = expr;\n bool sub_byte_op_p = ((bitlen % BITS_PER_UNIT)\n \t\t\t|| (bitpos % BITS_PER_UNIT)\n-\t\t\t|| mode_for_size (bitlen, MODE_INT, 0) == BLKmode);\n+\t\t\t|| !int_mode_for_size (bitlen, 0).exists ());\n \n if (!sub_byte_op_p)\n return (native_encode_expr (tmp_int, ptr + first_byte, total_bytes, 0)\nIndex: gcc/reload1.c\n===================================================================\n--- gcc/reload1.c\t2017-09-04 11:49:42.942500722 +0100\n+++ gcc/reload1.c\t2017-09-04 12:18:44.943547783 +0100\n@@ -2189,11 +2189,12 @@ alter_reg (int i, int from_reg, bool don\n \t {\n \t adjust = inherent_size - total_size;\n \t if (adjust)\n-\t\tstack_slot\n-\t\t = adjust_address_nv (x, mode_for_size (total_size\n-\t\t\t\t\t\t * BITS_PER_UNIT,\n-\t\t\t\t\t\t MODE_INT, 1),\n-\t\t\t\t adjust);\n+\t\t{\n+\t\t unsigned int total_bits = total_size * BITS_PER_UNIT;\n+\t\t machine_mode mem_mode\n+\t\t = int_mode_for_size (total_bits, 1).else_blk ();\n+\t\t stack_slot = adjust_address_nv (x, mem_mode, adjust);\n+\t\t}\n \t }\n \n \t if (! dont_share_p && ira_conflicts_p)\n@@ -2240,11 +2241,12 @@ alter_reg (int i, int from_reg, bool don\n \t {\n \t adjust = GET_MODE_SIZE (mode) - total_size;\n \t if (adjust)\n-\t\tstack_slot\n-\t\t = adjust_address_nv (x, mode_for_size (total_size\n-\t\t\t\t\t\t\t * BITS_PER_UNIT,\n-\t\t\t\t\t\t\t MODE_INT, 1),\n-\t\t\t\t adjust);\n+\t\t{\n+\t\t unsigned int total_bits = total_size * BITS_PER_UNIT;\n+\t\t machine_mode mem_mode\n+\t\t = int_mode_for_size (total_bits, 1).else_blk ();\n+\t\t stack_slot = adjust_address_nv (x, mem_mode, adjust);\n+\t\t}\n \t }\n \n \t spill_stack_slot[from_reg] = stack_slot;\nIndex: gcc/stor-layout.c\n===================================================================\n--- gcc/stor-layout.c\t2017-08-30 12:20:41.643620906 +0100\n+++ gcc/stor-layout.c\t2017-09-04 12:18:44.944553324 +0100\n@@ -506,8 +506,10 @@ mode_for_vector (scalar_mode innermode,\n /* For integers, try mapping it to a same-sized scalar mode. */\n if (mode == VOIDmode\n && GET_MODE_CLASS (innermode) == MODE_INT)\n- mode = mode_for_size (nunits * GET_MODE_BITSIZE (innermode),\n-\t\t\t MODE_INT, 0);\n+ {\n+ unsigned int nbits = nunits * GET_MODE_BITSIZE (innermode);\n+ mode = int_mode_for_size (nbits, 0).else_blk ();\n+ }\n \n if (mode == VOIDmode\n || (GET_MODE_CLASS (mode) == MODE_INT\n@@ -2295,7 +2297,7 @@ layout_type (tree type)\n TYPE_SIZE_UNIT (type) = size_int (POINTER_SIZE_UNITS);\n /* A pointer might be MODE_PARTIAL_INT, but ptrdiff_t must be\n \t integral, which may be an __intN. */\n- SET_TYPE_MODE (type, mode_for_size (POINTER_SIZE, MODE_INT, 0));\n+ SET_TYPE_MODE (type, int_mode_for_size (POINTER_SIZE, 0).require ());\n TYPE_PRECISION (type) = POINTER_SIZE;\n break;\n \n@@ -2304,7 +2306,8 @@ layout_type (tree type)\n /* It's hard to see what the mode and size of a function ought to\n \t be, but we do know the alignment is FUNCTION_BOUNDARY, so\n \t make it consistent with that. */\n- SET_TYPE_MODE (type, mode_for_size (FUNCTION_BOUNDARY, MODE_INT, 0));\n+ SET_TYPE_MODE (type,\n+\t\t int_mode_for_size (FUNCTION_BOUNDARY, 0).else_blk ());\n TYPE_SIZE (type) = bitsize_int (FUNCTION_BOUNDARY);\n TYPE_SIZE_UNIT (type) = size_int (FUNCTION_BOUNDARY / BITS_PER_UNIT);\n break;\nIndex: gcc/ada/gcc-interface/utils2.c\n===================================================================\n--- gcc/ada/gcc-interface/utils2.c\t2017-05-31 10:02:29.736972972 +0100\n+++ gcc/ada/gcc-interface/utils2.c\t2017-09-04 12:18:44.864110098 +0100\n@@ -800,7 +800,8 @@ build_load_modify_store (tree dest, tree\n \t\t{\n \t\t unsigned int size = tree_to_uhwi (TYPE_SIZE (type));\n \t\t type = copy_type (type);\n-\t\t SET_TYPE_MODE (type, mode_for_size (size, MODE_INT, 0));\n+\t\t machine_mode mode = int_mode_for_size (size, 0).else_blk ();\n+\t\t SET_TYPE_MODE (type, mode);\n \t\t}\n \n \t /* Create the temporary by inserting a SAVE_EXPR. */\n", "prefixes": [ "2/9" ] }