Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/809099/?format=api
{ "id": 809099, "url": "http://patchwork.ozlabs.org/api/patches/809099/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504367034-1000-3-git-send-email-bmeng.cn@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504367034-1000-3-git-send-email-bmeng.cn@gmail.com>", "list_archive_url": null, "date": "2017-09-02T15:43:54", "name": "[U-Boot,3/3] block: Drop the ftide020 driver", "commit_ref": "2c3b68081a6a13030f07e839dbb8cc29fb6a72c6", "pull_url": null, "state": "accepted", "archived": false, "hash": "9651ed103d40ad9bc86c7298486bf6da7cbe6aa5", "submitter": { "id": 64981, "url": "http://patchwork.ozlabs.org/api/people/64981/?format=api", "name": "Bin Meng", "email": "bmeng.cn@gmail.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504367034-1000-3-git-send-email-bmeng.cn@gmail.com/mbox/", "series": [ { "id": 1161, "url": "http://patchwork.ozlabs.org/api/series/1161/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1161", "date": "2017-09-02T15:43:52", "name": "[U-Boot,1/3] block: ide: Drop CONFIG_IDE_INIT_POSTRESET", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1161/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809099/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809099/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"asLjr98x\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xl0gH1F2Jz9sQl\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSun, 3 Sep 2017 01:40:27 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid C2D9CC21F21; Sat, 2 Sep 2017 15:39:54 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 97DFAC21EDF;\n\tSat, 2 Sep 2017 15:39:46 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 17EA4C21E61; Sat, 2 Sep 2017 15:39:38 +0000 (UTC)", "from mail-it0-f65.google.com (mail-it0-f65.google.com\n\t[209.85.214.65])\n\tby lists.denx.de (Postfix) with ESMTPS id 85C96C21DD9\n\tfor <u-boot@lists.denx.de>; Sat, 2 Sep 2017 15:39:34 +0000 (UTC)", "by mail-it0-f65.google.com with SMTP id k189so1174275itk.1\n\tfor <u-boot@lists.denx.de>; Sat, 02 Sep 2017 08:39:34 -0700 (PDT)", "from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com.\n\t[147.11.156.139]) by smtp.gmail.com with ESMTPSA id\n\tx87sm1425596ita.38.2017.09.02.08.39.31\n\t(version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tSat, 02 Sep 2017 08:39:32 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:subject:date:message-id:in-reply-to:references;\n\tbh=3cXqEWalUXlDU5j8g3FSqFw4RyHkW8feseoRNeY7mEE=;\n\tb=asLjr98xRph4VzEJREJG3APUaBLfZryP5HONsGZa/IlzQMo/DfVmYebrA3Vk0OqP9A\n\t8w9R27NsPvHJ1pU/FiCDl5zeizth9oxdEHSZPk/Uo9ZNEUoA8smCnhrET+sUP6xAggb1\n\tj+BvWLkYps12uIJFzYHaht1RUN7UgsYE7zT/cnV8I1+H+7MWrMfiYvDrijLOZxM7iK2i\n\tCYT5VsXdgVE/qXAn+11mM9PndvDiLT4RyQaLx4VFdFmOBaZxfS7xXLxGKGO8jFzhZvRj\n\tdmS1Us6BMn1Qw4OJrZ3XhFrH328KUwS2H/rhN3gfQXa6B10nRQXdvHqc345l1zCmtojy\n\tgrCw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=3cXqEWalUXlDU5j8g3FSqFw4RyHkW8feseoRNeY7mEE=;\n\tb=FkEx1JMcu7vZlHcc1uxuJM4GMI566WJ2QQVEbPtl85QcOsxyWoz6RjOHy1t+6NgAZU\n\t9n9/dBJrff3KZ0tWKiN74BNtpAuhZT88n1G66iyX9vbZuQXaQdORN2wXJPeCbfhm+2XW\n\ttlWxADqM58Vc2LmJmChCZBgPO87iEZa1AslWGw/irGhrFsllbiec/gABGs9ZvOyfEbw/\n\tD75dQVOzKdobg05jhzl7bB4esKxy3hc/USmR64OZDdVl82q16MDxfWaqjoanrrMAaA6v\n\tjm7lrEcEqvPFsZjtZYBdePjOF52ECKp3bJ5qPq9jqcQnAZ2mnUK3G3GhpymSSIW2G+u5\n\tlmeQ==", "X-Gm-Message-State": "AHPjjUhBcmUbPlxffOmwh1QI/TducPNmaNOYf7lLh+F3EmMNDdNfYBn6\n\tK3PB7GyL8Qqn3g==", "X-Google-Smtp-Source": "ADKCNb6d16zaJbOXEA8rVZ9jmGuOfFFRdUCc/snKELP0lzMy4MV0co563YItIaouNYaqFA81N6PT9g==", "X-Received": "by 10.36.190.130 with SMTP id i124mr1221962itf.181.1504366773158;\n\tSat, 02 Sep 2017 08:39:33 -0700 (PDT)", "From": "Bin Meng <bmeng.cn@gmail.com>", "To": "Tom Rini <trini@konsulko.com>, U-Boot Mailing List <u-boot@lists.denx.de>", "Date": "Sat, 2 Sep 2017 08:43:54 -0700", "Message-Id": "<1504367034-1000-3-git-send-email-bmeng.cn@gmail.com>", "X-Mailer": "git-send-email 1.7.9.5", "In-Reply-To": "<1504367034-1000-1-git-send-email-bmeng.cn@gmail.com>", "References": "<1504367034-1000-1-git-send-email-bmeng.cn@gmail.com>", "Subject": "[U-Boot] [PATCH 3/3] block: Drop the ftide020 driver", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "This is not used in U-Boot.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\n---\n\n drivers/block/Makefile | 1 -\n drivers/block/ftide020.c | 347 -------------------------------------------\n drivers/block/ftide020.h | 266 ---------------------------------\n scripts/config_whitelist.txt | 3 -\n 4 files changed, 617 deletions(-)\n delete mode 100644 drivers/block/ftide020.c\n delete mode 100644 drivers/block/ftide020.h", "diff": "diff --git a/drivers/block/Makefile b/drivers/block/Makefile\nindex dea2c15..d06a598 100644\n--- a/drivers/block/Makefile\n+++ b/drivers/block/Makefile\n@@ -12,7 +12,6 @@ obj-y += blk_legacy.o\n endif\n \n obj-$(CONFIG_IDE) += ide.o\n-obj-$(CONFIG_IDE_FTIDE020) += ftide020.o\n obj-$(CONFIG_SANDBOX) += sandbox.o\n obj-$(CONFIG_SYSTEMACE) += systemace.o\n obj-$(CONFIG_BLOCK_CACHE) += blkcache.o\ndiff --git a/drivers/block/ftide020.c b/drivers/block/ftide020.c\ndeleted file mode 100644\nindex 1f6995e..0000000\n--- a/drivers/block/ftide020.c\n+++ /dev/null\n@@ -1,347 +0,0 @@\n-/*\n- * Faraday FTIDE020 ATA Controller (AHB)\n- *\n- * (C) Copyright 2011 Andes Technology\n- * Greentime Hu <greentime@andestech.com>\n- * Macpaul Lin <macpaul@andestech.com>\n- * Kuo-Wei Chou <kwchou@andestech.com>\n- *\n- * SPDX-License-Identifier:\tGPL-2.0+\n- */\n-/* ftide020.c - ide support functions for the FTIDE020_S controller */\n-\n-#include <config.h>\n-#include <common.h>\n-#include <ata.h>\n-#include <ide.h>\n-#include <asm/io.h>\n-#include <api_public.h>\n-\n-#include \"ftide020.h\"\n-\n-/* base address */\n-#define FTIDE_BASE\tCONFIG_SYS_ATA_BASE_ADDR\n-\n-/*\n- * data address - The CMD and DATA use the same FIFO in FTIDE020_S\n- * FTIDE_DATA = CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_DATA_OFFSET\n- *\t\t= &ftide020->rw_fifo\n- */\n-#define FTIDE_DATA\t(&ftide020->rw_fifo)\n-\n-/* command and data I/O macros */\n-/* 0x0 - DATA FIFO */\n-#define WRITE_DATA(x)\toutl((x), &ftide020->rw_fifo)\t/* 0x00 */\n-#define READ_DATA()\tinl(&ftide020->rw_fifo)\t\t/* 0x00 */\n-/* 0x04 - R: Status Reg, W: CMD_FIFO */\n-#define WRITE_CMD(x)\toutl((x), &ftide020->cmd_fifo)\t/* 0x04 */\n-#define READ_STATUS()\tinl(&ftide020->cmd_fifo)\t/* 0x04 */\n-\n-void ftide_set_device(int cx8, int dev)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\n-\tWRITE_CMD(SET_DEV_CMD | IDE_SET_CX8(cx8) | dev);\n-}\n-\n-unsigned char ide_read_register(int dev, unsigned int port)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\n-\tftide_set_device(0, dev);\n-\tWRITE_CMD(READ_REG_CMD | IDE_REG_CS_READ(CONFIG_IDE_REG_CS) |\n-\t\tIDE_REG_DA_WRITE(port));\n-\n-\treturn READ_DATA() & 0xff;\n-}\n-\n-void ide_write_register(int dev, unsigned int port, unsigned char val)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\n-\tftide_set_device(0, dev);\n-\tWRITE_CMD(WRITE_REG_CMD | IDE_REG_CS_WRITE(CONFIG_IDE_REG_CS) |\n-\t\tIDE_REG_DA_WRITE(port) | val);\n-}\n-\n-void ide_write_data(int dev, const ulong *sect_buf, int words)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\n-\tftide_set_device(0, dev);\n-\tWRITE_CMD(WRITE_DATA_CMD | ((words << 2) - 1));\n-\n-\t/* block write */\n-\toutsl(FTIDE_DATA, sect_buf, words);\n-}\n-\n-void ide_read_data(int dev, ulong *sect_buf, int words)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\n-\tftide_set_device(0, dev);\n-\tWRITE_CMD(READ_DATA_CMD | ((words << 2) - 1));\n-\n-\t/* block read */\n-\tinsl(FTIDE_DATA, sect_buf, words);\n-}\n-\n-void ftide_dfifo_ready(ulong *time)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\n-\twhile (!(READ_STATUS() & STATUS_RFE)) {\n-\t\tif (*time-- == 0)\n-\t\t\tbreak;\n-\n-\t\tudelay(100);\n-\t}\n-}\n-\n-extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];\n-\n-/* Reset_IDE_controller */\n-static void reset_ide_controller(void)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\tunsigned int val;\n-\n-\tval = inl(&ftide020->cr);\n-\n-\tval |= CONTROL_RST;\n-\toutl(val, &ftide020->cr);\n-\n-\t/* wait until reset OK, this is poor HW design */\n-\tmdelay(50);\n-\tval &= ~(CONTROL_RST);\n-\toutl(val, &ftide020->cr);\n-\n-\tmdelay(50);\n-\tval |= CONTROL_SRST;\n-\toutl(val, &ftide020->cr);\n-\n-\t/* wait until reset OK, this is poor HW design */\n-\tmdelay(50);\n-\tval &= ~(CONTROL_SRST);\n-\toutl(val, &ftide020->cr);\n-\n-\t/* IORDY enable for PIO, for 2 device */\n-\tval |= (CONTROL_IRE0 | CONTROL_IRE1);\n-\toutl(val, &ftide020->cr);\n-}\n-\n-/* IDE clock frequence */\n-uint ftide_clock_freq(void)\n-{\n-\t/*\n-\t * todo: To aquire dynamic system frequency is dependend on the power\n-\t * management unit which the ftide020 is connected to. In current,\n-\t * there are only few PMU supports in u-boot.\n-\t * So this function is wait for future enhancement.\n-\t */\n-\treturn 100;\n-}\n-\n-/* Calculate Timing Registers */\n-static unsigned int timing_cal(u16 t0, u16 t1, u16 t2, u16 t4)\n-{\n-\tunsigned int val, ahb_ns = 8;\n-\tu8 TEOC, T1, T2, T4;\n-\n-\tT1 = (u8) (t1 / ahb_ns);\n-\tif ((T1 * ahb_ns) == t1)\n-\t\tT1--;\n-\n-\tT2 = (u8) (t2 / ahb_ns);\n-\tif ((T2 * ahb_ns) == t2)\n-\t\tT2--;\n-\n-\tT4 = (u8) (t4 / ahb_ns);\n-\tif ((T4 * ahb_ns) == t4)\n-\t\tT4--;\n-\n-\tTEOC = (u8) (t0 / ahb_ns);\n-\tif ((TEOC * ahb_ns) == t0)\n-\t\tTEOC--;\n-\n-\tTEOC = ((TEOC > (T1 + T2 + T4)) ? (TEOC - (T1 + T2 + T4)) : 0);\n-\n-\t/*\n-\t * Here the fields in data timing registers in PIO mode\n-\t * is accessed the same way as command timing registers.\n-\t */\n-\tval =\tDT_REG_PIO_T1(T1)\t|\n-\t\tDT_REG_PIO_T2(T2)\t|\n-\t\tDT_REG_PIO_T4(T4)\t|\n-\t\tDT_REG_PIO_TEOC(TEOC);\n-\n-\treturn val;\n-}\n-\n-/* Set Timing Register */\n-static unsigned int set_mode_timing(u8 dev, u8 id, u8 mode)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\tu16 t0, t1, t2, t4;\n-\tu8 tcyc, tcvs, tmli, tenv, tack, trp;\n-\tunsigned int val, sysclk = 8;\n-\n-\tif (id >= TATOL_TIMING)\n-\t\treturn 0;\n-\n-\tsysclk = ftide_clock_freq();\n-\tswitch (id) {\n-\tcase CMD_TIMING:\n-\t\tif (mode < REG_MODE) {\n-\t\t\tt0 = REG_ACCESS_TIMING[REG_T0][mode];\n-\t\t\tt1 = REG_ACCESS_TIMING[REG_T1][mode];\n-\t\t\tt2 = REG_ACCESS_TIMING[REG_T2][mode];\n-\t\t\tt4 = REG_ACCESS_TIMING[REG_T4][mode];\n-\n-\t\t\tval = timing_cal(t0, t1, t2, t4);\n-\t\t\toutl(val, (dev ? &ftide020->ctrd1 : &ftide020->ctrd0));\n-\t\t\treturn 1;\n-\t\t} else\n-\t\t\treturn 0;\n-\tcase PIO_TIMING:\n-\t\tif (mode < PIO_MODE) {\n-\t\t\tt0 = PIO_ACCESS_TIMING[PIO_T0][mode];\n-\t\t\tt1 = PIO_ACCESS_TIMING[PIO_T1][mode];\n-\t\t\tt2 = PIO_ACCESS_TIMING[PIO_T2][mode];\n-\t\t\tt4 = PIO_ACCESS_TIMING[PIO_T4][mode];\n-\n-\t\t\tval = timing_cal(t0, t1, t2, t4);\n-\n-\t\t\toutl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0));\n-\t\t\treturn 1;\n-\t\t} else\n-\t\t\treturn 0;\n-\tcase DMA_TIMING:\n-\t\tif (mode < UDMA_MODE) {\n-\t\t\t/*\n-\t\t\t * 0.999 is ceiling\n-\t\t\t * for tcyc, tcvs, tmli, tenv, trp, tack\n-\t\t\t */\n-\t\t\ttcyc = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCYC][mode] \\\n-\t\t\t\t\t\t* sysclk) + 9990) / 10000);\n-\t\t\ttcvs = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCVS][mode] \\\n-\t\t\t\t\t\t* sysclk) + 9990) / 10000);\n-\t\t\ttmli = (u8) (((UDMA_ACCESS_TIMING[UDMA_TMLI][mode] \\\n-\t\t\t\t\t\t* sysclk) + 9990) / 10000);\n-\t\t\ttenv = (u8) (((UDMA_ACCESS_TIMING[UDMA_TENV][mode] \\\n-\t\t\t\t\t\t* sysclk) + 9990) / 10000);\n-\t\t\ttrp = (u8) (((UDMA_ACCESS_TIMING[UDMA_TRP][mode] \\\n-\t\t\t\t\t\t* sysclk) + 9990) / 10000);\n-\t\t\ttack = (u8) (((UDMA_ACCESS_TIMING[UDMA_TACK][mode] \\\n-\t\t\t\t\t\t * sysclk) + 9990) / 10000);\n-\n-\t\t\tval =\tDT_REG_UDMA_TENV((tenv > 0) ? (tenv - 1) : 0) |\n-\t\t\t\tDT_REG_UDMA_TMLI((tmli > 0) ? (tmli - 1) : 0) |\n-\t\t\t\tDT_REG_UDMA_TCYC((tcyc > 0) ? (tcyc - 1) : 0) |\n-\t\t\t\tDT_REG_UDMA_TACK((tack > 0) ? (tack - 1) : 0) |\n-\t\t\t\tDT_REG_UDMA_TCVS((tcvs > 0) ? (tcvs - 1) : 0) |\n-\t\t\t\tDT_REG_UDMA_TRP((trp > 0) ? (trp - 1) : 0);\n-\n-\t\t\toutl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0));\n-\t\t\treturn 1;\n-\t\t} else\n-\t\t\treturn 0;\n-\tdefault:\n-\t\treturn 0;\n-\t}\n-}\n-\n-static void ftide_read_hwrev(void)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\tunsigned int rev;\n-\n-\trev = inl(&ftide020->revision);\n-}\n-\n-static int ftide_controller_probe(void)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\tunsigned int bak;\n-\n-\tbak = inl(&ftide020->ctrd1);\n-\n-\t/* probing by using shorter setup time */\n-\toutl(CONFIG_CTRD1_PROBE_T1, &ftide020->ctrd1);\n-\tif ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T1) {\n-\t\toutl(bak, &ftide020->ctrd1);\n-\t\treturn 0;\n-\t}\n-\n-\t/* probing by using longer setup time */\n-\toutl(CONFIG_CTRD1_PROBE_T2, &ftide020->ctrd1);\n-\tif ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T2) {\n-\t\toutl(bak, &ftide020->ctrd1);\n-\t\treturn 0;\n-\t}\n-\n-\toutl(bak, &ftide020->ctrd1);\n-\n-\treturn 1;\n-}\n-\n-/* ide_preinit() was migrated from linux driver ide_probe_for_ftide() */\n-int ide_preinit(void)\n-{\n-\tstatic struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;\n-\tint status;\n-\tunsigned int val;\n-\tint i;\n-\n-\tstatus = 1;\n-\tfor (i = 0; i < CONFIG_SYS_IDE_MAXBUS; i++)\n-\t\tide_bus_offset[i] = -ATA_STATUS;\n-\n-\t/* auto-detect IDE controller */\n-\tif (ftide_controller_probe()) {\n-\t\tprintf(\"FTIDE020_S\\n\");\n-\t} else {\n-\t\tprintf(\"FTIDE020_S ATA controller not found.\\n\");\n-\t\treturn API_ENODEV;\n-\t}\n-\n-\t/* check HW IP revision */\n-\tftide_read_hwrev();\n-\n-\t/* set FIFO threshold */\n-\toutl(((WRITE_FIFO - RX_THRESH) << 16) | RX_THRESH, &ftide020->dmatirr);\n-\n-\t/* set Device_0 PIO_4 timing */\n-\tset_mode_timing(0, CMD_TIMING, REG_MODE4);\n-\tset_mode_timing(0, PIO_TIMING, PIO_MODE4);\n-\n-\t/* set Device_1 PIO_4 timing */\n-\tset_mode_timing(1, CMD_TIMING, REG_MODE4);\n-\tset_mode_timing(1, PIO_TIMING, PIO_MODE4);\n-\n-\t/* from E-bios */\n-\t/* little endian */\n-\toutl(0x0, &ftide020->cr);\n-\tmdelay(10);\n-\n-\toutl(0x0fff0fff, &ftide020->ahbtr);\n-\tmdelay(10);\n-\n-\t/* Enable controller Interrupt */\n-\tval = inl(&ftide020->cr);\n-\n-\t/* Enable: IDE IRQ, IDE Terminate ERROR IRQ, AHB Timeout error IRQ */\n-\tval |= (CONTROL_IIE | CONTROL_TERIE | CONTROL_AERIE);\n-\toutl(val, &ftide020->cr);\n-\n-\tstatus = 0;\n-\n-\treturn status;\n-}\n-\n-void ide_set_reset(int flag)\n-{\n-\tdebug(\"ide_set_reset()\\n\");\n-\treset_ide_controller();\n-\treturn;\n-}\ndiff --git a/drivers/block/ftide020.h b/drivers/block/ftide020.h\ndeleted file mode 100644\nindex 2d88c7c..0000000\n--- a/drivers/block/ftide020.h\n+++ /dev/null\n@@ -1,266 +0,0 @@\n-/*\n- * Faraday FTIDE020_s ATA Controller (AHB)\n- *\n- * (C) Copyright 2011 Andes Technology\n- * Greentime Hu <greentime@andestech.com>\n- * Macpaul Lin <macpaul@andestech.com>\n- * Kuo-Wei Chou <kwchou@andestech.com>\n- *\n- * SPDX-License-Identifier:\tGPL-2.0+\n- */\n-\n-#ifndef __FTIDE020_H\n-#define __FTIDE020_H\n-\n-/* ftide020.h - ide support functions for the FTIDE020_S controller */\n-\n-/* ATA controller register offset */\n-struct ftide020_s {\n-\tunsigned int\trw_fifo;\t/* 0x00 - READ/WRITE FIFO\t*/\n-\tunsigned int\tcmd_fifo;\t/* 0x04 - R: Status Reg, W: CMD_FIFO */\n-\tunsigned int\tcr;\t\t/* 0x08 - Control Reg\t\t*/\n-\tunsigned int\tdmatirr;\t/* 0x0c - DMA Threshold/Interrupt Reg */\n-\tunsigned int\tctrd0;\t\t/* 0x10 - Command Timing Reg Device 0 */\n-\tunsigned int\tdtrd0;\t\t/* 0x14 - Data Timing Reg Device 0 */\n-\tunsigned int\tctrd1;\t\t/* 0x18 - Command Timing Reg Device 1 */\n-\tunsigned int\tdtrd1;\t\t/* 0x1c - Data Timing Reg Device 1 */\n-\tunsigned int\tahbtr;\t\t/* 0x20 - AHB Timeout Reg\t*/\n-\tunsigned int\tRESVD0;\t\t/* 0x24 */\n-\tunsigned int\tRESVD1;\t\t/* 0x28 */\n-\tunsigned int\tRESVD2;\t\t/* 0x2c */\n-\tunsigned int\tf_cfifo;\t/* 0x30 - Feature Info of CMD_FIFO */\n-\tunsigned int\tf_wfifo;\t/* 0x34 - Feature Info of WRITE_FIFO */\n-\tunsigned int\tf_rfifo;\t/* 0x3c - Feature Info of READ_FIFO */\n-\tunsigned int\trevision;\t/* 0x38 - Revision No. of FTIDE020_S */\n-};\n-\n-/* reference parameters */\n-#define CONFIG_IDE_REG_CS\t0x2\t/* ref: ATA spec chaper 10, table 42 */\n-#define CONFIG_CTRD1_PROBE_T1\t0x2\n-#define CONFIG_CTRD1_PROBE_T2\t0x5\n-\n-/* status register - 0x04 */\n-#define STATUS_CSEL\t\t(1 << 0)\t/* CSEL\t\t\t*/\n-#define STATUS_CS(x)\t\t(((x) >> 1) & 0x3)\t/* CS#[1:0]\t*/\n-#define STATUS_DMACK\t\t(1 << 3)\t/* DMACK#\t\t*/\n-#define STATUS_DMARQ\t\t(1 << 4)\t/* DMA req\t\t*/\n-#define STATUS_INTRQ\t\t(1 << 5)\t/* INT req\t\t*/\n-#define STATUS_DIOR\t\t(1 << 6)\t/* DIOR\t\t\t*/\n-#define STATUS_IORDY\t\t(1 << 7)\t/* I/O ready\t\t*/\n-#define STATUS_DIOW\t\t(1 << 8)\t/* DIOW#\t\t*/\n-#define STATUS_PDIAG\t\t(1 << 9)\t/* PDIAG\t\t*/\n-#define STATUS_DASP\t\t(1 << 10)\t/* DASP#\t\t*/\n-#define STATUS_DEV\t\t(1 << 11)\t/* selected device\t*/\n-#define STATUS_PIO\t\t(1 << 12)\t/* PIO in progress\t*/\n-#define STATUS_DMA\t\t(1 << 13)\t/* DMA in progress\t*/\n-#define STATUS_WFE\t\t(1 << 14)\t/* write fifo full\t*/\n-#define STATUS_RFE\t\t(1 << 15)\t/* read fifo empty\t*/\n-#define STATUS_COUNTER(x)\t(((x) >> 16) & 0x3fff)\t/* data tx counter */\n-#define STATUS_ERR\t\t(1 << 30)\t/* trasfer terminated\t*/\n-#define STATUS_AER\t\t(1 << 31)\t/* AHB timeout indicate\t*/\n-\n-/* Control register - 0x08 */\n-#define CONTROL_TYPE_PIO\t0x0\n-#define CONTROL_TYPE_UDMA\t0x1\n-\n-/* Device 0 */\n-#define CONTROL_TYP0(x)\t\t(((x) & 0x7) << 0)\n-#define CONTROL_IRE0\t\t(1 << 3) /* enable IORDY for PIO */\n-#define CONTROL_RESVD_DW0\t(1 << 4) /* Reserved - DW0 ?\t*/\n-#define CONTROL_E0\t\t(1 << 5) /* E0: 1: Big Endian\t*/\n-#define CONTROL_RESVD_WP0\t(1 << 6) /* Reserved - WP0 ?\t*/\n-#define CONTROL_RESVD_SE0\t(1 << 7) /* Reserved - SE0 ?\t*/\n-#define CONTROL_RESVD_ECC0\t(1 << 8) /* Reserved - ECC0 ?\t*/\n-\n-#define CONTROL_RAEIE\t\t(1 << 9) /* IRQ - read fifo almost full */\n-#define CONTROL_RNEIE\t\t(1 << 10) /* IRQ - read fifo not empty\t*/\n-#define CONTROL_WAFIE\t\t(1 << 11) /* IRQ - write fifo almost empty */\n-#define CONTROL_WNFIE\t\t(1 << 12) /* IRQ - write fifo not full\t*/\n-#define CONTROL_RESVD_FIRQ\t(1 << 13) /* RESERVED - FIRQ ?\t\t*/\n-#define CONTROL_AERIE\t\t(1 << 14) /* IRQ - AHB timeout error\t*/\n-#define CONTROL_IIE\t\t(1 << 15) /* IDE IRQ enable\t\t*/\n-\n-/* Device 1 */\n-#define CONTROL_TYP1(x)\t\t(((x) & 0x7) << 16)\n-#define CONTROL_IRE1\t\t(1 << 19)\t/* enable IORDY for PIO */\n-#define CONTROL_RESVD_DW1\t(1 << 20)\t/* Reserved - DW1 ?\t*/\n-#define CONTROL_E1\t\t(1 << 21)\t/* E1: 1: Big Endian\t*/\n-#define CONTROL_RESVD_WP1\t(1 << 22)\t/* Reserved - WP1 ?\t*/\n-#define CONTROL_RESVD_SE1\t(1 << 23)\t/* Reserved - SE1 ?\t*/\n-#define CONTROL_RESVD_ECC1\t(1 << 24)\t/* Reserved - ECC1 ?\t*/\n-\n-#define CONTROL_DRE\t(1 << 25)\t/* DMA receive enable\t\t*/\n-#define CONTROL_DTE\t(1 << 26)\t/* DMA transmit enable\t\t*/\n-#define CONTRIL_RESVD\t(1 << 27)\n-#define CONTROL_TERIE\t(1 << 28)\t/* transfer terminate error IRQ\t*/\n-#define CONTROL_T\t(1 << 29)\t/* terminate current operation\t*/\n-#define CONTROL_SRST\t(1 << 30)\t/* IDE soft reset\t\t*/\n-#define CONTROL_RST\t(1 << 31)\t/* IDE hardware reset\t\t*/\n-\n-/* IRQ register - 0x0c */\n-#define IRQ_RXTHRESH(x)\t(((x) & 0x3ff) << 0)\t/* Read FIFO threshold\t*/\n-#define IRQ_RFAEIRQ\t(1 << 10)\t/* Read FIFO almost full intr req */\n-#define IRQ_RFNEIRQ\t(1 << 11)\t/* Read FIFO not empty intr req\t*/\n-#define IRQ_WFAFIRQ\t(1 << 12)\t/* Write FIFO almost empty int req */\n-#define IRQ_WFNFIRQ\t(1 << 13)\t/* Write FIFO not full intr req\t*/\n-#define IRQ_RESVD_FIRQ\t(1 << 14)\t/* Reserved - FIRQ ?\t\t*/\n-#define IRQ_IIRQ\t(1 << 15)\t/* IDE device interrupt request\t*/\n-#define IRQ_TXTHRESH(x)\t(((x) & 0x3ff) << 16)\t/* Write FIFO thershold\t*/\n-#define IRQ_TERMERR\t(1 << 28)\t/* Transfer termination indication */\n-#define IRQ_AHBERR\t(1 << 29)\t/* AHB Timeout indication\t*/\n-\n-/* Command Timing Register 0-1: ctrd (0x10, 0x18) */\n-#define CT_REG_T1(x)\t(((x) & 0xff) << 0)\t/* setup time of addressed */\n-#define CT_REG_T2(x)\t(((x) & 0xff) << 8)\t/* pluse width of DIOR/DIOW */\n-#define CT_REG_T4(x)\t(((x) & 0xff) << 16)\t/* data hold time */\n-#define CT_REG_TEOC(x)\t(((x) & 0xff) << 24)\t/* time to the end of a cycle */\n-\n-/* Data Timing Register 0-1: dtrd (0x14, 0x1c) */\n-/*\n- * PIO mode:\n- *\tb(0:7)\t\tDT_REG_PIO_T1: the setup time of addressed\n- *\tb(8:15)\t\tDT_REG_PIO_T2: the pluse width of DIOR/DIOW\n- *\tb(16:23)\tDT_REG_PIO_T4: data hold time\n- *\tb(24:31)\tDT_REG_PIO_TEOC: the time to the end of a cycle\n- */\n-#define DT_REG_PIO_T1(x)\t(((x) & 0xff) << 0)\n-#define DT_REG_PIO_T2(x)\t(((x) & 0xff) << 8)\n-#define DT_REG_PIO_T4(x)\t(((x) & 0xff) << 16)\n-#define DT_REG_PIO_TEOC(x)\t(((x) & 0xff) << 24)\n-\n-/*\n- * UDMA mode:\n- *\tb(0:3)\t\tDT_REG_UDMA_TENV: the envelope time\n- *\tb(4:7)\t\tDT_REG_UDMA_TMLI: interlock time\n- *\tb(8:15)\t\tDT_REG_UDMA_TCYC: cycle time - data time\n- *\tb(16:19)\tDT_REG_UDMA_TACK: setup and hold time of DMACK\n- *\tb(23:30)\tDT_REG_UDMA_TCVS: setup time of CRC\n- *\tb(24:31)\tDT_REG_UDMA_TRP: time to ready to pause\n- */\n-#define DT_REG_UDMA_TENV(x)\t(((x) & 0xf) << 0)\n-#define DT_REG_UDMA_TMLI(x)\t(((x) & 0xf) << 4)\n-#define DT_REG_UDMA_TCYC(x)\t(((x) & 0xff) << 8)\n-#define DT_REG_UDMA_TACK(x)\t(((x) & 0xf) << 16)\n-#define DT_REG_UDMA_TCVS(x)\t(((x) & 0xf) << 20)\n-#define DT_REG_UDMA_TRP(x)\t(((x) & 0xff) << 24)\n-\n-/* ftide020_s command formats */\n-/* read: IDE Register (CF1) */\n-#define IDE_REG_OPCODE_READ\t(1 << 13)\t\t/* 0x2000 */\n-#define IDE_REG_CS_READ(x)\t(((x) & 0x3) << 11)\n-#define IDE_REG_DA_READ(x)\t(((x) & 0x7) << 8)\n-#define IDE_REG_CMD_READ(x)\t0x0\t\t\t/* fixed value */\n-\n-/* write: IDE Register (CF2) */\n-#define IDE_REG_OPCODE_WRITE\t(0x5 << 13)\t\t/* 0xA000 */\n-#define IDE_REG_CS_WRITE(x)\t(((x) & 0x3) << 11)\n-#define IDE_REG_DA_WRITE(x)\t(((x) & 0x7) << 8)\n-/* b(0:7) IDE_REG_CMD_WRITE(x):\tActual ATA command or data */\n-#define IDE_REG_CMD_WRITE(x)\t(((x) & 0xff) << 0)\n-\n-/* read/write data: PIO/UDMA (CF3) */\n-#define IDE_DATA_WRITE\t\t(1 << 15)\t\t/* read: 0, write: 1 */\n-#define IDE_DATA_OPCODE\t\t(0x2 << 13)\t/* device data access opcode */\n-/* b(0:12) IDE_DATA_COUNTER(x): Number of transfers minus 1 */\n-#define IDE_DATA_COUNTER(x)\t(((x) & 0x1fff) << 0)\n-\n-/* set device: (CF4) */\n-#define IDE_SET_OPCODE\t(0x2740 << 2)\t\t\t/* [15:2], 0x9d00 */\n-/* CF3 counter value: 0: Tx in bytes, 1: in blocks (each block is 8 bytes) */\n-#define IDE_SET_CX8(x)\t(((x) & 0x1) << 1)\n-#define IDE_SET_DEV(x)\t(((x) & 0x1) << 0)\t/* 0: Master, 1: Slave */\n-\n-/*\n- * IDE command bit definition\n- * This section is designed for minor hardware revision compatibility.\n- */\n-#define READ_REG_CMD\tIDE_REG_OPCODE_READ\t\t\t/* 0x2000 */\n-#define WRITE_REG_CMD\tIDE_REG_OPCODE_WRITE\t\t\t/* 0xA000 */\n-#define READ_DATA_CMD\tIDE_DATA_OPCODE\t\t\t\t/* 0x4000 */\n-#define WRITE_DATA_CMD\t(IDE_DATA_OPCODE | IDE_DATA_WRITE)\t/* 0xC000 */\n-#define SET_DEV_CMD\tIDE_SET_OPCODE\t\t\t\t/* 0x9D00 */\n-\n-#define TATOL_TIMING\t\t3\n-#define CMD_TIMING\t\t0\n-#define PIO_TIMING\t\t1\n-#define DMA_TIMING\t\t2\n-\n-/* Timing Parameters */\n-/* Register Access Timing Parameters */\n-#define REG_PARAMETER\t\t4\n-#define REG_T0\t\t\t0\n-#define REG_T1\t\t\t1\n-#define REG_T2\t\t\t2\n-#define REG_T4\t\t\t3\n-\n-#define REG_MODE\t\t5\n-#define REG_MODE0\t\t0\n-#define REG_MODE1\t\t1\n-#define REG_MODE2\t\t2\n-#define REG_MODE3\t\t3\n-#define REG_MODE4\t\t4\n-\n-/* PIO Access Timing Parameters */\n-#define PIO_PARAMETER\t\t4\n-#define PIO_T0\t\t\t0\n-#define PIO_T1\t\t\t1\n-#define PIO_T2\t\t\t2\n-#define PIO_T4\t\t\t3\n-\n-#define PIO_MODE\t\t5\n-#define PIO_MODE0\t\t0\n-#define PIO_MODE1\t\t1\n-#define PIO_MODE2\t\t2\n-#define PIO_MODE3\t\t3\n-#define PIO_MODE4\t\t4\n-\n-/* UDMA Access Timing Parameters */\n-#define UDMA_PARAMETER\t\t6\n-#define UDMA_TCYC\t\t0\n-#define UDMA_TCVS\t\t1\n-#define UDMA_TMLI\t\t2\n-#define UDMA_TENV\t\t3\n-#define UDMA_TRP\t\t4\n-#define UDMA_TACK\t\t5\n-\n-#define UDMA_MODE\t\t7\n-#define UDMA_MODE0\t\t0\n-#define UDMA_MODE1\t\t1\n-#define UDMA_MODE2\t\t2\n-#define UDMA_MODE3\t\t3\n-#define UDMA_MODE4\t\t4\n-#define UDMA_MODE5\t\t5\n-#define UDMA_MODE6\t\t6\n-\n-/*\n- * RX_THRESH:\n- * hardware limitation: max = 8, should support 1,4,8,16,32,64,128,256\n- */\n-#define RX_THRESH\t\t8\n-#define WRITE_FIFO\t\t32\t/* Hardwired value */\n-\n-/* Time Table */\n-unsigned int REG_ACCESS_TIMING[REG_PARAMETER][REG_MODE] = {\n-\t{600,\t383,\t330,\t180,\t120},\n-\t{70,\t50,\t30,\t30,\t25},\n-\t{290,\t290,\t290,\t80,\t70},\n-\t{30,\t20,\t15,\t10,\t10},\n-};\n-\n-unsigned int PIO_ACCESS_TIMING[PIO_PARAMETER][PIO_MODE] = {\n-\t{600,\t383,\t240,\t180,\t120},\n-\t{70,\t50,\t30,\t30,\t25},\n-\t{165,\t125,\t100,\t80,\t70},\n-\t{30,\t20,\t15,\t10,\t10},\n-};\n-\n-unsigned int UDMA_ACCESS_TIMING[UDMA_PARAMETER][UDMA_MODE] = {\n-\t{1120,\t730,\t540,\t390,\t250,\t168,\t130}, /* 10X */\n-\t{700,\t480,\t310,\t200,\t67,\t100,\t100}, /* 10X */\n-\t{200,\t200,\t200,\t200,\t200,\t200,\t200}, /* 10X */\n-\t{200,\t200,\t200,\t200,\t200,\t200,\t200}, /* 10X */\n-\t{1600,\t1250,\t1000,\t1000,\t1000,\t850,\t850}, /* 10X */\n-\t{200,\t200,\t200,\t200,\t200,\t200,\t200}, /* 10X */\n-};\n-\n-#endif /* __FTIDE020_H */\ndiff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt\nindex 2aa23dc..fb2224e 100644\n--- a/scripts/config_whitelist.txt\n+++ b/scripts/config_whitelist.txt\n@@ -377,8 +377,6 @@ CONFIG_CS8900_BUS32\n CONFIG_CSF_SIZE\n CONFIG_CTL_JTAG\n CONFIG_CTL_TBE\n-CONFIG_CTRD1_PROBE_T1\n-CONFIG_CTRD1_PROBE_T2\n CONFIG_CUSTOMER_BOARD_SUPPORT\n CONFIG_CYRUS\n CONFIG_D2NET_V2\n@@ -1082,7 +1080,6 @@ CONFIG_ICACHE\n CONFIG_ICS307_REFCLK_HZ\n CONFIG_IDE_PCMCIA\n CONFIG_IDE_PREINIT\n-CONFIG_IDE_REG_CS\n CONFIG_IDE_RESET\n CONFIG_IDE_SWAP_IO\n CONFIG_IDS8313\n", "prefixes": [ "U-Boot", "3/3" ] }