Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 808968,
    "url": "http://patchwork.ozlabs.org/api/patches/808968/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170901185736.28051-5-thierry.reding@gmail.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170901185736.28051-5-thierry.reding@gmail.com>",
    "list_archive_url": null,
    "date": "2017-09-01T18:57:24",
    "name": "[04/16] gpio: Move irq_base to struct gpio_irq_chip",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "8895e5fd79139ab4cd46bc68043a888d4874e48a",
    "submitter": {
        "id": 26234,
        "url": "http://patchwork.ozlabs.org/api/people/26234/?format=api",
        "name": "Thierry Reding",
        "email": "thierry.reding@gmail.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170901185736.28051-5-thierry.reding@gmail.com/mbox/",
    "series": [
        {
            "id": 1098,
            "url": "http://patchwork.ozlabs.org/api/series/1098/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=1098",
            "date": "2017-09-01T18:57:20",
            "name": "gpio: Tight IRQ chip integration and banked infrastructure",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/1098/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/808968/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/808968/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-gpio-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": [
            "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
            "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"PKXkEI80\"; dkim-atps=neutral"
        ],
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkT980T8Yz9t16\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat,  2 Sep 2017 05:00:57 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752481AbdIAS5v (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 1 Sep 2017 14:57:51 -0400",
            "from mail-wm0-f65.google.com ([74.125.82.65]:35951 \"EHLO\n\tmail-wm0-f65.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752437AbdIAS5s (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Fri, 1 Sep 2017 14:57:48 -0400",
            "by mail-wm0-f65.google.com with SMTP id p17so957300wmd.3;\n\tFri, 01 Sep 2017 11:57:47 -0700 (PDT)",
            "from localhost\n\t(p200300E41BD6D60076D02BFFFE273F51.dip0.t-ipconnect.de.\n\t[2003:e4:1bd6:d600:76d0:2bff:fe27:3f51])\n\tby smtp.gmail.com with ESMTPSA id\n\t66sm386419wmn.17.2017.09.01.11.57.43\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tFri, 01 Sep 2017 11:57:44 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=h56Jd1dDpBcvBeA7zpFoAUMTBV/z2MRsxs1xX0Cxu8A=;\n\tb=PKXkEI80M/erJyoX2glO1hQ4Hc9F4qBZL2hN5LZ546wfefX80cSFGRvUYdQS49OByr\n\t7jc65WKbmBmM6drBKVbj2jVD+wvYNm34j5wKSMWO4mEDD/eL1NlhW+Q9QkrKZ0ZPT1UD\n\tuS4XN9BPOngFcJVTWiZb16viFwfCZDGgHkpVcfhIbL3T13GOQaaX2u0EfFrAABjZWUsn\n\tgpbgEowYvcRfuNh8mQNrgHVSUJefvZF6pNybe8Ao4EQ4SnCe4uONX3yvM8VxVcFV/4UB\n\tOb1FbnZG1lbjNCTPr7SRiYBFc/fI0Mi56bWAqAi+HTWBZcZC600gIkhFEWewxCIEVx94\n\t6MRw==",
        "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=h56Jd1dDpBcvBeA7zpFoAUMTBV/z2MRsxs1xX0Cxu8A=;\n\tb=lO9d+mcNhLhlBurHtfBi4l+1VqmRmfRHvJayLkTnPVLiDNGsWG+pJDTVUqfInZCE6a\n\t2dARkmE6UY4hpBQnsspHv6QZ1GPA0af5l5UxpjPWOO4ZXO7UxDrEkhZjg69Vkiyue2Ai\n\tx841lPReZM7uSnK0ABZMjkO/ploGQ7NYnqcr4oKX1nKDrVdtWGmiwQFBNNPtS8LHiw4E\n\tEg4sR0Q5xC2sZkQZU6OpdGk5VKCug2xDxDIIKuS5rjnZ1/h7FuHtgnRKkFDLHAqIE4IC\n\t/iut7k8WDyw/Q/gHeCAsOhZNyW+csApJwj1qF4HqjzjH5RyjWpRqaiSWM+VpOCEbeOBK\n\t5R/g==",
        "X-Gm-Message-State": "AHPjjUg537lW1EOi2/RJU0DAS8dKwPAIbjQ4kBGW29cmScVv7xxZ/3/w\n\tO/QE5IDXb7hzcw==",
        "X-Google-Smtp-Source": "ADKCNb7KUruPwo9rDjI8MfvB7qxQq5nBS1kbjzO8UiyHwaHve3njlKsIv/HZPZp3EHRiDSGRQ2lu8w==",
        "X-Received": "by 10.28.136.140 with SMTP id k134mr1144885wmd.97.1504292265173; \n\tFri, 01 Sep 2017 11:57:45 -0700 (PDT)",
        "From": "Thierry Reding <thierry.reding@gmail.com>",
        "To": "Linus Walleij <linus.walleij@linaro.org>",
        "Cc": "Jonathan Hunter <jonathanh@nvidia.com>, linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org",
        "Subject": "[PATCH 04/16] gpio: Move irq_base to struct gpio_irq_chip",
        "Date": "Fri,  1 Sep 2017 20:57:24 +0200",
        "Message-Id": "<20170901185736.28051-5-thierry.reding@gmail.com>",
        "X-Mailer": "git-send-email 2.13.3",
        "In-Reply-To": "<20170901185736.28051-1-thierry.reding@gmail.com>",
        "References": "<20170901185736.28051-1-thierry.reding@gmail.com>",
        "Sender": "linux-gpio-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-gpio.vger.kernel.org>",
        "X-Mailing-List": "linux-gpio@vger.kernel.org"
    },
    "content": "From: Thierry Reding <treding@nvidia.com>\n\nIn order to consolidate the multiple ways to associate an IRQ chip with\na GPIO chip, move more fields into the new struct gpio_irq_chip.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\n drivers/gpio/gpiolib.c                      |  2 +-\n drivers/pinctrl/mvebu/pinctrl-armada-37xx.c |  2 +-\n include/linux/gpio/driver.h                 | 10 ++++++++--\n 3 files changed, 10 insertions(+), 4 deletions(-)",
    "diff": "diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\nindex d8ea8a292978..e5ad28978d5c 100644\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -1781,7 +1781,7 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip)\n \t\tops = &gpiochip_domain_ops;\n \n \tgpiochip->irq.domain = irq_domain_add_simple(np, gpiochip->ngpio,\n-\t\t\t\t\t\t     gpiochip->irq_base,\n+\t\t\t\t\t\t     gpiochip->irq.first,\n \t\t\t\t\t\t     ops, gpiochip);\n \tif (!gpiochip->irq.domain)\n \t\treturn -EINVAL;\ndiff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c\nindex e66ff18ee362..8df8a4998f48 100644\n--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c\n+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c\n@@ -681,7 +681,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev,\n \t * the chained irq with all of them.\n \t */\n \tfor (i = 0; i < nrirqs; i++) {\n-\t\tstruct irq_data *d = irq_get_irq_data(gc->irq_base + i);\n+\t\tstruct irq_data *d = irq_get_irq_data(gc->irq.first + i);\n \n \t\t/*\n \t\t * The mask field is a \"precomputed bitmask for\ndiff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h\nindex 031037bb8670..9389406df0b1 100644\n--- a/include/linux/gpio/driver.h\n+++ b/include/linux/gpio/driver.h\n@@ -47,6 +47,14 @@ struct gpio_irq_chip {\n \tconst struct irq_domain_ops *domain_ops;\n \n \t/**\n+\t * @first:\n+\t *\n+\t * If not dynamically assigned, the base (first) IRQ to allocate GPIO\n+\t * chip IRQs from (deprecated).\n+\t */\n+\tunsigned int first;\n+\n+\t/**\n \t * @parent_handler:\n \t *\n \t * The interrupt handler for the GPIO chip's parent interrupts, may be\n@@ -152,7 +160,6 @@ static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n  *\tsafely.\n  * @bgpio_dir: shadowed direction register for generic GPIO to clear/set\n  *\tdirection safely.\n- * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)\n  * @irq_handler: the irq handler to use (often a predefined irq core function)\n  *\tfor GPIO IRQs, provided by GPIO driver\n  * @irq_default_type: default IRQ triggering type applied during GPIO driver\n@@ -232,7 +239,6 @@ struct gpio_chip {\n \t * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib\n \t * to handle IRQs for most practical cases.\n \t */\n-\tunsigned int\t\tirq_base;\n \tirq_flow_handler_t\tirq_handler;\n \tunsigned int\t\tirq_default_type;\n \tunsigned int\t\tirq_chained_parent;\n",
    "prefixes": [
        "04/16"
    ]
}