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GET /api/patches/808963/?format=api
{ "id": 808963, "url": "http://patchwork.ozlabs.org/api/patches/808963/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20170901185736.28051-10-thierry.reding@gmail.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170901185736.28051-10-thierry.reding@gmail.com>", "list_archive_url": null, "date": "2017-09-01T18:57:29", "name": "[09/16] gpio: Move irq_valid_mask into struct gpio_irq_chip", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "9b6c0b19d3c0b7bf85db6ca831916ef3072a1227", "submitter": { "id": 26234, "url": "http://patchwork.ozlabs.org/api/people/26234/?format=api", "name": "Thierry Reding", "email": "thierry.reding@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20170901185736.28051-10-thierry.reding@gmail.com/mbox/", "series": [ { "id": 1099, "url": "http://patchwork.ozlabs.org/api/series/1099/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=1099", "date": "2017-09-01T18:57:20", "name": "gpio: Tight IRQ chip integration and banked infrastructure", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1099/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808963/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808963/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tFri, 01 Sep 2017 11:57:55 -0700 (PDT)", "From": "Thierry Reding <thierry.reding@gmail.com>", "To": "Linus Walleij <linus.walleij@linaro.org>", "Cc": "Jonathan Hunter <jonathanh@nvidia.com>, linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org", "Subject": "[PATCH 09/16] gpio: Move irq_valid_mask into struct gpio_irq_chip", "Date": "Fri, 1 Sep 2017 20:57:29 +0200", "Message-Id": "<20170901185736.28051-10-thierry.reding@gmail.com>", "X-Mailer": "git-send-email 2.13.3", "In-Reply-To": "<20170901185736.28051-1-thierry.reding@gmail.com>", "References": "<20170901185736.28051-1-thierry.reding@gmail.com>", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nIn order to consolidate the multiple ways to associate an IRQ chip with\na GPIO chip, move more fields into the new struct gpio_irq_chip.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\n Documentation/gpio/driver.txt | 4 ++--\n drivers/gpio/gpio-aspeed.c | 4 ++--\n drivers/gpio/gpio-stmpe.c | 4 ++--\n drivers/gpio/gpiolib.c | 16 ++++++++--------\n drivers/pinctrl/intel/pinctrl-baytrail.c | 4 ++--\n drivers/pinctrl/intel/pinctrl-cherryview.c | 4 ++--\n drivers/platform/x86/intel_int0002_vgpio.c | 4 ++--\n include/linux/gpio/driver.h | 21 +++++++++++++++------\n 8 files changed, 35 insertions(+), 26 deletions(-)", "diff": "diff --git a/Documentation/gpio/driver.txt b/Documentation/gpio/driver.txt\nindex dcf6af1d9e56..d8de1c7de85a 100644\n--- a/Documentation/gpio/driver.txt\n+++ b/Documentation/gpio/driver.txt\n@@ -313,8 +313,8 @@ symbol:\n mark all the child IRQs as having the other IRQ as parent.\n \n If there is a need to exclude certain GPIOs from the IRQ domain, you can\n-set .irq_need_valid_mask of the gpiochip before gpiochip_add_data() is\n-called. This allocates an .irq_valid_mask with as many bits set as there\n+set .irq.need_valid_mask of the gpiochip before gpiochip_add_data() is\n+called. This allocates an .irq.valid_mask with as many bits set as there\n are GPIOs in the chip. Drivers can exclude GPIOs by clearing bits from this\n mask. The mask must be filled in before gpiochip_irqchip_add() or\n gpiochip_irqchip_add_nested() is called.\ndiff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c\nindex a9342b471359..fbd551a0c634 100644\n--- a/drivers/gpio/gpio-aspeed.c\n+++ b/drivers/gpio/gpio-aspeed.c\n@@ -498,7 +498,7 @@ static void set_irq_valid_mask(struct aspeed_gpio *gpio)\n \t\t\tif (i >= gpio->config->nr_gpios)\n \t\t\t\tbreak;\n \n-\t\t\tclear_bit(i, gpio->chip.irq_valid_mask);\n+\t\t\tclear_bit(i, gpio->chip.irq.valid_mask);\n \t\t}\n \n \t\tprops++;\n@@ -853,7 +853,7 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)\n \tgpio->chip.set_config = aspeed_gpio_set_config;\n \tgpio->chip.label = dev_name(&pdev->dev);\n \tgpio->chip.base = -1;\n-\tgpio->chip.irq_need_valid_mask = true;\n+\tgpio->chip.irq.need_valid_mask = true;\n \n \trc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);\n \tif (rc < 0)\ndiff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c\nindex 5aee24fe0254..5b99ff7e75ef 100644\n--- a/drivers/gpio/gpio-stmpe.c\n+++ b/drivers/gpio/gpio-stmpe.c\n@@ -451,7 +451,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev)\n \tof_property_read_u32(np, \"st,norequest-mask\",\n \t\t\t&stmpe_gpio->norequest_mask);\n \tif (stmpe_gpio->norequest_mask)\n-\t\tstmpe_gpio->chip.irq_need_valid_mask = true;\n+\t\tstmpe_gpio->chip.irq.need_valid_mask = true;\n \n \tif (irq < 0)\n \t\tdev_info(&pdev->dev,\n@@ -482,7 +482,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev)\n \t\t\t/* Forbid unused lines to be mapped as IRQs */\n \t\t\tfor (i = 0; i < sizeof(u32); i++)\n \t\t\t\tif (stmpe_gpio->norequest_mask & BIT(i))\n-\t\t\t\t\tclear_bit(i, stmpe_gpio->chip.irq_valid_mask);\n+\t\t\t\t\tclear_bit(i, stmpe_gpio->chip.irq.valid_mask);\n \t\t}\n \t\tret = gpiochip_irqchip_add_nested(&stmpe_gpio->chip,\n \t\t\t\t\t\t &stmpe_gpio_irq_chip,\ndiff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\nindex f506473f5c70..6cec36126f44 100644\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -1514,33 +1514,33 @@ static struct gpio_chip *find_chip_by_name(const char *name)\n \n static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip)\n {\n-\tif (!gpiochip->irq_need_valid_mask)\n+\tif (!gpiochip->irq.need_valid_mask)\n \t\treturn 0;\n \n-\tgpiochip->irq_valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio),\n+\tgpiochip->irq.valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio),\n \t\t\t\t\t sizeof(long), GFP_KERNEL);\n-\tif (!gpiochip->irq_valid_mask)\n+\tif (!gpiochip->irq.valid_mask)\n \t\treturn -ENOMEM;\n \n \t/* Assume by default all GPIOs are valid */\n-\tbitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio);\n+\tbitmap_fill(gpiochip->irq.valid_mask, gpiochip->ngpio);\n \n \treturn 0;\n }\n \n static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)\n {\n-\tkfree(gpiochip->irq_valid_mask);\n-\tgpiochip->irq_valid_mask = NULL;\n+\tkfree(gpiochip->irq.valid_mask);\n+\tgpiochip->irq.valid_mask = NULL;\n }\n \n static bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,\n \t\t\t\t unsigned int offset)\n {\n \t/* No mask means all valid */\n-\tif (likely(!gpiochip->irq_valid_mask))\n+\tif (likely(!gpiochip->irq.valid_mask))\n \t\treturn true;\n-\treturn test_bit(offset, gpiochip->irq_valid_mask);\n+\treturn test_bit(offset, gpiochip->irq.valid_mask);\n }\n \n /**\ndiff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c\nindex 5897981e5ed3..9c1ca29c60b7 100644\n--- a/drivers/pinctrl/intel/pinctrl-baytrail.c\n+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c\n@@ -1660,7 +1660,7 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)\n \n \t\tvalue = readl(reg);\n \t\tif (value & BYT_DIRECT_IRQ_EN) {\n-\t\t\tclear_bit(i, gc->irq_valid_mask);\n+\t\t\tclear_bit(i, gc->irq.valid_mask);\n \t\t\tdev_dbg(dev, \"excluding GPIO %d from IRQ domain\\n\", i);\n \t\t} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {\n \t\t\tbyt_gpio_clear_triggering(vg, i);\n@@ -1703,7 +1703,7 @@ static int byt_gpio_probe(struct byt_gpio *vg)\n \tgc->can_sleep\t= false;\n \tgc->parent\t= &vg->pdev->dev;\n \tgc->ngpio\t= vg->soc_data->npins;\n-\tgc->irq_need_valid_mask\t= true;\n+\tgc->irq.need_valid_mask\t= true;\n \n #ifdef CONFIG_PM_SLEEP\n \tvg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,\ndiff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c\nindex 1cd7043edbc1..e23def322de2 100644\n--- a/drivers/pinctrl/intel/pinctrl-cherryview.c\n+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c\n@@ -1584,7 +1584,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)\n \tchip->label = dev_name(pctrl->dev);\n \tchip->parent = pctrl->dev;\n \tchip->base = -1;\n-\tchip->irq_need_valid_mask = need_valid_mask;\n+\tchip->irq.need_valid_mask = need_valid_mask;\n \n \tret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);\n \tif (ret) {\n@@ -1616,7 +1616,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)\n \t\tintsel >>= CHV_PADCTRL0_INTSEL_SHIFT;\n \n \t\tif (need_valid_mask && intsel >= pctrl->community->nirqs)\n-\t\t\tclear_bit(i, chip->irq_valid_mask);\n+\t\t\tclear_bit(i, chip->irq.valid_mask);\n \t}\n \n \t/* Clear all interrupts */\ndiff --git a/drivers/platform/x86/intel_int0002_vgpio.c b/drivers/platform/x86/intel_int0002_vgpio.c\nindex f6b3af73dea5..f7b67e898abc 100644\n--- a/drivers/platform/x86/intel_int0002_vgpio.c\n+++ b/drivers/platform/x86/intel_int0002_vgpio.c\n@@ -165,7 +165,7 @@ static int int0002_probe(struct platform_device *pdev)\n \tchip->direction_output = int0002_gpio_direction_output;\n \tchip->base = -1;\n \tchip->ngpio = GPE0A_PME_B0_VIRT_GPIO_PIN + 1;\n-\tchip->irq_need_valid_mask = true;\n+\tchip->irq.need_valid_mask = true;\n \n \tret = devm_gpiochip_add_data(&pdev->dev, chip, NULL);\n \tif (ret) {\n@@ -173,7 +173,7 @@ static int int0002_probe(struct platform_device *pdev)\n \t\treturn ret;\n \t}\n \n-\tbitmap_clear(chip->irq_valid_mask, 0, GPE0A_PME_B0_VIRT_GPIO_PIN);\n+\tbitmap_clear(chip->irq.valid_mask, 0, GPE0A_PME_B0_VIRT_GPIO_PIN);\n \n \t/*\n \t * We manually request the irq here instead of passing a flow-handler\ndiff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h\nindex 7d632a8932be..f8d31e7da9cc 100644\n--- a/include/linux/gpio/driver.h\n+++ b/include/linux/gpio/driver.h\n@@ -114,6 +114,21 @@ struct gpio_irq_chip {\n \t * True if set the interrupt handling is nested.\n \t */\n \tbool nested;\n+\n+\t/**\n+\t * @need_valid_mask:\n+\t *\n+\t * If set core allocates @valid_mask with all bits set to one.\n+\t */\n+\tbool need_valid_mask;\n+\n+\t/**\n+\t * @valid_mask:\n+\t *\n+\t * If not %NULL holds bitmask of GPIOs which are valid to be included\n+\t * in IRQ domain of the chip.\n+\t */\n+\tunsigned long *valid_mask;\n };\n \n static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n@@ -183,10 +198,6 @@ static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n *\tsafely.\n * @bgpio_dir: shadowed direction register for generic GPIO to clear/set\n *\tdirection safely.\n- * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all\n- *\tbits set to one\n- * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to\n- *\tbe included in IRQ domain of the chip\n * @lock_key: per GPIO IRQ chip lockdep class\n *\n * A gpio_chip can help platforms abstract various sources of GPIOs so\n@@ -254,8 +265,6 @@ struct gpio_chip {\n \t * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib\n \t * to handle IRQs for most practical cases.\n \t */\n-\tbool\t\t\tirq_need_valid_mask;\n-\tunsigned long\t\t*irq_valid_mask;\n \tstruct lock_class_key\t*lock_key;\n \n \t/**\n", "prefixes": [ "09/16" ] }