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GET /api/patches/808961/?format=api
{ "id": 808961, "url": "http://patchwork.ozlabs.org/api/patches/808961/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170901185736.28051-11-thierry.reding@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170901185736.28051-11-thierry.reding@gmail.com>", "list_archive_url": null, "date": "2017-09-01T18:57:30", "name": "[10/16] gpio: Move lock_key into struct gpio_irq_chip", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a4b0e63f7b32a17b047ff401594590b93ad60ded", "submitter": { "id": 26234, "url": "http://patchwork.ozlabs.org/api/people/26234/?format=api", "name": "Thierry Reding", "email": "thierry.reding@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170901185736.28051-11-thierry.reding@gmail.com/mbox/", "series": [ { "id": 1098, "url": "http://patchwork.ozlabs.org/api/series/1098/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=1098", "date": "2017-09-01T18:57:20", "name": "gpio: Tight IRQ chip integration and banked infrastructure", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1098/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808961/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808961/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Lv1CGIXL\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkT8B1gNtz9sRV\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 2 Sep 2017 05:00:10 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752600AbdIAS76 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 1 Sep 2017 14:59:58 -0400", "from mail-wr0-f194.google.com ([209.85.128.194]:34193 \"EHLO\n\tmail-wr0-f194.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752529AbdIAS56 (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Fri, 1 Sep 2017 14:57:58 -0400", "by mail-wr0-f194.google.com with SMTP id z91so491086wrc.1;\n\tFri, 01 Sep 2017 11:57:57 -0700 (PDT)", "from localhost\n\t(p200300E41BD6D60076D02BFFFE273F51.dip0.t-ipconnect.de.\n\t[2003:e4:1bd6:d600:76d0:2bff:fe27:3f51])\n\tby smtp.gmail.com with ESMTPSA id 6sm717925wre.0.2017.09.01.11.57.55\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tFri, 01 Sep 2017 11:57:56 -0700 (PDT)" ], "DKIM-Signature": "v=1; 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\n\tFri, 01 Sep 2017 11:57:56 -0700 (PDT)", "From": "Thierry Reding <thierry.reding@gmail.com>", "To": "Linus Walleij <linus.walleij@linaro.org>", "Cc": "Jonathan Hunter <jonathanh@nvidia.com>, linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org", "Subject": "[PATCH 10/16] gpio: Move lock_key into struct gpio_irq_chip", "Date": "Fri, 1 Sep 2017 20:57:30 +0200", "Message-Id": "<20170901185736.28051-11-thierry.reding@gmail.com>", "X-Mailer": "git-send-email 2.13.3", "In-Reply-To": "<20170901185736.28051-1-thierry.reding@gmail.com>", "References": "<20170901185736.28051-1-thierry.reding@gmail.com>", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nIn order to consolidate the multiple ways to associate an IRQ chip with\na GPIO chip, move more fields into the new struct gpio_irq_chip.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\n drivers/gpio/gpiolib.c | 4 ++--\n include/linux/gpio/driver.h | 9 +++++++--\n 2 files changed, 9 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\nindex 6cec36126f44..7a16dd37bd3d 100644\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -1656,7 +1656,7 @@ int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,\n \t * This lock class tells lockdep that GPIO irqs are in a different\n \t * category than their parents, so it won't report false recursion.\n \t */\n-\tirq_set_lockdep_class(irq, chip->lock_key);\n+\tirq_set_lockdep_class(irq, chip->irq.lock_key);\n \tirq_set_chip_and_handler(irq, chip->irq.chip, chip->irq.handler);\n \t/* Chips that use nested thread handlers have them marked */\n \tif (chip->irq.nested)\n@@ -1959,7 +1959,7 @@ int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,\n \tgpiochip->irq.handler = handler;\n \tgpiochip->irq.default_type = type;\n \tgpiochip->to_irq = gpiochip_to_irq;\n-\tgpiochip->lock_key = lock_key;\n+\tgpiochip->irq.lock_key = lock_key;\n \tgpiochip->irq.domain = irq_domain_add_simple(of_node,\n \t\t\t\t\tgpiochip->ngpio, first_irq,\n \t\t\t\t\t&gpiochip_domain_ops, gpiochip);\ndiff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h\nindex f8d31e7da9cc..c453e0716228 100644\n--- a/include/linux/gpio/driver.h\n+++ b/include/linux/gpio/driver.h\n@@ -71,6 +71,13 @@ struct gpio_irq_chip {\n \tunsigned int default_type;\n \n \t/**\n+\t * @lock_key:\n+\t *\n+\t * Per GPIO IRQ chip lockdep class.\n+\t */\n+\tstruct lock_class_key *lock_key;\n+\n+\t/**\n \t * @parent_handler:\n \t *\n \t * The interrupt handler for the GPIO chip's parent interrupts, may be\n@@ -198,7 +205,6 @@ static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n *\tsafely.\n * @bgpio_dir: shadowed direction register for generic GPIO to clear/set\n *\tdirection safely.\n- * @lock_key: per GPIO IRQ chip lockdep class\n *\n * A gpio_chip can help platforms abstract various sources of GPIOs so\n * they can all be accessed through a common programing interface.\n@@ -265,7 +271,6 @@ struct gpio_chip {\n \t * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib\n \t * to handle IRQs for most practical cases.\n \t */\n-\tstruct lock_class_key\t*lock_key;\n \n \t/**\n \t * @irq:\n", "prefixes": [ "10/16" ] }