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GET /api/patches/808953/?format=api
{ "id": 808953, "url": "http://patchwork.ozlabs.org/api/patches/808953/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170901185736.28051-16-thierry.reding@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170901185736.28051-16-thierry.reding@gmail.com>", "list_archive_url": null, "date": "2017-09-01T18:57:35", "name": "[15/16] gpio: tegra: Use banked GPIO infrastructure", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5aee9c95b8f233ffc41e506ab576e8abfbbfba5e", "submitter": { "id": 26234, "url": "http://patchwork.ozlabs.org/api/people/26234/?format=api", "name": "Thierry Reding", "email": "thierry.reding@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170901185736.28051-16-thierry.reding@gmail.com/mbox/", "series": [ { "id": 1098, "url": "http://patchwork.ozlabs.org/api/series/1098/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=1098", "date": "2017-09-01T18:57:20", "name": "gpio: Tight IRQ chip integration and banked infrastructure", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1098/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808953/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808953/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"jshVj8d3\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkT6w1kRMz9sPm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 2 Sep 2017 04:59:04 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752329AbdIAS6c (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 1 Sep 2017 14:58:32 -0400", "from mail-wm0-f66.google.com ([74.125.82.66]:34847 \"EHLO\n\tmail-wm0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752569AbdIAS6H (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Fri, 1 Sep 2017 14:58:07 -0400", "by mail-wm0-f66.google.com with SMTP id e204so964328wma.2;\n\tFri, 01 Sep 2017 11:58:06 -0700 (PDT)", "from localhost\n\t(p200300E41BD6D60076D02BFFFE273F51.dip0.t-ipconnect.de.\n\t[2003:e4:1bd6:d600:76d0:2bff:fe27:3f51])\n\tby smtp.gmail.com with ESMTPSA id\n\tl4sm653323wrb.70.2017.09.01.11.58.04\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tFri, 01 Sep 2017 11:58:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=YG7Ugx3dX0q5S01R7qpc3WHptGIboJ/nl2v2wFURo+0=;\n\tb=jshVj8d3o7a1g0gxwJGW/ctHKBG4lBdgLFA5hEToL/oitA4oUz2ec40Iz7nS0oYnq+\n\t1QqKMrDcFXAaWDMerOUtHmFcfvOYROoCuShvq6dKzVzcdq6ezOzXqX4x38jELUu6pWfl\n\ti8l8DXdttwmTGBZuxS8oUPLFhOET3Bd/OoiYCyRVtEGb5ZJwj8h5Rm/p3zl8EEAYCKdF\n\tY1lIQTSeTdFBfweF6oUdfks4ifZdWITe30yXqs/IVl7wa2FQkwF+rdN2874QxyofiYfe\n\tnM17EByU5kFOedg23vcpgcJKVPtdHpovlEFaHviufjoBWI3m8HCtgbMVNNmBEDq3PUtc\n\t5x3g==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=YG7Ugx3dX0q5S01R7qpc3WHptGIboJ/nl2v2wFURo+0=;\n\tb=d2gbhgrBRh7gA9j/TV76sqV4C1H+90wOjQ1DEuuPatMDNFb71nSuDHZoGzhCCqKAKW\n\tTzaGx0dyIgZJTk6Y8PT/s9fzXv18KHg7AUNAu8UB7e57DB8ztjQOQfYSsOXIK4NUHd+D\n\tJOMOQAcPl2kKECgPrE+pt1JalmjnfbjsUbWS3obWvLEMB6QKLdFtKXn/LP54ABtGhJt6\n\tvGxPrCMMyVm280yw/pVHYx3WtDq+SPMhA4hwCItZVXQpOzYoo83NOxYIBmUPpYWlmpXG\n\t0vPfBm6F3Dd/ueGCkQTt2DwAo4sju6WzjzpfEvYtgiDMGLW7yuVZJSaJt0oAwloA9D44\n\twgXw==", "X-Gm-Message-State": "AHPjjUiSVIicY09srBtuIP6k1fTWtezPMa2MNvp6xGG9PmFaYqhq0HZD\n\tVD4CjEjkLNYG8g==", "X-Google-Smtp-Source": "ADKCNb7+p8kPzonGbrWSYUva0mvM/h8dG5NQT1nmKnL9KFwAfXd5/L70whJePAFIwKrlrpIg0M/hLA==", "X-Received": "by 10.28.87.1 with SMTP id l1mr899216wmb.99.1504292285558;\n\tFri, 01 Sep 2017 11:58:05 -0700 (PDT)", "From": "Thierry Reding <thierry.reding@gmail.com>", "To": "Linus Walleij <linus.walleij@linaro.org>", "Cc": "Jonathan Hunter <jonathanh@nvidia.com>, linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org", "Subject": "[PATCH 15/16] gpio: tegra: Use banked GPIO infrastructure", "Date": "Fri, 1 Sep 2017 20:57:35 +0200", "Message-Id": "<20170901185736.28051-16-thierry.reding@gmail.com>", "X-Mailer": "git-send-email 2.13.3", "In-Reply-To": "<20170901185736.28051-1-thierry.reding@gmail.com>", "References": "<20170901185736.28051-1-thierry.reding@gmail.com>", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nConvert the Tegra GPIO driver to use the banked GPIO infrastructure,\nwhich simplifies some parts of the driver.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\n drivers/gpio/Kconfig | 1 +\n drivers/gpio/gpio-tegra.c | 203 ++++++++++++++++++++++------------------------\n 2 files changed, 98 insertions(+), 106 deletions(-)", "diff": "diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig\nindex f9e22c6fdd02..9364f037fe86 100644\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -439,6 +439,7 @@ config GPIO_TEGRA\n \tdefault ARCH_TEGRA\n \tdepends on ARCH_TEGRA || COMPILE_TEST\n \tdepends on OF_GPIO\n+\tselect GPIOLIB_IRQCHIP\n \thelp\n \t Say yes here to support GPIO pins on NVIDIA Tegra SoCs.\n \ndiff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c\nindex fbaf974277df..250cebc3ab60 100644\n--- a/drivers/gpio/gpio-tegra.c\n+++ b/drivers/gpio/gpio-tegra.c\n@@ -67,8 +67,8 @@\n struct tegra_gpio_info;\n \n struct tegra_gpio_bank {\n-\tunsigned int bank;\n-\tunsigned int irq;\n+\tstruct gpio_bank bank;\n+\tunsigned int index;\n \tspinlock_t lvl_lock[4];\n \tspinlock_t dbc_lock[4];\t/* Lock for updating debounce count register */\n #ifdef CONFIG_PM_SLEEP\n@@ -84,6 +84,11 @@ struct tegra_gpio_bank {\n \tstruct tegra_gpio_info *tgi;\n };\n \n+static struct tegra_gpio_bank *to_tegra_gpio_bank(struct gpio_bank *bank)\n+{\n+\treturn container_of(bank, struct tegra_gpio_bank, bank);\n+}\n+\n struct tegra_gpio_soc_config {\n \tbool debounce_supported;\n \tu32 bank_stride;\n@@ -98,9 +103,14 @@ struct tegra_gpio_info {\n \tconst struct tegra_gpio_soc_config\t*soc;\n \tstruct gpio_chip\t\t\tgc;\n \tstruct irq_chip\t\t\t\tic;\n-\tu32\t\t\t\t\tbank_count;\n };\n \n+static inline struct tegra_gpio_info *\n+to_tegra_gpio_info(struct gpio_chip *chip)\n+{\n+\treturn container_of(chip, struct tegra_gpio_info, gc);\n+}\n+\n static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,\n \t\t\t\t u32 val, u32 reg)\n {\n@@ -264,8 +274,8 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)\n \n static void tegra_gpio_irq_ack(struct irq_data *d)\n {\n-\tstruct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);\n-\tstruct tegra_gpio_info *tgi = bank->tgi;\n+\tstruct gpio_chip *chip = irq_data_get_irq_chip_data(d);\n+\tstruct tegra_gpio_info *tgi = to_tegra_gpio_info(chip);\n \tunsigned int gpio = d->hwirq;\n \n \ttegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));\n@@ -273,8 +283,8 @@ static void tegra_gpio_irq_ack(struct irq_data *d)\n \n static void tegra_gpio_irq_mask(struct irq_data *d)\n {\n-\tstruct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);\n-\tstruct tegra_gpio_info *tgi = bank->tgi;\n+\tstruct gpio_chip *chip = irq_data_get_irq_chip_data(d);\n+\tstruct tegra_gpio_info *tgi = to_tegra_gpio_info(chip);\n \tunsigned int gpio = d->hwirq;\n \n \ttegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);\n@@ -282,8 +292,8 @@ static void tegra_gpio_irq_mask(struct irq_data *d)\n \n static void tegra_gpio_irq_unmask(struct irq_data *d)\n {\n-\tstruct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);\n-\tstruct tegra_gpio_info *tgi = bank->tgi;\n+\tstruct gpio_chip *chip = irq_data_get_irq_chip_data(d);\n+\tstruct tegra_gpio_info *tgi = to_tegra_gpio_info(chip);\n \tunsigned int gpio = d->hwirq;\n \n \ttegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);\n@@ -292,12 +302,15 @@ static void tegra_gpio_irq_unmask(struct irq_data *d)\n static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)\n {\n \tunsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;\n-\tstruct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);\n-\tstruct tegra_gpio_info *tgi = bank->tgi;\n+\tstruct gpio_chip *chip = irq_data_get_irq_chip_data(d);\n+\tstruct tegra_gpio_info *tgi = to_tegra_gpio_info(chip);\n+\tstruct tegra_gpio_bank *bank;\n \tunsigned long flags;\n \tu32 val;\n \tint ret;\n \n+\tbank = &tgi->bank_info[GPIO_BANK(gpio)];\n+\n \tswitch (type & IRQ_TYPE_SENSE_MASK) {\n \tcase IRQ_TYPE_EDGE_RISING:\n \t\tlvl_type = GPIO_INT_LVL_EDGE_RISING;\n@@ -352,52 +365,27 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)\n \n static void tegra_gpio_irq_shutdown(struct irq_data *d)\n {\n-\tstruct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);\n-\tstruct tegra_gpio_info *tgi = bank->tgi;\n-\tunsigned int gpio = d->hwirq;\n+\tstruct gpio_chip *chip = irq_data_get_irq_chip_data(d);\n \n-\tgpiochip_unlock_as_irq(&tgi->gc, gpio);\n+\tgpiochip_unlock_as_irq(chip, d->hwirq);\n }\n \n-static void tegra_gpio_irq_handler(struct irq_desc *desc)\n+static void tegra_gpio_update_bank(struct gpio_bank *bank)\n {\n-\tunsigned int port, pin, gpio;\n-\tbool unmasked = false;\n-\tu32 lvl;\n-\tunsigned long sta;\n-\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n-\tstruct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);\n-\tstruct tegra_gpio_info *tgi = bank->tgi;\n-\n-\tchained_irq_enter(chip, desc);\n+\tstruct tegra_gpio_info *tgi = to_tegra_gpio_info(bank->chip);\n+\tstruct tegra_gpio_bank *b = to_tegra_gpio_bank(bank);\n+\tunsigned int port;\n \n \tfor (port = 0; port < 4; port++) {\n-\t\tgpio = tegra_gpio_compose(bank->bank, port, 0);\n-\t\tsta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &\n-\t\t\ttegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));\n-\t\tlvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));\n-\n-\t\tfor_each_set_bit(pin, &sta, 8) {\n-\t\t\ttegra_gpio_writel(tgi, 1 << pin,\n-\t\t\t\t\t GPIO_INT_CLR(tgi, gpio));\n-\n-\t\t\t/* if gpio is edge triggered, clear condition\n-\t\t\t * before executing the handler so that we don't\n-\t\t\t * miss edges\n-\t\t\t */\n-\t\t\tif (!unmasked && lvl & (0x100 << pin)) {\n-\t\t\t\tunmasked = true;\n-\t\t\t\tchained_irq_exit(chip, desc);\n-\t\t\t}\n+\t\tunsigned int gpio = tegra_gpio_compose(b->index, port, 0);\n+\t\tu8 *pending = (u8 *)bank->pending;\n+\t\tu32 status, enable;\n \n-\t\t\tgeneric_handle_irq(irq_find_mapping(tgi->irq_domain,\n-\t\t\t\t\t\t\t gpio + pin));\n-\t\t}\n-\t}\n-\n-\tif (!unmasked)\n-\t\tchained_irq_exit(chip, desc);\n+\t\tstatus = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio));\n+\t\tenable = tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));\n \n+\t\tpending[port] = status & enable;\n+\t}\n }\n \n #ifdef CONFIG_PM_SLEEP\n@@ -410,7 +398,7 @@ static int tegra_gpio_resume(struct device *dev)\n \n \tlocal_irq_save(flags);\n \n-\tfor (b = 0; b < tgi->bank_count; b++) {\n+\tfor (b = 0; b < tgi->gc.num_banks; b++) {\n \t\tstruct tegra_gpio_bank *bank = &tgi->bank_info[b];\n \n \t\tfor (p = 0; p < ARRAY_SIZE(bank->oe); p++) {\n@@ -449,7 +437,7 @@ static int tegra_gpio_suspend(struct device *dev)\n \tunsigned int b, p;\n \n \tlocal_irq_save(flags);\n-\tfor (b = 0; b < tgi->bank_count; b++) {\n+\tfor (b = 0; b < tgi->gc.num_banks; b++) {\n \t\tstruct tegra_gpio_bank *bank = &tgi->bank_info[b];\n \n \t\tfor (p = 0; p < ARRAY_SIZE(bank->oe); p++) {\n@@ -484,20 +472,26 @@ static int tegra_gpio_suspend(struct device *dev)\n \n static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)\n {\n-\tstruct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);\n-\tunsigned int gpio = d->hwirq;\n+\tstruct gpio_chip *chip = irq_data_get_irq_chip_data(d);\n+\tunsigned int gpio = d->hwirq, parent_irq;\n+\tstruct tegra_gpio_bank *b;\n+\tstruct gpio_bank *bank;\n \tu32 port, bit, mask;\n \n+\tbank = chip->banks[GPIO_BANK(gpio)];\n+\tb = to_tegra_gpio_bank(bank);\n \tport = GPIO_PORT(gpio);\n \tbit = GPIO_BIT(gpio);\n \tmask = BIT(bit);\n \n \tif (enable)\n-\t\tbank->wake_enb[port] |= mask;\n+\t\tb->wake_enb[port] |= mask;\n \telse\n-\t\tbank->wake_enb[port] &= ~mask;\n+\t\tb->wake_enb[port] &= ~mask;\n+\n+\tparent_irq = chip->irq.parents[bank->parent_irq];\n \n-\treturn irq_set_irq_wake(bank->irq, enable);\n+\treturn irq_set_irq_wake(parent_irq, enable);\n }\n #endif\n \n@@ -511,7 +505,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)\n \tstruct tegra_gpio_info *tgi = s->private;\n \tunsigned int i, j;\n \n-\tfor (i = 0; i < tgi->bank_count; i++) {\n+\tfor (i = 0; i < tgi->gc.num_banks; i++) {\n \t\tfor (j = 0; j < 4; j++) {\n \t\t\tunsigned int gpio = tegra_gpio_compose(i, j, 0);\n \n@@ -561,17 +555,18 @@ static const struct dev_pm_ops tegra_gpio_pm_ops = {\n };\n \n /*\n- * This lock class tells lockdep that GPIO irqs are in a different category\n+ * This lock class tells lockdep that GPIO IRQs are in a different category\n * than their parents, so it won't report false recursion.\n */\n-static struct lock_class_key gpio_lock_class;\n+static struct lock_class_key tegra_gpio_lock_class;\n \n static int tegra_gpio_probe(struct platform_device *pdev)\n {\n \tstruct tegra_gpio_info *tgi;\n \tstruct resource *res;\n \tstruct tegra_gpio_bank *bank;\n-\tunsigned int gpio, i, j;\n+\tstruct gpio_irq_chip *irq;\n+\tunsigned int i, j;\n \tint ret;\n \n \ttgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);\n@@ -580,14 +575,20 @@ static int tegra_gpio_probe(struct platform_device *pdev)\n \n \ttgi->soc = of_device_get_match_data(&pdev->dev);\n \ttgi->dev = &pdev->dev;\n+\tirq = &tgi->gc.irq;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\ttgi->regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(tgi->regs))\n+\t\treturn PTR_ERR(tgi->regs);\n \n \tret = platform_irq_count(pdev);\n \tif (ret < 0)\n \t\treturn ret;\n \n-\ttgi->bank_count = ret;\n+\ttgi->gc.num_banks = ret;\n \n-\tif (!tgi->bank_count) {\n+\tif (!tgi->gc.num_banks) {\n \t\tdev_err(&pdev->dev, \"Missing IRQ resource\\n\");\n \t\treturn -ENODEV;\n \t}\n@@ -602,7 +603,7 @@ static int tegra_gpio_probe(struct platform_device *pdev)\n \ttgi->gc.get_direction\t\t= tegra_gpio_get_direction;\n \ttgi->gc.to_irq\t\t\t= tegra_gpio_to_irq;\n \ttgi->gc.base\t\t\t= 0;\n-\ttgi->gc.ngpio\t\t\t= tgi->bank_count * 32;\n+\ttgi->gc.ngpio\t\t\t= tgi->gc.num_banks * 32;\n \ttgi->gc.parent\t\t\t= &pdev->dev;\n \ttgi->gc.of_node\t\t\t= pdev->dev.of_node;\n \n@@ -616,76 +617,66 @@ static int tegra_gpio_probe(struct platform_device *pdev)\n \ttgi->ic.irq_set_wake\t\t= tegra_gpio_irq_set_wake;\n #endif\n \n+\tirq = &tgi->gc.irq;\n+\tirq->chip = &tgi->ic;\n+\tirq->handler = handle_simple_irq;\n+\tirq->lock_key = &tegra_gpio_lock_class;\n+\tirq->default_type = IRQ_TYPE_NONE;\n+\tirq->parent_handler = gpio_irq_chip_banked_handler;\n+\tirq->update_bank = tegra_gpio_update_bank;\n+\n+\tirq->parents = devm_kcalloc(&pdev->dev, tgi->gc.num_banks,\n+\t\t\t\t sizeof(unsigned int), GFP_KERNEL);\n+\tif (!irq->parents)\n+\t\treturn -ENOMEM;\n+\n+\tirq->num_parents = tgi->gc.num_banks;\n+\n \tplatform_set_drvdata(pdev, tgi);\n \n \tif (tgi->soc->debounce_supported)\n \t\ttgi->gc.set_config = tegra_gpio_set_config;\n \n-\ttgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,\n+\ttgi->bank_info = devm_kcalloc(&pdev->dev, tgi->gc.num_banks,\n \t\t\t\t sizeof(*tgi->bank_info), GFP_KERNEL);\n \tif (!tgi->bank_info)\n \t\treturn -ENOMEM;\n \n-\ttgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,\n-\t\t\t\t\t\ttgi->gc.ngpio,\n-\t\t\t\t\t\t&irq_domain_simple_ops, NULL);\n-\tif (!tgi->irq_domain)\n-\t\treturn -ENODEV;\n+\ttgi->gc.banks = devm_kcalloc(&pdev->dev, tgi->gc.num_banks,\n+\t\t\t\t sizeof(struct gpio_bank *),\n+\t\t\t\t GFP_KERNEL);\n+\tif (!tgi->gc.banks)\n+\t\treturn -ENOMEM;\n \n-\tfor (i = 0; i < tgi->bank_count; i++) {\n+\tfor (i = 0; i < tgi->gc.num_banks; i++) {\n \t\tret = platform_get_irq(pdev, i);\n \t\tif (ret < 0) {\n \t\t\tdev_err(&pdev->dev, \"Missing IRQ resource: %d\\n\", ret);\n \t\t\treturn ret;\n \t\t}\n \n+\t\tirq->parents[i] = ret;\n+\n \t\tbank = &tgi->bank_info[i];\n-\t\tbank->bank = i;\n-\t\tbank->irq = ret;\n-\t\tbank->tgi = tgi;\n-\t}\n+\t\tbank->bank.chip = &tgi->gc;\n+\t\tbank->bank.parent_irq = i;\n+\t\tbank->bank.num_pins = 32;\n+\t\tbank->index = i;\n \n-\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n-\ttgi->regs = devm_ioremap_resource(&pdev->dev, res);\n-\tif (IS_ERR(tgi->regs))\n-\t\treturn PTR_ERR(tgi->regs);\n+\t\ttgi->gc.banks[i] = &bank->bank;\n \n-\tfor (i = 0; i < tgi->bank_count; i++) {\n \t\tfor (j = 0; j < 4; j++) {\n-\t\t\tint gpio = tegra_gpio_compose(i, j, 0);\n+\t\t\tunsigned int gpio = tegra_gpio_compose(i, j, 0);\n \n \t\t\ttegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));\n+\t\t\tspin_lock_init(&bank->lvl_lock[j]);\n+\t\t\tspin_lock_init(&bank->dbc_lock[j]);\n \t\t}\n \t}\n \n \tret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);\n-\tif (ret < 0) {\n-\t\tirq_domain_remove(tgi->irq_domain);\n+\tif (ret < 0)\n \t\treturn ret;\n-\t}\n-\n-\tfor (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {\n-\t\tint irq = irq_create_mapping(tgi->irq_domain, gpio);\n-\t\t/* No validity check; all Tegra GPIOs are valid IRQs */\n-\n-\t\tbank = &tgi->bank_info[GPIO_BANK(gpio)];\n-\n-\t\tirq_set_lockdep_class(irq, &gpio_lock_class);\n-\t\tirq_set_chip_data(irq, bank);\n-\t\tirq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);\n-\t}\n-\n-\tfor (i = 0; i < tgi->bank_count; i++) {\n-\t\tbank = &tgi->bank_info[i];\n-\n-\t\tirq_set_chained_handler_and_data(bank->irq,\n-\t\t\t\t\t\t tegra_gpio_irq_handler, bank);\n-\n-\t\tfor (j = 0; j < 4; j++) {\n-\t\t\tspin_lock_init(&bank->lvl_lock[j]);\n-\t\t\tspin_lock_init(&bank->dbc_lock[j]);\n-\t\t}\n-\t}\n \n \ttegra_gpio_debuginit(tgi);\n \n", "prefixes": [ "15/16" ] }