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GET /api/patches/808951/?format=api
{ "id": 808951, "url": "http://patchwork.ozlabs.org/api/patches/808951/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170901185736.28051-17-thierry.reding@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170901185736.28051-17-thierry.reding@gmail.com>", "list_archive_url": null, "date": "2017-09-01T18:57:36", "name": "[16/16] gpio: tegra186: Use banked GPIO infrastructure", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4f22594ded517b0dd26f091fa4db14b3b38dab07", "submitter": { "id": 26234, "url": "http://patchwork.ozlabs.org/api/people/26234/?format=api", "name": "Thierry Reding", "email": "thierry.reding@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170901185736.28051-17-thierry.reding@gmail.com/mbox/", "series": [ { "id": 1098, "url": "http://patchwork.ozlabs.org/api/series/1098/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=1098", "date": "2017-09-01T18:57:20", "name": "gpio: Tight IRQ chip integration and banked infrastructure", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1098/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808951/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808951/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"TB9yO/C1\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkT685B2Jz9sQl\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 2 Sep 2017 04:58:24 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752601AbdIAS6M (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 1 Sep 2017 14:58:12 -0400", "from mail-wm0-f68.google.com ([74.125.82.68]:34363 \"EHLO\n\tmail-wm0-f68.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752588AbdIAS6J (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Fri, 1 Sep 2017 14:58:09 -0400", "by mail-wm0-f68.google.com with SMTP id l19so970036wmi.1;\n\tFri, 01 Sep 2017 11:58:08 -0700 (PDT)", "from localhost\n\t(p200300E41BD6D60076D02BFFFE273F51.dip0.t-ipconnect.de.\n\t[2003:e4:1bd6:d600:76d0:2bff:fe27:3f51])\n\tby smtp.gmail.com with ESMTPSA id\n\to191sm334549wmd.35.2017.09.01.11.58.06\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tFri, 01 Sep 2017 11:58:06 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=6HdMk8gqbdAzOBlpD1yg++ZCy9OJVxKiPShQ/RGw4ls=;\n\tb=TB9yO/C1kEPfKp9SBMqr6iiKd60Z1dcTVS1Cnt8aI5fvHjrcoHIrHuXwbKDUGLdPlu\n\tEjElXb3Ymc0eCY7wpub8TYWaM0KwGo1Eublr1T/7zvJ6RpLEYz8P7Bq9F0R4MMZWmMN/\n\tpzvY3flXWEeg0nh5a+PthLL8u9r+q3FTTiMl5SfvGHE6SyQUBy8uLq0jcWJN98dxnQqo\n\ta6Pd9d1ifY2NlQa3SoAVIK+xLH0YsYHDUaIfWSeJwr6EI63t+C21Lzr7QM20gwSMBerX\n\tBJpaKx9IC+tcXvaw6VXJasv2QxQuJdZmvjO/ZCzBz4pzXWJ3Kf6encjqvDIIaqrZeVvz\n\t0ujw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=6HdMk8gqbdAzOBlpD1yg++ZCy9OJVxKiPShQ/RGw4ls=;\n\tb=isaIg4Kq1BoXmZI/dhUVgrOuRbsjeIoT4SCJMXYRCu6LvUVJUH7y7Y2SOTV961fyUE\n\tA3AxkqDn5SchiKYlnKPdG79ZwfOk9aDyZ37rm/rTzXBlbRp+I9oqlFGh3J//zkVrqEda\n\tnBlAZTqJxZRZVKTc43wjuExArxtXvHK+cbEaUznP2S5ED2Uust5jRdMOTqHsYer95TY6\n\tihOmPb5kXp4a4qZJxUlD9L3v+XitHdE2L+gzBu+yMbnVAFiRlDV/YCsc25Vm9STvuwzr\n\tVSCC2+vHaiGhpOX7DS6PL3zFlQMu5J7fEkPHtBRdvAIryYsv876VHykNWs5GmOBdKah0\n\t4NxQ==", "X-Gm-Message-State": "AHPjjUhvStWglBzlDeMvePP9R2yqthIiHH94ANYScOyfJx0jv9eRIuhw\n\th1X/Xpjm0f/dUKPk", "X-Google-Smtp-Source": "ADKCNb7YWqrNTfCehhZkazmGAtpxI6NBAUbr/pTfrRadzzUzYqzynnHRn3V2rnN9uuoUmY6xXoq5sw==", "X-Received": "by 10.28.1.86 with SMTP id 83mr1176667wmb.191.1504292287295;\n\tFri, 01 Sep 2017 11:58:07 -0700 (PDT)", "From": "Thierry Reding <thierry.reding@gmail.com>", "To": "Linus Walleij <linus.walleij@linaro.org>", "Cc": "Jonathan Hunter <jonathanh@nvidia.com>, linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org", "Subject": "[PATCH 16/16] gpio: tegra186: Use banked GPIO infrastructure", "Date": "Fri, 1 Sep 2017 20:57:36 +0200", "Message-Id": "<20170901185736.28051-17-thierry.reding@gmail.com>", "X-Mailer": "git-send-email 2.13.3", "In-Reply-To": "<20170901185736.28051-1-thierry.reding@gmail.com>", "References": "<20170901185736.28051-1-thierry.reding@gmail.com>", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nConvert the Tegra186 GPIO driver to use the banked GPIO infrastructure,\nwhich simplifies some parts of the driver.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\n drivers/gpio/gpio-tegra186.c | 211 ++++++++++++++++---------------------------\n 1 file changed, 79 insertions(+), 132 deletions(-)", "diff": "diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c\nindex 162dc6b41ae8..4926b98a05f6 100644\n--- a/drivers/gpio/gpio-tegra186.c\n+++ b/drivers/gpio/gpio-tegra186.c\n@@ -13,6 +13,7 @@\n #include <linux/irq.h>\n #include <linux/module.h>\n #include <linux/of_device.h>\n+#include <linux/of_gpio.h>\n #include <linux/platform_device.h>\n \n #include <dt-bindings/gpio/tegra186-gpio.h>\n@@ -44,15 +45,27 @@\n \n #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)\n \n-struct tegra_gpio_port {\n+struct tegra_gpio_port_soc {\n \tconst char *name;\n \tunsigned int offset;\n \tunsigned int pins;\n \tunsigned int irq;\n };\n \n+struct tegra_gpio_port {\n+\tstruct gpio_bank bank;\n+\tunsigned int offset;\n+\tconst char *name;\n+};\n+\n+static inline struct tegra_gpio_port *\n+to_tegra_gpio_port(struct gpio_bank *bank)\n+{\n+\treturn container_of(bank, struct tegra_gpio_port, bank);\n+}\n+\n struct tegra_gpio_soc {\n-\tconst struct tegra_gpio_port *ports;\n+\tconst struct tegra_gpio_port_soc *ports;\n \tunsigned int num_ports;\n \tconst char *name;\n };\n@@ -60,21 +73,21 @@ struct tegra_gpio_soc {\n struct tegra_gpio {\n \tstruct gpio_chip gpio;\n \tstruct irq_chip intc;\n-\tunsigned int num_irq;\n-\tunsigned int *irq;\n \n \tconst struct tegra_gpio_soc *soc;\n \n+\tstruct tegra_gpio_port *ports;\n+\n \tvoid __iomem *base;\n };\n \n-static const struct tegra_gpio_port *\n+static const struct tegra_gpio_port_soc *\n tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)\n {\n \tunsigned int start = 0, i;\n \n \tfor (i = 0; i < gpio->soc->num_ports; i++) {\n-\t\tconst struct tegra_gpio_port *port = &gpio->soc->ports[i];\n+\t\tconst struct tegra_gpio_port_soc *port = &gpio->soc->ports[i];\n \n \t\tif (*pin >= start && *pin < start + port->pins) {\n \t\t\t*pin -= start;\n@@ -90,7 +103,7 @@ tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)\n static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,\n \t\t\t\t\t unsigned int pin)\n {\n-\tconst struct tegra_gpio_port *port;\n+\tconst struct tegra_gpio_port_soc *port;\n \n \tport = tegra186_gpio_get_port(gpio, &pin);\n \tif (!port)\n@@ -206,39 +219,10 @@ static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,\n \twritel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);\n }\n \n-static int tegra186_gpio_of_xlate(struct gpio_chip *chip,\n-\t\t\t\t const struct of_phandle_args *spec,\n-\t\t\t\t u32 *flags)\n-{\n-\tstruct tegra_gpio *gpio = gpiochip_get_data(chip);\n-\tunsigned int port, pin, i, offset = 0;\n-\n-\tif (WARN_ON(chip->of_gpio_n_cells < 2))\n-\t\treturn -EINVAL;\n-\n-\tif (WARN_ON(spec->args_count < chip->of_gpio_n_cells))\n-\t\treturn -EINVAL;\n-\n-\tport = spec->args[0] / 8;\n-\tpin = spec->args[0] % 8;\n-\n-\tif (port >= gpio->soc->num_ports) {\n-\t\tdev_err(chip->parent, \"invalid port number: %u\\n\", port);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tfor (i = 0; i < port; i++)\n-\t\toffset += gpio->soc->ports[i].pins;\n-\n-\tif (flags)\n-\t\t*flags = spec->args[1];\n-\n-\treturn offset + pin;\n-}\n-\n static void tegra186_irq_ack(struct irq_data *data)\n {\n-\tstruct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);\n+\tstruct gpio_chip *chip = irq_data_get_irq_chip_data(data);\n+\tstruct tegra_gpio *gpio = gpiochip_get_data(chip);\n \tvoid __iomem *base;\n \n \tbase = tegra186_gpio_get_base(gpio, data->hwirq);\n@@ -250,7 +234,8 @@ static void tegra186_irq_ack(struct irq_data *data)\n \n static void tegra186_irq_mask(struct irq_data *data)\n {\n-\tstruct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);\n+\tstruct gpio_chip *chip = irq_data_get_irq_chip_data(data);\n+\tstruct tegra_gpio *gpio = gpiochip_get_data(chip);\n \tvoid __iomem *base;\n \tu32 value;\n \n@@ -265,7 +250,8 @@ static void tegra186_irq_mask(struct irq_data *data)\n \n static void tegra186_irq_unmask(struct irq_data *data)\n {\n-\tstruct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);\n+\tstruct gpio_chip *chip = irq_data_get_irq_chip_data(data);\n+\tstruct tegra_gpio *gpio = gpiochip_get_data(chip);\n \tvoid __iomem *base;\n \tu32 value;\n \n@@ -280,7 +266,8 @@ static void tegra186_irq_unmask(struct irq_data *data)\n \n static int tegra186_irq_set_type(struct irq_data *data, unsigned int flow)\n {\n-\tstruct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);\n+\tstruct gpio_chip *chip = irq_data_get_irq_chip_data(data);\n+\tstruct tegra_gpio *gpio = gpiochip_get_data(chip);\n \tvoid __iomem *base;\n \tu32 value;\n \n@@ -332,76 +319,22 @@ static int tegra186_irq_set_type(struct irq_data *data, unsigned int flow)\n \treturn 0;\n }\n \n-static void tegra186_gpio_irq(struct irq_desc *desc)\n-{\n-\tstruct tegra_gpio *gpio = irq_desc_get_handler_data(desc);\n-\tstruct irq_domain *domain = gpio->gpio.irq.domain;\n-\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n-\tunsigned int parent = irq_desc_get_irq(desc);\n-\tunsigned int i, offset = 0;\n-\n-\tchained_irq_enter(chip, desc);\n-\n-\tfor (i = 0; i < gpio->soc->num_ports; i++) {\n-\t\tconst struct tegra_gpio_port *port = &gpio->soc->ports[i];\n-\t\tvoid __iomem *base = gpio->base + port->offset;\n-\t\tunsigned int pin, irq;\n-\t\tunsigned long value;\n-\n-\t\t/* skip ports that are not associated with this controller */\n-\t\tif (parent != gpio->irq[port->irq])\n-\t\t\tgoto skip;\n-\n-\t\tvalue = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));\n-\n-\t\tfor_each_set_bit(pin, &value, port->pins) {\n-\t\t\tirq = irq_find_mapping(domain, offset + pin);\n-\t\t\tif (WARN_ON(irq == 0))\n-\t\t\t\tcontinue;\n-\n-\t\t\tgeneric_handle_irq(irq);\n-\t\t}\n-\n-skip:\n-\t\toffset += port->pins;\n-\t}\n-\n-\tchained_irq_exit(chip, desc);\n-}\n-\n-static int tegra186_gpio_irq_domain_xlate(struct irq_domain *domain,\n-\t\t\t\t\t struct device_node *np,\n-\t\t\t\t\t const u32 *spec, unsigned int size,\n-\t\t\t\t\t unsigned long *hwirq,\n-\t\t\t\t\t unsigned int *type)\n+static void tegra186_gpio_update_bank(struct gpio_bank *bank)\n {\n-\tstruct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);\n-\tunsigned int port, pin, i, offset = 0;\n-\n-\tif (size < 2)\n-\t\treturn -EINVAL;\n-\n-\tport = spec[0] / 8;\n-\tpin = spec[0] % 8;\n-\n-\tif (port >= gpio->soc->num_ports) {\n-\t\tdev_err(gpio->gpio.parent, \"invalid port number: %u\\n\", port);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tfor (i = 0; i < port; i++)\n-\t\toffset += gpio->soc->ports[i].pins;\n+\tstruct tegra_gpio_port *port = to_tegra_gpio_port(bank);\n+\tstruct tegra_gpio *gpio = gpiochip_get_data(bank->chip);\n+\tvoid __iomem *base = gpio->base + port->offset;\n+\tu32 value;\n \n-\t*type = spec[1] & IRQ_TYPE_SENSE_MASK;\n-\t*hwirq = offset + pin;\n+\tvalue = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));\n \n-\treturn 0;\n+\tbank->pending[0] = value;\n }\n \n static const struct irq_domain_ops tegra186_gpio_irq_domain_ops = {\n \t.map = gpiochip_irq_map,\n \t.unmap = gpiochip_irq_unmap,\n-\t.xlate = tegra186_gpio_irq_domain_xlate,\n+\t.xlate = gpio_banked_irq_domain_xlate,\n };\n \n static struct lock_class_key tegra186_gpio_lock_class;\n@@ -420,6 +353,7 @@ static int tegra186_gpio_probe(struct platform_device *pdev)\n \t\treturn -ENOMEM;\n \n \tgpio->soc = of_device_get_match_data(&pdev->dev);\n+\tirq = &gpio->gpio.irq;\n \n \tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"gpio\");\n \tgpio->base = devm_ioremap_resource(&pdev->dev, res);\n@@ -430,21 +364,47 @@ static int tegra186_gpio_probe(struct platform_device *pdev)\n \tif (err < 0)\n \t\treturn err;\n \n-\tgpio->num_irq = err;\n+\tirq->num_parents = err;\n \n-\tgpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),\n-\t\t\t\t GFP_KERNEL);\n-\tif (!gpio->irq)\n+\tirq->parents = devm_kcalloc(&pdev->dev, irq->num_parents,\n+\t\t\t\t sizeof(*irq->parents), GFP_KERNEL);\n+\tif (!irq->parents)\n \t\treturn -ENOMEM;\n \n-\tfor (i = 0; i < gpio->num_irq; i++) {\n+\tfor (i = 0; i < irq->num_parents; i++) {\n \t\terr = platform_get_irq(pdev, i);\n \t\tif (err < 0)\n \t\t\treturn err;\n \n-\t\tgpio->irq[i] = err;\n+\t\tirq->parents[i] = err;\n \t}\n \n+\tgpio->ports = devm_kcalloc(&pdev->dev, gpio->soc->num_ports,\n+\t\t\t\t sizeof(struct tegra_gpio_port),\n+\t\t\t\t GFP_KERNEL);\n+\tif (!gpio->ports)\n+\t\treturn -ENOMEM;\n+\n+\tgpio->gpio.banks = devm_kcalloc(&pdev->dev, gpio->soc->num_ports,\n+\t\t\t\t\tsizeof(struct gpio_bank *),\n+\t\t\t\t\tGFP_KERNEL);\n+\tif (!gpio->gpio.banks)\n+\t\treturn -ENOMEM;\n+\n+\tfor (i = 0; i < gpio->soc->num_ports; i++) {\n+\t\tconst struct tegra_gpio_port_soc *soc = &gpio->soc->ports[i];\n+\t\tstruct tegra_gpio_port *port = &gpio->ports[i];\n+\n+\t\tgpio->gpio.banks[i] = &port->bank;\n+\t\tport->bank.parent_irq = soc->irq;\n+\t\tport->bank.num_pins = soc->pins;\n+\n+\t\tport->offset = soc->offset;\n+\t\tport->name = soc->name;\n+\t}\n+\n+\tgpio->gpio.num_banks = gpio->soc->num_ports;\n+\n \tgpio->gpio.label = gpio->soc->name;\n \tgpio->gpio.parent = &pdev->dev;\n \n@@ -465,7 +425,7 @@ static int tegra186_gpio_probe(struct platform_device *pdev)\n \t\treturn -ENOMEM;\n \n \tfor (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {\n-\t\tconst struct tegra_gpio_port *port = &gpio->soc->ports[i];\n+\t\tconst struct tegra_gpio_port_soc *port = &gpio->soc->ports[i];\n \t\tchar *name;\n \n \t\tfor (j = 0; j < port->pins; j++) {\n@@ -484,7 +444,11 @@ static int tegra186_gpio_probe(struct platform_device *pdev)\n \n \tgpio->gpio.of_node = pdev->dev.of_node;\n \tgpio->gpio.of_gpio_n_cells = 2;\n-\tgpio->gpio.of_xlate = tegra186_gpio_of_xlate;\n+\tgpio->gpio.of_gpio_bank_shift = 3;\n+\tgpio->gpio.of_gpio_bank_mask = 0x1fffffff;\n+\tgpio->gpio.of_gpio_pin_shift = 0;\n+\tgpio->gpio.of_gpio_pin_mask = 0x7;\n+\tgpio->gpio.of_xlate = of_gpio_banked_xlate;\n \n \tgpio->intc.name = pdev->dev.of_node->name;\n \tgpio->intc.irq_ack = tegra186_irq_ack;\n@@ -492,31 +456,14 @@ static int tegra186_gpio_probe(struct platform_device *pdev)\n \tgpio->intc.irq_unmask = tegra186_irq_unmask;\n \tgpio->intc.irq_set_type = tegra186_irq_set_type;\n \n-\tirq = &gpio->gpio.irq;\n \tirq->chip = &gpio->intc;\n \tirq->first = 0;\n \tirq->domain_ops = &tegra186_gpio_irq_domain_ops;\n \tirq->handler = handle_simple_irq;\n \tirq->lock_key = &tegra186_gpio_lock_class;\n \tirq->default_type = IRQ_TYPE_NONE;\n-\tirq->parent_handler = tegra186_gpio_irq;\n-\tirq->parent_handler_data = gpio;\n-\tirq->num_parents = gpio->num_irq;\n-\tirq->parents = gpio->irq;\n-\n-\tirq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,\n-\t\t\t\tsizeof(*irq->map), GFP_KERNEL);\n-\tif (!irq->map)\n-\t\treturn -ENOMEM;\n-\n-\tfor (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {\n-\t\tconst struct tegra_gpio_port *port = &gpio->soc->ports[i];\n-\n-\t\tfor (j = 0; j < port->pins; j++)\n-\t\t\tirq->map[offset + j] = irq->parents[port->irq];\n-\n-\t\toffset += port->pins;\n-\t}\n+\tirq->parent_handler = gpio_irq_chip_banked_handler;\n+\tirq->update_bank = tegra186_gpio_update_bank;\n \n \tplatform_set_drvdata(pdev, gpio);\n \n@@ -540,7 +487,7 @@ static int tegra186_gpio_remove(struct platform_device *pdev)\n \t\t.irq = controller,\t\t\t\t\\\n \t}\n \n-static const struct tegra_gpio_port tegra186_main_ports[] = {\n+static const struct tegra_gpio_port_soc tegra186_main_ports[] = {\n \tTEGRA_MAIN_GPIO_PORT( A, 0x2000, 7, 2),\n \tTEGRA_MAIN_GPIO_PORT( B, 0x3000, 7, 3),\n \tTEGRA_MAIN_GPIO_PORT( C, 0x3200, 7, 3),\n@@ -580,7 +527,7 @@ static const struct tegra_gpio_soc tegra186_main_soc = {\n \t\t.irq = controller,\t\t\t\t\\\n \t}\n \n-static const struct tegra_gpio_port tegra186_aon_ports[] = {\n+static const struct tegra_gpio_port_soc tegra186_aon_ports[] = {\n \tTEGRA_AON_GPIO_PORT( S, 0x0200, 5, 0),\n \tTEGRA_AON_GPIO_PORT( U, 0x0400, 6, 0),\n \tTEGRA_AON_GPIO_PORT( V, 0x0800, 8, 0),\n", "prefixes": [ "16/16" ] }