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GET /api/patches/808724/?format=api
{ "id": 808724, "url": "http://patchwork.ozlabs.org/api/patches/808724/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170901153535.30680-1-tklauser@distanz.ch/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170901153535.30680-1-tklauser@distanz.ch>", "list_archive_url": null, "date": "2017-09-01T15:35:35", "name": "[v7] nios2: Add Altera JTAG UART emulation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2a7c0cbe76734902b94db43b224c3d77a4f5b956", "submitter": { "id": 2451, "url": "http://patchwork.ozlabs.org/api/people/2451/?format=api", "name": "Tobias Klauser", "email": "tklauser@distanz.ch" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170901153535.30680-1-tklauser@distanz.ch/mbox/", "series": [ { "id": 1048, "url": "http://patchwork.ozlabs.org/api/series/1048/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1048", "date": "2017-09-01T15:35:35", "name": "[v7] nios2: Add Altera JTAG UART emulation", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/1048/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808724/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808724/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xkNgv4GnYz9t1t\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 2 Sep 2017 01:38:51 +1000 (AEST)", "from localhost ([::1]:46293 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dno1x-0006VN-Jw\n\tfor incoming@patchwork.ozlabs.org; Fri, 01 Sep 2017 11:38:49 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:50572)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <tklauser@distanz.ch>) id 1dnnyy-0004Lz-UC\n\tfor qemu-devel@nongnu.org; Fri, 01 Sep 2017 11:35:52 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <tklauser@distanz.ch>) id 1dnnyv-00008Q-Go\n\tfor qemu-devel@nongnu.org; Fri, 01 Sep 2017 11:35:44 -0400", "from mail.zhinst.com ([212.126.164.98]:40554)\n\tby eggs.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <tklauser@distanz.ch>) id 1dnnyu-000051-Vl\n\tfor qemu-devel@nongnu.org; Fri, 01 Sep 2017 11:35:41 -0400", "from ziws08.zhinst.com ([10.42.0.7])\n\tby mail.zhinst.com (Kerio Connect 9.2.4) with ESMTP;\n\tFri, 1 Sep 2017 17:35:35 +0200" ], "From": "Tobias Klauser <tklauser@distanz.ch>", "To": "qemu-devel@nongnu.org", "Date": "Fri, 1 Sep 2017 17:35:35 +0200", "Message-Id": "<20170901153535.30680-1-tklauser@distanz.ch>", "X-Mailer": "git-send-email 2.13.0", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "212.126.164.98", "Subject": "[Qemu-devel] [PATCH v7] nios2: Add Altera JTAG UART emulation", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Marek Vasut <marex@denx.de>, Paolo Bonzini <pbonzini@redhat.com>,\n\tJuro Bystricky <juro.bystricky@intel.com>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Juro Bystricky <juro.bystricky@intel.com>\n\nAdd the Altera JTAG UART model.\n\nHardware emulation based on:\nhttps://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf\n(Please see \"Register Map\" on page 65)\n\nSigned-off-by: Juro Bystricky <juro.bystricky@intel.com>\nAcked-by: Marek Vasut <marex@denx.de>\nTested-by: Tobias Klauser <tklauser@distanz.ch>\n[tk: updated to compile with latest qemu master]\nSigned-off-by: Tobias Klauser <tklauser@distanz.ch>\n---\n\nv7:\n - resending with changes needed to compile with latest qemu master\n\n default-configs/nios2-softmmu.mak | 1 +\n hw/char/Makefile.objs | 1 +\n hw/char/altera_juart.c | 286 ++++++++++++++++++++++++++++++++++++++\n include/hw/char/altera_juart.h | 46 ++++++\n 4 files changed, 334 insertions(+)\n create mode 100644 hw/char/altera_juart.c\n create mode 100644 include/hw/char/altera_juart.h", "diff": "diff --git a/default-configs/nios2-softmmu.mak b/default-configs/nios2-softmmu.mak\nindex 74dc70caaef0..61598465c11d 100644\n--- a/default-configs/nios2-softmmu.mak\n+++ b/default-configs/nios2-softmmu.mak\n@@ -4,3 +4,4 @@ CONFIG_NIOS2=y\n CONFIG_SERIAL=y\n CONFIG_PTIMER=y\n CONFIG_ALTERA_TIMER=y\n+CONFIG_ALTERA_JUART=y\ndiff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs\nindex 1bcd37e98d9c..adb0e3ebc36a 100644\n--- a/hw/char/Makefile.objs\n+++ b/hw/char/Makefile.objs\n@@ -28,6 +28,7 @@ common-obj-$(CONFIG_LM32) += lm32_juart.o\n common-obj-$(CONFIG_LM32) += lm32_uart.o\n common-obj-$(CONFIG_MILKYMIST) += milkymist-uart.o\n common-obj-$(CONFIG_SCLPCONSOLE) += sclpconsole.o sclpconsole-lm.o\n+common-obj-$(CONFIG_ALTERA_JUART) += altera_juart.o\n \n obj-$(CONFIG_VIRTIO) += virtio-serial-bus.o\n obj-$(CONFIG_TERMINAL3270) += terminal3270.o\ndiff --git a/hw/char/altera_juart.c b/hw/char/altera_juart.c\nnew file mode 100644\nindex 000000000000..66adbd261f4c\n--- /dev/null\n+++ b/hw/char/altera_juart.c\n@@ -0,0 +1,286 @@\n+/*\n+ * QEMU model of the Altera JTAG UART.\n+ *\n+ * Copyright (c) 2016-2017 Intel Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version\n+ * 2 of the License, or (at your option) any later version.\n+ *\n+ * You should have received a copy of the GNU General Public License along\n+ * with this program; if not, see <http://www.gnu.org/licenses/>.\n+ *\n+ * The Altera JTAG UART hardware registers are described in:\n+ * https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf\n+ * (In particular \"Register Map\" on page 65)\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"chardev/char-serial.h\"\n+#include \"hw/char/altera_juart.h\"\n+#include \"sysemu/sysemu.h\"\n+#include \"qemu/error-report.h\"\n+\n+/* Data register */\n+#define OFFSET_R_DATA 0\n+#define DATA_RVALID BIT(15)\n+#define DATA_RAVAIL 0xFFFF0000\n+\n+/* Control register */\n+#define OFFSET_R_CONTROL 4\n+#define CONTROL_RE BIT(0)\n+#define CONTROL_WE BIT(1)\n+#define CONTROL_RI BIT(8)\n+#define CONTROL_WI BIT(9)\n+#define CONTROL_AC BIT(10)\n+#define CONTROL_WSPACE 0xFFFF0000\n+\n+#define CONTROL_WMASK (CONTROL_RE | CONTROL_WE | CONTROL_AC)\n+\n+#define TYPE_ALTERA_JUART \"altera-juart\"\n+#define ALTERA_JUART(obj) \\\n+ OBJECT_CHECK(AlteraJUARTState, (obj), TYPE_ALTERA_JUART)\n+\n+/* Two registers 4 bytes wide each */\n+#define ALTERA_JTAG_UART_REGS_MEM_SIZE (2 * 4)\n+\n+/*\n+ * The JTAG UART core generates an interrupt when either of the individual\n+ * interrupt conditions is pending and enabled.\n+ */\n+static void altera_juart_update_irq(AlteraJUARTState *s)\n+{\n+ unsigned int irq;\n+\n+ irq = ((s->jcontrol & CONTROL_WE) && (s->jcontrol & CONTROL_WI)) ||\n+ ((s->jcontrol & CONTROL_RE) && (s->jcontrol & CONTROL_RI));\n+\n+ qemu_set_irq(s->irq, irq);\n+}\n+\n+static uint64_t altera_juart_read(void *opaque, hwaddr addr, unsigned int size)\n+{\n+ AlteraJUARTState *s = opaque;\n+ uint32_t r;\n+\n+ switch (addr) {\n+ case OFFSET_R_DATA:\n+ r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & (s->rx_fifo_size - 1)];\n+ if (s->rx_fifo_len) {\n+ s->rx_fifo_len--;\n+ qemu_chr_fe_accept_input(&s->chr);\n+ s->jdata = r | DATA_RVALID | (s->rx_fifo_len << 16);\n+ s->jcontrol |= CONTROL_RI;\n+ } else {\n+ s->jdata = 0;\n+ s->jcontrol &= ~CONTROL_RI;\n+ }\n+\n+ altera_juart_update_irq(s);\n+ return s->jdata;\n+\n+ case OFFSET_R_CONTROL:\n+ return s->jcontrol;\n+ }\n+\n+ return 0;\n+}\n+\n+static void altera_juart_write(void *opaque, hwaddr addr,\n+ uint64_t value, unsigned int size)\n+{\n+ AlteraJUARTState *s = opaque;\n+ unsigned char c;\n+\n+ switch (addr) {\n+ case OFFSET_R_DATA:\n+ c = value & 0xFF;\n+ s->jcontrol |= CONTROL_WI;\n+ s->jdata = c;\n+ qemu_chr_fe_write(&s->chr, &c, 1);\n+ altera_juart_update_irq(s);\n+ break;\n+\n+ case OFFSET_R_CONTROL:\n+ /* Only RE and WE are writable */\n+ value &= CONTROL_WMASK;\n+ s->jcontrol &= ~CONTROL_WMASK;\n+ s->jcontrol |= value;\n+\n+ /* Writing 1 to AC clears it to 0 */\n+ if (value & CONTROL_AC) {\n+ s->jcontrol &= ~CONTROL_AC;\n+ }\n+ altera_juart_update_irq(s);\n+ break;\n+ }\n+}\n+\n+static int altera_juart_can_receive(void *opaque)\n+{\n+ AlteraJUARTState *s = opaque;\n+ return s->rx_fifo_size - s->rx_fifo_len;\n+}\n+\n+static void altera_juart_receive(void *opaque, const uint8_t *buf, int size)\n+{\n+ int i;\n+ AlteraJUARTState *s = opaque;\n+\n+ for (i = 0; i < size; i++) {\n+ s->rx_fifo[s->rx_fifo_pos] = buf[i];\n+ s->rx_fifo_pos++;\n+ s->rx_fifo_pos &= (s->rx_fifo_size - 1);\n+ s->rx_fifo_len++;\n+ }\n+ s->jcontrol |= CONTROL_RI;\n+ altera_juart_update_irq(s);\n+}\n+\n+static void altera_juart_event(void *opaque, int event)\n+{\n+}\n+\n+static void altera_juart_reset(DeviceState *d)\n+{\n+ AlteraJUARTState *s = ALTERA_JUART(d);\n+\n+ s->jdata = 0;\n+\n+ /* The number of spaces available in the write FIFO */\n+ s->jcontrol = s->rx_fifo_size << 16;\n+ s->rx_fifo_pos = 0;\n+ s->rx_fifo_len = 0;\n+}\n+\n+static const MemoryRegionOps juart_ops = {\n+ .read = altera_juart_read,\n+ .write = altera_juart_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .valid = {\n+ .min_access_size = 4,\n+ .max_access_size = 4\n+ }\n+};\n+\n+static void altera_juart_init(Object *obj)\n+{\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);\n+ AlteraJUARTState *s = ALTERA_JUART(obj);\n+\n+ memory_region_init_io(&s->mmio, OBJECT(s), &juart_ops, s,\n+ TYPE_ALTERA_JUART, ALTERA_JTAG_UART_REGS_MEM_SIZE);\n+ sysbus_init_mmio(sbd, &s->mmio);\n+ sysbus_init_irq(sbd, &s->irq);\n+}\n+\n+void altera_juart_create(int channel, const hwaddr addr, qemu_irq irq, uint32_t fifo_sz)\n+{\n+ DeviceState *dev;\n+ SysBusDevice *bus;\n+ Chardev *chr;\n+ const char chr_name[] = \"juart\";\n+ char label[ARRAY_SIZE(chr_name) + 1];\n+\n+ dev = qdev_create(NULL, TYPE_ALTERA_JUART);\n+\n+ if (channel >= MAX_SERIAL_PORTS) {\n+ error_report(\"Only %d serial ports are supported by QEMU\",\n+ MAX_SERIAL_PORTS);\n+ exit(1);\n+ }\n+\n+ chr = serial_hds[channel];\n+ if (!chr) {\n+ snprintf(label, ARRAY_SIZE(label), \"%s%d\", chr_name, channel);\n+ chr = qemu_chr_new(label, \"null\");\n+ if (!chr) {\n+ error_report(\"Failed to assign serial port to altera %s\", label);\n+ exit(1);\n+ }\n+ }\n+ qdev_prop_set_chr(dev, \"chardev\", chr);\n+\n+ /*\n+ * FIFO size can be set from 8 to 32,768 bytes.\n+ * Only powers of two are allowed.\n+ */\n+ if (fifo_sz < 8 || fifo_sz > 32768 || (fifo_sz & ~(1 << ctz32(fifo_sz)))) {\n+ error_report(\"juart%d: Invalid FIFO size. [%u]\", channel, fifo_sz);\n+ exit(1);\n+ }\n+\n+ qdev_prop_set_uint32(dev, \"fifo-size\", fifo_sz);\n+ bus = SYS_BUS_DEVICE(dev);\n+ qdev_init_nofail(dev);\n+\n+ if (addr != (hwaddr)-1) {\n+ sysbus_mmio_map(bus, 0, addr);\n+ }\n+\n+ sysbus_connect_irq(bus, 0, irq);\n+}\n+\n+static const VMStateDescription vmstate_altera_juart = {\n+ .name = \"altera-juart\" ,\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_UINT32(jdata, AlteraJUARTState),\n+ VMSTATE_UINT32(jcontrol, AlteraJUARTState),\n+ VMSTATE_VBUFFER_UINT32(rx_fifo, AlteraJUARTState, 1, NULL, rx_fifo_size),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static void altera_juart_realize(DeviceState *dev, Error **errp)\n+{\n+ AlteraJUARTState *s = ALTERA_JUART(dev);\n+ qemu_chr_fe_set_handlers(&s->chr,\n+ altera_juart_can_receive,\n+ altera_juart_receive,\n+ altera_juart_event,\n+ NULL, s, NULL, true);\n+ s->rx_fifo = g_malloc(s->rx_fifo_size);\n+}\n+\n+static void altera_juart_unrealize(DeviceState *dev, Error **errp)\n+{\n+ AlteraJUARTState *s = ALTERA_JUART(dev);\n+ g_free(s->rx_fifo);\n+}\n+\n+static Property altera_juart_props[] = {\n+ DEFINE_PROP_CHR(\"chardev\", AlteraJUARTState, chr),\n+ DEFINE_PROP_UINT32(\"fifo-size\", AlteraJUARTState, rx_fifo_size,\n+ ALTERA_JUART_DEFAULT_FIFO_SIZE),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n+static void altera_juart_class_init(ObjectClass *oc, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(oc);\n+\n+ dc->realize = altera_juart_realize;\n+ dc->unrealize = altera_juart_unrealize;\n+ dc->props = altera_juart_props;\n+ dc->vmsd = &vmstate_altera_juart;\n+ dc->reset = altera_juart_reset;\n+ dc->desc = \"Altera JTAG UART\";\n+}\n+\n+static const TypeInfo altera_juart_info = {\n+ .name = TYPE_ALTERA_JUART,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(AlteraJUARTState),\n+ .instance_init = altera_juart_init,\n+ .class_init = altera_juart_class_init,\n+};\n+\n+static void altera_juart_register(void)\n+{\n+ type_register_static(&altera_juart_info);\n+}\n+\n+type_init(altera_juart_register)\ndiff --git a/include/hw/char/altera_juart.h b/include/hw/char/altera_juart.h\nnew file mode 100644\nindex 000000000000..fcf7a602523d\n--- /dev/null\n+++ b/include/hw/char/altera_juart.h\n@@ -0,0 +1,46 @@\n+/*\n+ * Altera JTAG UART emulation\n+ *\n+ * Copyright (c) 2016-2017 Intel Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version\n+ * 2 of the License, or (at your option) any later version.\n+ *\n+ * You should have received a copy of the GNU General Public License along\n+ * with this program; if not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef ALTERA_JUART_H\n+#define ALTERA_JUART_H\n+\n+#include \"chardev/char-fe.h\"\n+#include \"hw/sysbus.h\"\n+\n+/*\n+ * The read and write FIFO depths can be set from 8 to 32,768 bytes.\n+ * Only powers of two are allowed. A depth of 64 is generally optimal for\n+ * performance, and larger values are rarely necessary.\n+ */\n+\n+#define ALTERA_JUART_DEFAULT_FIFO_SIZE 64\n+\n+typedef struct AlteraJUARTState {\n+ SysBusDevice busdev;\n+ MemoryRegion mmio;\n+ CharBackend chr;\n+ qemu_irq irq;\n+\n+ unsigned int rx_fifo_size;\n+ unsigned int rx_fifo_pos;\n+ unsigned int rx_fifo_len;\n+ uint32_t jdata;\n+ uint32_t jcontrol;\n+ uint8_t *rx_fifo;\n+} AlteraJUARTState;\n+\n+void altera_juart_create(int channel, const hwaddr addr, qemu_irq irq,\n+ uint32_t fifo_size);\n+\n+#endif /* ALTERA_JUART_H */\n", "prefixes": [ "v7" ] }