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{ "id": 808683, "url": "http://patchwork.ozlabs.org/api/patches/808683/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20170901132425.GA32479@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170901132425.GA32479@arm.com>", "list_archive_url": null, "date": "2017-09-01T13:24:26", "name": "[ARM,AArch64] Testsuite framework changes and execution tests [Patch (8/8)]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c1c1ece191196c41f8c811e221726f35921c9170", "submitter": { "id": 69689, "url": "http://patchwork.ozlabs.org/api/people/69689/?format=api", "name": "Tamar Christina", "email": "Tamar.Christina@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20170901132425.GA32479@arm.com/mbox/", "series": [ { "id": 1028, "url": "http://patchwork.ozlabs.org/api/series/1028/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=1028", "date": "2017-09-01T13:24:26", "name": "[ARM,AArch64] Testsuite framework changes and execution tests [Patch (8/8)]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1028/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808683/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808683/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461293-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461293-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"hbsW2A/M\"; dkim-atps=neutral", "sourceware.org; auth=none", "spf=none (sender IP is )\n\tsmtp.mailfrom=Tamar.Christina@arm.com; " ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xkKjD0bFnz9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 1 Sep 2017 23:24:47 +1000 (AEST)", "(qmail 24770 invoked by alias); 1 Sep 2017 13:24:37 -0000", "(qmail 24756 invoked by uid 89); 1 Sep 2017 13:24:36 -0000", "from mail-eopbgr50062.outbound.protection.outlook.com (HELO\n\tEUR03-VE1-obe.outbound.protection.outlook.com) (40.107.5.62)\n\tby sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with\n\tESMTP; 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run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-25.5 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=", "X-HELO": "EUR03-VE1-obe.outbound.protection.outlook.com", "Date": "Fri, 1 Sep 2017 14:24:26 +0100", "From": "Tamar Christina <tamar.christina@arm.com>", "To": "gcc-patches@gcc.gnu.org", "Cc": "nd@arm.com, james.greenhalgh@arm.com, Richard.Earnshaw@arm.com,\n\tMarcus.Shawcroft@arm.com", "Subject": "[PATCH][GCC][ARM][AArch64] Testsuite framework changes and\n\texecution tests [Patch (8/8)]", "Message-ID": "<20170901132425.GA32479@arm.com>", "MIME-Version": "1.0", "Content-Type": "multipart/mixed; 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PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(102415395)(6040450)(601004)(2401047)(8121501046)(5005006)(3002001)(93006095)(93001095)(10201501046)(100000703101)(100105400095)(6055026)(6041248)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123564025)(20161123555025)(20161123560025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:HE1PR0802MB2316; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:HE1PR0802MB2316; ", "X-Forefront-PRVS": "0417A3FFD2", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(4630300001)(7370300001)(6009001)(39860400002)(189002)(53754006)(199003)(377424004)(3846002)(568964002)(86362001)(189998001)(55016002)(83506001)(1076002)(84326002)(5890100001)(6116002)(2906002)(110136004)(81156014)(81166006)(7350300001)(2476003)(8676002)(6916009)(7736002)(21086003)(25786009)(5000100001)(101416001)(4326008)(2351001)(106356001)(53936002)(54356999)(305945005)(50986999)(478600001)(4610100001)(5660300001)(42186005)(72206003)(68736007)(97736004)(36756003)(4001350100001)(33656002)(66066001)(105586002)(2361001)(18370500001)(2700100001);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR0802MB2316; H:arm.com;\n\tFPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: arm.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "arm.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Sep 2017 13:24:24.9899\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "HE1PR0802MB2316", "X-IsSubscribed": "yes" }, "content": "Hi All,\n\nThis patch enables the execution runs for Dot product and also\nadds the feature tests.\n\nThe ARMv8.2-a Dot Product instructions only support 8-bit\nelement vectorization.\n\nDot product is available from ARMv8.2-a and onwards.\n\nRegtested and bootstrapped on aarch64-none-elf and\narm-none-eabi and no issues.\n\nOk for trunk?\n\ngcc/testsuite\n2017-09-01 Tamar Christina <tamar.christina@arm.com>\n\n\t* lib/target-supports.exp\n\t(check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache): New.\n\t(check_effective_target_arm_v8_2a_dotprod_neon_ok): New.\n\t(add_options_for_arm_v8_2a_dotprod_neon): New.\n\t(check_effective_target_arm_v8_2a_dotprod_neon_hw): New.\n\t(check_effective_target_vect_sdot_qi): New.\n\t(check_effective_target_vect_udot_qi): New.\n\t* gcc.target/arm/simd/vdot-exec.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vdot-exec.c: New.\n\t* gcc/doc/sourcebuild.texi: Document arm_v8_2a_dotprod_neon.\n\n--", "diff": "diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi\nindex e6313dc031ef5b2b5a72180bccf1e876812efe48..bb6fe68a460dd6a699a76953e221028a15997001 100644\n--- a/gcc/doc/sourcebuild.texi\n+++ b/gcc/doc/sourcebuild.texi\n@@ -1678,6 +1678,17 @@ ARM target supports executing instructions from ARMv8.2 with the FP16\n extension. Some multilibs may be incompatible with these options.\n Implies arm_v8_2a_fp16_neon_ok and arm_v8_2a_fp16_scalar_hw.\n \n+@item arm_v8_2a_dotprod_neon_ok\n+@anchor{arm_v8_2a_dotprod_neon_ok}\n+ARM target supports options to generate instructions from ARMv8.2 with\n+the Dot Product extension. Some multilibs may be incompatible with these\n+options.\n+\n+@item arm_v8_2a_dotprod_neon_hw\n+ARM target supports executing instructions from ARMv8.2 with the Dot\n+Product extension. Some multilibs may be incompatible with these options.\n+Implies arm_v8_2a_dotprod_neon_ok.\n+\n @item arm_prefer_ldrd_strd\n ARM target prefers @code{LDRD} and @code{STRD} instructions over\n @code{LDM} and @code{STM} instructions.\n@@ -2269,6 +2280,11 @@ supported by the target; see the\n @ref{arm_v8_2a_fp16_neon_ok,,arm_v8_2a_fp16_neon_ok} effective target\n keyword.\n \n+@item arm_v8_2a_dotprod_neon\n+Add options for ARMv8.2 with Adv.SIMD Dot Product support, if this is\n+supported by the target; see the\n+@ref{arm_v8_2a_dotprod_neon_ok} effective target keyword.\n+\n @item bind_pic_locally\n Add the target-specific flags needed to enable functions to bind\n locally when using pic/PIC passes in the testsuite.\ndiff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-exec.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-exec.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..96d7f0ebc4fd89e966a17b2d7bb6b17e4b511c67\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-exec.c\n@@ -0,0 +1,75 @@\n+/* { dg-skip-if \"can't compile on arm.\" { arm*-*-* } } */\n+/* { dg-do run } */\n+/* { dg-additional-options \"-O3 -march=armv8.2-a+dotprod\" } */\n+/* { dg-require-effective-target arm_v8_2a_dotprod_neon_hw } */\n+\n+#include <arm_neon.h>\n+\n+extern void abort();\n+\n+#define P(n1,n2) n1,n1,n1,n1,n2,n2,n2,n2\n+#define ARR(nm, p, ty, ...) ty nm##_##p = { __VA_ARGS__ }\n+#define TEST(t1, t2, t3, f, r1, r2, n1, n2) \\\n+\tARR(f, x, t1, r1);\t\t \\\n+\tARR(f, y, t2, r2);\t\t \\\n+\tt3 f##_##r = {0};\t\t \\\n+\tf##_##r = f (f##_##r, f##_##x, f##_##y); \\\n+\tif (f##_##r[0] != n1 || f##_##r[1] != n2) \\\n+\t abort ();\n+\n+#define TEST_LANE(t1, t2, t3, f, r1, r2, n1, n2, n3, n4) \\\n+\tARR(f, x, t1, r1);\t\t \\\n+\tARR(f, y, t2, r2);\t\t \\\n+\tt3 f##_##rx = {0};\t\t \\\n+\tf##_##rx = f (f##_##rx, f##_##x, f##_##y, 0); \\\n+\tif (f##_##rx[0] != n1 || f##_##rx[1] != n2) \\\n+\t abort ();\t\t\t\t \\\n+\tt3 f##_##rx1 = {0};\t\t\t \\\n+\tf##_##rx1 = f (f##_##rx1, f##_##x, f##_##y, 1); \\\n+\tif (f##_##rx1[0] != n3 || f##_##rx1[1] != n4) \\\n+\t abort ();\n+\n+#define Px(n1,n2,n3,n4) P(n1,n2),P(n3,n4)\n+#define TEST_LANEQ(t1, t2, t3, f, r1, r2, n1, n2, n3, n4, n5, n6, n7, n8) \\\n+\tARR(f, x, t1, r1);\t\t \\\n+\tARR(f, y, t2, r2);\t\t \\\n+\tt3 f##_##rx = {0};\t\t \\\n+\tf##_##rx = f (f##_##rx, f##_##x, f##_##y, 0); \\\n+\tif (f##_##rx[0] != n1 || f##_##rx[1] != n2) \\\n+\t abort ();\t\t\t\t \\\n+\tt3 f##_##rx1 = {0};\t\t\t \\\n+\tf##_##rx1 = f (f##_##rx1, f##_##x, f##_##y, 1); \\\n+\tif (f##_##rx1[0] != n3 || f##_##rx1[1] != n4) \\\n+\t abort (); \\\n+\tt3 f##_##rx2 = {0};\t\t\t\t \\\n+\tf##_##rx2 = f (f##_##rx2, f##_##x, f##_##y, 2); \\\n+\tif (f##_##rx2[0] != n5 || f##_##rx2[1] != n6) \\\n+\t abort ();\t\t\t\t \\\n+\tt3 f##_##rx3 = {0};\t\t\t \\\n+\tf##_##rx3 = f (f##_##rx3, f##_##x, f##_##y, 3); \\\n+\tif (f##_##rx3[0] != n7 || f##_##rx3[1] != n8) \\\n+\t abort ();\n+\n+int\n+main()\n+{\n+ TEST (uint8x8_t, uint8x8_t, uint32x2_t, vdot_u32, P(1,2), P(2,3), 8, 24);\n+ TEST (int8x8_t, int8x8_t, int32x2_t, vdot_s32, P(1,2), P(-2,-3), -8, -24);\n+\n+ TEST (uint8x16_t, uint8x16_t, uint32x4_t, vdotq_u32, P(1,2), P(2,3), 8, 24);\n+ TEST (int8x16_t, int8x16_t, int32x4_t, vdotq_s32, P(1,2), P(-2,-3), -8, -24);\n+\n+ TEST_LANE (uint8x8_t, uint8x8_t, uint32x2_t, vdot_lane_u32, P(1,2), P(2,3), 8, 16, 12, 24);\n+ TEST_LANE (int8x8_t, int8x8_t, int32x2_t, vdot_lane_s32, P(1,2), P(-2,-3), -8, -16, -12, -24);\n+\n+ TEST_LANE (uint8x16_t, uint8x8_t, uint32x4_t, vdotq_lane_u32, P(1,2), P(2,3), 8, 16, 12, 24);\n+ TEST_LANE (int8x16_t, int8x8_t, int32x4_t, vdotq_lane_s32, P(1,2), P(-2,-3), -8, -16, -12, -24);\n+\n+ TEST_LANEQ (uint8x8_t, uint8x16_t, uint32x2_t, vdot_laneq_u32, P(1,2), Px(2,3,1,4), 8, 16, 12, 24, 4, 8, 16, 32);\n+ TEST_LANEQ (int8x8_t, int8x16_t, int32x2_t, vdot_laneq_s32, P(1,2), Px(-2,-3,-1,-4), -8, -16, -12, -24, -4, -8, -16, -32);\n+\n+ TEST_LANEQ (uint8x16_t, uint8x16_t, uint32x4_t, vdotq_laneq_u32, Px(1,2,2,1), Px(2,3,1,4), 8, 16, 12, 24, 4, 8, 16, 32);\n+ TEST_LANEQ (int8x16_t, int8x16_t, int32x4_t, vdotq_laneq_s32, Px(1,2,2,1), Px(-2,-3,-1,-4), -8, -16, -12, -24, -4, -8, -16, -32);\n+\n+ return 0;\n+}\ndiff --git a/gcc/testsuite/gcc.target/arm/simd/vdot-exec.c b/gcc/testsuite/gcc.target/arm/simd/vdot-exec.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..bb5fb114f9b3ac975b7ae9b7ef0f101a891c0c2d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/simd/vdot-exec.c\n@@ -0,0 +1,51 @@\n+/* { dg-do run } */\n+/* { dg-additional-options \"-O3\" } */\n+/* { dg-require-effective-target arm_v8_2a_dotprod_neon_hw } */\n+/* { dg-add-options arm_v8_2a_dotprod_neon } */\n+\n+#include <arm_neon.h>\n+\n+extern void abort();\n+\n+#define P(n1,n2) n1,n1,n1,n1,n2,n2,n2,n2\n+#define ARR(nm, p, ty, ...) ty nm##_##p = { __VA_ARGS__ }\n+#define TEST(t1, t2, t3, f, r1, r2, n1, n2) \\\n+\tARR(f, x, t1, r1);\t\t \\\n+\tARR(f, y, t2, r2);\t\t \\\n+\tt3 f##_##r = {0};\t\t \\\n+\tf##_##r = f (f##_##r, f##_##x, f##_##y); \\\n+\tif (f##_##r[0] != n1 || f##_##r[1] != n2) \\\n+\t abort ();\n+\n+#define P(n1,n2) n1,n1,n1,n1,n2,n2,n2,n2\n+#define ARR(nm, p, ty, ...) ty nm##_##p = { __VA_ARGS__ }\n+#define TEST_LANE(t1, t2, t3, f, r1, r2, n1, n2, n3, n4) \\\n+\tARR(f, x, t1, r1);\t\t \\\n+\tARR(f, y, t2, r2);\t\t \\\n+\tt3 f##_##rx = {0};\t\t \\\n+\tf##_##rx = f (f##_##rx, f##_##x, f##_##y, 0); \\\n+\tif (f##_##rx[0] != n1 || f##_##rx[1] != n2) \\\n+\t abort ();\t\t\t\t \\\n+\tt3 f##_##rx1 = {0};\t\t\t \\\n+\tf##_##rx1 = f (f##_##rx1, f##_##x, f##_##y, 1); \\\n+\tif (f##_##rx1[0] != n3 || f##_##rx1[1] != n4) \\\n+\t abort (); \\\n+\n+int\n+main()\n+{\n+ TEST (uint8x8_t, uint8x8_t, uint32x2_t, vdot_u32, P(1,2), P(2,3), 8, 24);\n+ TEST (int8x8_t, int8x8_t, int32x2_t, vdot_s32, P(1,2), P(-2,-3), -8, -24);\n+\n+ TEST (uint8x16_t, uint8x16_t, uint32x4_t, vdotq_u32, P(1,2), P(2,3), 8, 24);\n+ TEST (int8x16_t, int8x16_t, int32x4_t, vdotq_s32, P(1,2), P(-2,-3), -8, -24);\n+\n+ TEST_LANE (uint8x8_t, uint8x8_t, uint32x2_t, vdot_lane_u32, P(1,2), P(2,3), 8, 16, 12, 24);\n+\n+ TEST_LANE (int8x8_t, int8x8_t, int32x2_t, vdot_lane_s32, P(1,2), P(-2,-3), -8, -16, -12, -24);\n+\n+ TEST_LANE (uint8x16_t, uint8x8_t, uint32x4_t, vdotq_lane_u32, P(1,2), P(2,3), 8, 16, 12, 24);\n+ TEST_LANE (int8x16_t, int8x8_t, int32x4_t, vdotq_lane_s32, P(1,2), P(-2,-3), -8, -16, -12, -24);\n+\n+ return 0;\n+}\ndiff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp\nindex 5219fbf4671e83a6fa7affdab926115e8a23f9cb..77d75b06a74b7a5925b6616d1880a5ec598d9f7a 100644\n--- a/gcc/testsuite/lib/target-supports.exp\n+++ b/gcc/testsuite/lib/target-supports.exp\n@@ -4217,6 +4217,48 @@ proc check_effective_target_arm_v8_2a_fp16_neon_ok { } {\n \t\tcheck_effective_target_arm_v8_2a_fp16_neon_ok_nocache]\n }\n \n+# Return 1 if the target supports ARMv8.2 Adv.SIMD Dot Product\n+# instructions, 0 otherwise. The test is valid for ARM and for AArch64.\n+# Record the command line options needed.\n+\n+proc check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache { } {\n+ global et_arm_v8_2a_dotprod_neon_flags\n+ set et_arm_v8_2a_dotprod_neon_flags \"\"\n+\n+ if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {\n+ return 0;\n+ }\n+\n+ # Iterate through sets of options to find the compiler flags that\n+ # need to be added to the -march option.\n+ foreach flags {\"\" \"-mfloat-abi=softfp -mfpu=neon-fp-armv8\" \"-mfloat-abi=hard -mfpu=neon-fp-armv8\"} {\n+ if { [check_no_compiler_messages_nocache \\\n+ arm_v8_2a_dotprod_neon_ok object {\n+ #if !defined (__ARM_FEATURE_DOTPROD)\n+ #error \"__ARM_FEATURE_DOTPROD not defined\"\n+ #endif\n+ } \"$flags -march=armv8.2-a+dotprod\"] } {\n+ set et_arm_v8_2a_dotprod_neon_flags \"$flags -march=armv8.2-a+dotprod\"\n+ return 1\n+ }\n+ }\n+\n+ return 0;\n+}\n+\n+proc check_effective_target_arm_v8_2a_dotprod_neon_ok { } {\n+ return [check_cached_effective_target arm_v8_2a_dotprod_neon_ok \\\n+ check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache]\n+}\n+\n+proc add_options_for_arm_v8_2a_dotprod_neon { flags } {\n+ if { ! [check_effective_target_arm_v8_2a_dotprod_neon_ok] } {\n+ return \"$flags\"\n+ }\n+ global et_arm_v8_2a_dotprod_neon_flags\n+ return \"$flags $et_arm_v8_2a_dotprod_neon_flags\"\n+}\n+\n # Return 1 if the target supports executing ARMv8 NEON instructions, 0\n # otherwise.\n \n@@ -4354,6 +4396,42 @@ proc check_effective_target_arm_v8_2a_fp16_neon_hw { } {\n } [add_options_for_arm_v8_2a_fp16_neon \"\"]]\n }\n \n+# Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2\n+# with the Dot Product extension, 0 otherwise. The test is valid for ARM and for\n+# AArch64.\n+\n+proc check_effective_target_arm_v8_2a_dotprod_neon_hw { } {\n+ if { ![check_effective_target_arm_v8_2a_dotprod_neon_ok] } {\n+ return 0;\n+ }\n+ return [check_runtime arm_v8_2a_dotprod_neon_hw_available {\n+ #include \"arm_neon.h\"\n+ int\n+ main (void)\n+ {\n+\n+\t uint32x2_t results = {0,0};\n+\t uint8x8_t a = {1,1,1,1,2,2,2,2};\n+\t uint8x8_t b = {2,2,2,2,3,3,3,3};\n+\n+ #ifdef __ARM_ARCH_ISA_A64\n+ asm (\"udot %0.2s, %1.8b, %2.8b\"\n+ : \"=w\"(results)\n+ : \"w\"(a), \"w\"(b)\n+ : /* No clobbers. */);\n+\n+\t #elif __ARM_ARCH >= 8\n+ asm (\"vudot.u8 %P0, %P1, %P2\"\n+ : \"=w\"(results)\n+ : \"w\"(a), \"w\"(b)\n+ : /* No clobbers. */);\n+ #endif\n+\n+ return (results[0] == 8 && results[1] == 24) ? 1 : 0;\n+ }\n+ } [add_options_for_arm_v8_2a_dotprod_neon \"\"]]\n+}\n+\n # Return 1 if this is a ARM target with NEON enabled.\n \n proc check_effective_target_arm_neon { } {\n@@ -5619,6 +5697,8 @@ proc check_effective_target_vect_sdot_qi { } {\n } else {\n \tset et_vect_sdot_qi_saved($et_index) 0\n \tif { [istarget ia64-*-*]\n+\t || [istarget aarch64*-*-*]\n+\t || [istarget arm*-*-*]\n \t || ([istarget mips*-*-*]\n \t\t && [et-is-effective-target mips_msa]) } {\n set et_vect_udot_qi_saved 1\n@@ -5643,6 +5723,8 @@ proc check_effective_target_vect_udot_qi { } {\n } else {\n \tset et_vect_udot_qi_saved($et_index) 0\n if { [istarget powerpc*-*-*]\n+\t || [istarget aarch64*-*-*]\n+\t || [istarget arm*-*-*]\n \t || [istarget ia64-*-*]\n \t || ([istarget mips*-*-*]\n \t\t && [et-is-effective-target mips_msa]) } {\n@@ -7952,7 +8034,7 @@ proc check_effective_target_aarch64_tiny { } {\n # Create functions to check that the AArch64 assembler supports the\n # various architecture extensions via the .arch_extension pseudo-op.\n \n-foreach { aarch64_ext } { \"fp\" \"simd\" \"crypto\" \"crc\" \"lse\"} {\n+foreach { aarch64_ext } { \"fp\" \"simd\" \"crypto\" \"crc\" \"lse\" \"dotprod\"} {\n eval [string map [list FUNC $aarch64_ext] {\n \tproc check_effective_target_aarch64_asm_FUNC_ok { } {\n \t if { [istarget aarch64*-*-*] } {\n\n", "prefixes": [ "ARM", "AArch64" ] }