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GET /api/patches/808680/?format=api
{ "id": 808680, "url": "http://patchwork.ozlabs.org/api/patches/808680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20170901132253.GA32341@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170901132253.GA32341@arm.com>", "list_archive_url": null, "date": "2017-09-01T13:22:55", "name": "[AArch64] Dot Product NEON intrinsics [Patch (6/8)]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "367ebb27f9bb703b2b5351b2192dc7d1b4cd7815", "submitter": { "id": 69689, "url": "http://patchwork.ozlabs.org/api/people/69689/?format=api", "name": "Tamar Christina", "email": "Tamar.Christina@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20170901132253.GA32341@arm.com/mbox/", "series": [ { "id": 1025, "url": "http://patchwork.ozlabs.org/api/series/1025/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=1025", "date": "2017-09-01T13:22:55", "name": "[AArch64] Dot Product NEON intrinsics [Patch (6/8)]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1025/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808680/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808680/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461291-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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Christina <tamar.christina@arm.com>", "To": "gcc-patches@gcc.gnu.org", "Cc": "nd@arm.com, james.greenhalgh@arm.com, Richard.Earnshaw@arm.com,\n\tMarcus.Shawcroft@arm.com", "Subject": "[PATCH][GCC][AArch64] Dot Product NEON intrinsics [Patch (6/8)]", "Message-ID": "<20170901132253.GA32341@arm.com>", "MIME-Version": "1.0", "Content-Type": "multipart/mixed; boundary=\"fUYQa+Pmc3FrFX/N\"", "Content-Disposition": "inline", "User-Agent": "Mutt/1.5.24 (2015-08-30)", "X-ClientProxiedBy": "VI1P194CA0024.EURP194.PROD.OUTLOOK.COM\n\t(2603:10a6:800:be::34) To\n\tHE1PR0802MB2315.eurprd08.prod.outlook.com\n\t(2603:10a6:3:c4::21)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "d3c96355-d6cf-4d81-8df7-08d4f13c8e39", "X-MS-Office365-Filtering-HT": "Tenant", "X-Microsoft-Antispam": "UriScan:; BCL:0; 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"X-Exchange-Antispam-Report-Test": "UriScan:(180628864354917);", "X-Microsoft-Antispam-PRVS": "<HE1PR0802MB2315F5DCA91C28E031642B36FF920@HE1PR0802MB2315.eurprd08.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(102415395)(6040450)(601004)(2401047)(5005006)(8121501046)(93006095)(93001095)(3002001)(10201501046)(100000703101)(100105400095)(6055026)(6041248)(20161123564025)(20161123560025)(20161123555025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123558100)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:HE1PR0802MB2315; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:HE1PR0802MB2315; ", "X-Forefront-PRVS": "0417A3FFD2", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(4630300001)(7370300001)(6009001)(39860400002)(53754006)(189002)(377424004)(199003)(36756003)(33656002)(68736007)(478600001)(5660300001)(7350300001)(8676002)(86362001)(66066001)(5890100001)(6916009)(53936002)(2906002)(110136004)(55016002)(81156014)(305945005)(7736002)(1076002)(3846002)(42186005)(25786009)(6116002)(81166006)(189998001)(83506001)(4001350100001)(101416001)(50986999)(2476003)(54356999)(84326002)(105586002)(21086003)(2361001)(4610100001)(72206003)(106356001)(568964002)(2351001)(5000100001)(97736004)(4326008)(18370500001)(2700100001);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR0802MB2315; H:arm.com;\n\tFPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: arm.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "arm.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Sep 2017 13:22:54.7082\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "HE1PR0802MB2315", "X-IsSubscribed": "yes" }, "content": "Hi All,\n\nThis patch adds the Adv.SIMD intrinsics for Dot product.\n\nDot product is available from ARMv8.2-a and onwards.\n\nRegtested and bootstrapped on aarch64-none-elf and no issues.\n\nOk for trunk?\n\ngcc/\n2017-09-01 Tamar Christina <tamar.christina@arm.com>\n\n\t* config/aarch64/arm_neon.h (vdot_u32, vdotq_u32, vdot_s32, vdotq_s32): New.\n\t(vdot_lane_u32, vdot_laneq_u32, vdotq_lane_u32, vdotq_laneq_u32): New.\n\t(vdot_lane_s32, vdot_laneq_s32, vdotq_lane_s32, vdotq_laneq_s32): New.\n\ngcc/testsuite/\n2017-09-01 Tamar Christina <tamar.christina@arm.com>\n\n\t* gcc.target/aarch64/advsimd-intrinsics/vect-dot-qi.h: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vdot-compile.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vect-dot-s8.c: New.\n\t* gcc.target/aarch64/advsimd-intrinsics/vect-dot-u8.c: New.\n\n--", "diff": "diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h\nindex d7b30b0e5ee6144d543d354ce9978fe9c5d5ae73..96e740f91a7fb01d201c1badf08199a2a76cb483 100644\n--- a/gcc/config/aarch64/arm_neon.h\n+++ b/gcc/config/aarch64/arm_neon.h\n@@ -31541,6 +31541,99 @@ vminnmvq_f16 (float16x8_t __a)\n \n #pragma GCC pop_options\n \n+/* AdvSIMD Dot Product intrinsics. */\n+\n+#pragma GCC push_options\n+#pragma GCC target (\"arch=armv8.2-a+dotprod\")\n+\n+__extension__ extern __inline uint32x2_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdot_u32 (uint32x2_t __r, uint8x8_t __a, uint8x8_t __b)\n+{\n+ return __builtin_aarch64_udotv8qi_uuuu (__r, __a, __b);\n+}\n+\n+__extension__ extern __inline uint32x4_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdotq_u32 (uint32x4_t __r, uint8x16_t __a, uint8x16_t __b)\n+{\n+ return __builtin_aarch64_udotv16qi_uuuu (__r, __a, __b);\n+}\n+\n+__extension__ extern __inline int32x2_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdot_s32 (int32x2_t __r, int8x8_t __a, int8x8_t __b)\n+{\n+ return __builtin_aarch64_sdotv8qi (__r, __a, __b);\n+}\n+\n+__extension__ extern __inline int32x4_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdotq_s32 (int32x4_t __r, int8x16_t __a, int8x16_t __b)\n+{\n+ return __builtin_aarch64_sdotv16qi (__r, __a, __b);\n+}\n+\n+__extension__ extern __inline uint32x2_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdot_lane_u32 (uint32x2_t __r, uint8x8_t __a, uint8x8_t __b, const int __index)\n+{\n+ return __builtin_aarch64_udot_lanev8qi_uuuus (__r, __a, __b, __index);\n+}\n+\n+__extension__ extern __inline uint32x2_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdot_laneq_u32 (uint32x2_t __r, uint8x8_t __a, uint8x16_t __b,\n+\t\tconst int __index)\n+{\n+ return __builtin_aarch64_udot_laneqv8qi_uuuus (__r, __a, __b, __index);\n+}\n+\n+__extension__ extern __inline uint32x4_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdotq_lane_u32 (uint32x4_t __r, uint8x16_t __a, uint8x8_t __b,\n+\t\tconst int __index)\n+{\n+ return __builtin_aarch64_udot_lanev16qi_uuuus (__r, __a, __b, __index);\n+}\n+\n+__extension__ extern __inline uint32x4_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdotq_laneq_u32 (uint32x4_t __r, uint8x16_t __a, uint8x16_t __b,\n+\t\t const int __index)\n+{\n+ return __builtin_aarch64_udot_laneqv16qi_uuuus (__r, __a, __b, __index);\n+}\n+\n+__extension__ extern __inline int32x2_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdot_lane_s32 (int32x2_t __r, int8x8_t __a, int8x8_t __b, const int __index)\n+{\n+ return __builtin_aarch64_sdot_lanev8qi (__r, __a, __b, __index);\n+}\n+\n+__extension__ extern __inline int32x2_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdot_laneq_s32 (int32x2_t __r, int8x8_t __a, int8x16_t __b, const int __index)\n+{\n+ return __builtin_aarch64_sdot_laneqv8qi (__r, __a, __b, __index);\n+}\n+\n+__extension__ extern __inline int32x4_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdotq_lane_s32 (int32x4_t __r, int8x16_t __a, int8x8_t __b, const int __index)\n+{\n+ return __builtin_aarch64_sdot_lanev16qi (__r, __a, __b, __index);\n+}\n+\n+__extension__ extern __inline int32x4_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vdotq_laneq_s32 (int32x4_t __r, int8x16_t __a, int8x16_t __b, const int __index)\n+{\n+ return __builtin_aarch64_sdot_laneqv16qi (__r, __a, __b, __index);\n+}\n+#pragma GCC pop_options\n+\n #undef __aarch64_vget_lane_any\n \n #undef __aarch64_vdup_lane_any\ndiff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-compile.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-compile.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..f75503e1ef52a215b91538dad243b51d88b99c00\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-compile.c\n@@ -0,0 +1,74 @@\n+/* { dg-skip-if \"can't compile on arm.\" { arm*-*-* } } */\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-O3 -march=armv8.2-a+dotprod\" } */\n+\n+#include <arm_neon.h>\n+\n+/* Unsigned Dot Product instructions. */\n+\n+uint32x2_t ufoo (uint32x2_t r, uint8x8_t x, uint8x8_t y)\n+{\n+ return vdot_u32 (r, x, y);\n+}\n+\n+uint32x4_t ufooq (uint32x4_t r, uint8x16_t x, uint8x16_t y)\n+{\n+ return vdotq_u32 (r, x, y);\n+}\n+\n+uint32x2_t ufoo_lane (uint32x2_t r, uint8x8_t x, uint8x8_t y)\n+{\n+ return vdot_lane_u32 (r, x, y, 0);\n+}\n+\n+uint32x2_t ufoo_laneq (uint32x2_t r, uint8x8_t x, uint8x16_t y)\n+{\n+ return vdot_laneq_u32 (r, x, y, 0);\n+}\n+\n+uint32x4_t ufooq_lane (uint32x4_t r, uint8x16_t x, uint8x8_t y)\n+{\n+ return vdotq_lane_u32 (r, x, y, 0);\n+}\n+\n+uint32x4_t ufooq_laneq (uint32x4_t r, uint8x16_t x, uint8x16_t y)\n+{\n+ return vdotq_laneq_u32 (r, x, y, 0);\n+}\n+\n+/* Signed Dot Product instructions. */\n+\n+int32x2_t sfoo (int32x2_t r, int8x8_t x, int8x8_t y)\n+{\n+ return vdot_s32 (r, x, y);\n+}\n+\n+int32x4_t sfooq (int32x4_t r, int8x16_t x, int8x16_t y)\n+{\n+ return vdotq_s32 (r, x, y);\n+}\n+\n+int32x2_t sfoo_lane (int32x2_t r, int8x8_t x, int8x8_t y)\n+{\n+ return vdot_lane_s32 (r, x, y, 0);\n+}\n+\n+int32x2_t sfoo_laneq (int32x2_t r, int8x8_t x, int8x16_t y)\n+{\n+ return vdot_laneq_s32 (r, x, y, 0);\n+}\n+\n+int32x4_t sfooq_lane (int32x4_t r, int8x16_t x, int8x8_t y)\n+{\n+ return vdotq_lane_s32 (r, x, y, 0);\n+}\n+\n+int32x4_t sfooq_laneq (int32x4_t r, int8x16_t x, int8x16_t y)\n+{\n+ return vdotq_laneq_s32 (r, x, y, 0);\n+}\n+\n+/* { dg-final { scan-assembler-times {[us]dot\\tv[0-9]+\\.2s, v[0-9]+\\.8b, v[0-9]+\\.8b} 2 } } */\n+/* { dg-final { scan-assembler-times {[us]dot\\tv[0-9]+\\.2s, v[0-9]+\\.8b, v[0-9]+\\.4b\\[[0-9]+\\]} 4 } } */\n+/* { dg-final { scan-assembler-times {[us]dot\\tv[0-9]+\\.4s, v[0-9]+\\.16b, v[0-9]+\\.16b} 2 } } */\n+/* { dg-final { scan-assembler-times {[us]dot\\tv[0-9]+\\.4s, v[0-9]+\\.16b, v[0-9]+\\.4b\\[[0-9]+\\]} 4 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vect-dot-qi.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vect-dot-qi.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..90b00aff95cfef96d1963be17673dc191cc71169\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vect-dot-qi.h\n@@ -0,0 +1,15 @@\n+TYPE char X[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));\n+TYPE char Y[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));\n+\n+__attribute__ ((noinline)) int\n+foo1(int len) {\n+ int i;\n+ TYPE int result = 0;\n+ TYPE short prod;\n+\n+ for (i=0; i<len; i++) {\n+ prod = X[i] * Y[i];\n+ result += prod;\n+ }\n+ return result;\n+}\n\\ No newline at end of file\ndiff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vect-dot-s8.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vect-dot-s8.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..7c840ffc94f4adfb0d36cbd899958435235e20b2\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vect-dot-s8.c\n@@ -0,0 +1,9 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-O3 -march=armv8.2-a+dotprod\" } */\n+\n+#define N 64\n+#define TYPE signed\n+\n+#include \"vect-dot-qi.h\"\n+\n+/* { dg-final { scan-assembler-times {sdot\\tv[0-9]+\\.4s, v[0-9]+\\.16b, v[0-9]+\\.16b} 4 } } */\n\\ No newline at end of file\ndiff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vect-dot-u8.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vect-dot-u8.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..eff97a0c8ef312ba2db2b68b48cd0a8348719cd8\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vect-dot-u8.c\n@@ -0,0 +1,9 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-O3 -march=armv8.2-a+dotprod\" } */\n+\n+#define N 64\n+#define TYPE unsigned\n+\n+#include \"vect-dot-qi.h\"\n+\n+/* { dg-final { scan-assembler-times {udot\\tv[0-9]+\\.4s, v[0-9]+\\.16b, v[0-9]+\\.16b} 4 } } */\n\\ No newline at end of file\n\n", "prefixes": [ "AArch64" ] }