Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/808596/?format=api
{ "id": 808596, "url": "http://patchwork.ozlabs.org/api/patches/808596/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/20170901090455.32316-4-antoine.tenart@free-electrons.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170901090455.32316-4-antoine.tenart@free-electrons.com>", "list_archive_url": null, "date": "2017-09-01T09:04:54", "name": "[net-next,v2,3/4] net: mvpp2: use the GoP interrupt for link status changes", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "96b066fbd80f899b3ec2bacf0880cf9179e7e6d6", "submitter": { "id": 61603, "url": "http://patchwork.ozlabs.org/api/people/61603/?format=api", "name": "Antoine Tenart", "email": "antoine.tenart@free-electrons.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/20170901090455.32316-4-antoine.tenart@free-electrons.com/mbox/", "series": [ { "id": 979, "url": "http://patchwork.ozlabs.org/api/series/979/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=979", "date": "2017-09-01T09:04:53", "name": "net: mvpp2: optional PHYs and GoP link irq", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/979/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808596/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808596/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkCyn4BtDz9t2r\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 1 Sep 2017 19:06:09 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751880AbdIAJFz (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tFri, 1 Sep 2017 05:05:55 -0400", "from mail.free-electrons.com ([62.4.15.54]:45335 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751532AbdIAJFD (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Fri, 1 Sep 2017 05:05:03 -0400", "by mail.free-electrons.com (Postfix, from userid 110)\n\tid 263C0209B6; Fri, 1 Sep 2017 11:05:01 +0200 (CEST)", "from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id E412B2099C;\n\tFri, 1 Sep 2017 11:05:00 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0", "From": "Antoine Tenart <antoine.tenart@free-electrons.com>", "To": "davem@davemloft.net", "Cc": "Antoine Tenart <antoine.tenart@free-electrons.com>, andrew@lunn.ch,\n\tgregory.clement@free-electrons.com,\n\tthomas.petazzoni@free-electrons.com, nadavh@marvell.com,\n\tlinux@armlinux.org.uk, linux-kernel@vger.kernel.org,\n\tmw@semihalf.com, stefanc@marvell.com,\n\tmiquel.raynal@free-electrons.com, netdev@vger.kernel.org", "Subject": "[PATCH net-next v2 3/4] net: mvpp2: use the GoP interrupt for link\n\tstatus changes", "Date": "Fri, 1 Sep 2017 11:04:54 +0200", "Message-Id": "<20170901090455.32316-4-antoine.tenart@free-electrons.com>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170901090455.32316-1-antoine.tenart@free-electrons.com>", "References": "<20170901090455.32316-1-antoine.tenart@free-electrons.com>", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "This patch adds the GoP link interrupt support for when a port isn't\nconnected to a PHY. Because of this the phylib callback is never called\nand the link status management isn't done. This patch use the GoP link\ninterrupt in such cases to still have a minimal link management. Without\nthis patch ports not connected to a PHY cannot work.\n\nSigned-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>\nTested-by: Marcin Wojtas <mw@semihalf.com>\n---\n drivers/net/ethernet/marvell/mvpp2.c | 177 ++++++++++++++++++++++++++++++++++-\n 1 file changed, 172 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c\nindex b4d4759ddc25..dd0ee2691c86 100644\n--- a/drivers/net/ethernet/marvell/mvpp2.c\n+++ b/drivers/net/ethernet/marvell/mvpp2.c\n@@ -348,16 +348,24 @@\n #define MVPP2_GMAC_FLOW_CTRL_AUTONEG\tBIT(11)\n #define MVPP2_GMAC_CONFIG_FULL_DUPLEX\tBIT(12)\n #define MVPP2_GMAC_AN_DUPLEX_EN\t\tBIT(13)\n+#define MVPP2_GMAC_STATUS0\t\t\t0x10\n+#define MVPP2_GMAC_STATUS0_LINK_UP\t\tBIT(0)\n #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG\t\t0x1c\n #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS\t6\n #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK\t0x1fc0\n #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v)\t(((v) << 6) & \\\n \t\t\t\t\tMVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)\n+#define MVPP22_GMAC_INT_STAT\t\t\t0x20\n+#define MVPP22_GMAC_INT_STAT_LINK\t\tBIT(1)\n+#define MVPP22_GMAC_INT_MASK\t\t\t0x24\n+#define MVPP22_GMAC_INT_MASK_LINK_STAT\tBIT(1)\n #define MVPP22_GMAC_CTRL_4_REG\t\t\t0x90\n #define MVPP22_CTRL4_EXT_PIN_GMII_SEL\tBIT(0)\n #define MVPP22_CTRL4_DP_CLK_SEL\t\tBIT(5)\n #define MVPP22_CTRL4_SYNC_BYPASS_DIS\tBIT(6)\n #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE\tBIT(7)\n+#define MVPP22_GMAC_INT_SUM_MASK\t\t0xa4\n+#define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT\tBIT(1)\n \n /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,\n * relative to port->base.\n@@ -370,11 +378,19 @@\n #define MVPP22_XLG_CTRL1_REG\t\t\t0x104\n #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS\t0\n #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK\t0x1fff\n+#define MVPP22_XLG_STATUS\t\t\t0x10c\n+#define MVPP22_XLG_STATUS_LINK_UP\t\tBIT(0)\n+#define MVPP22_XLG_INT_STAT\t\t\t0x114\n+#define MVPP22_XLG_INT_STAT_LINK\t\tBIT(1)\n+#define MVPP22_XLG_INT_MASK\t\t\t0x118\n+#define MVPP22_XLG_INT_MASK_LINK\t\tBIT(1)\n #define MVPP22_XLG_CTRL3_REG\t\t\t0x11c\n #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK\t(7 << 13)\n #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC\t(0 << 13)\n #define MVPP22_XLG_CTRL3_MACMODESELECT_10G\t(1 << 13)\n-\n+#define MVPP22_XLG_EXT_INT_MASK\t\t\t0x15c\n+#define MVPP22_XLG_EXT_INT_MASK_XLG\t\tBIT(1)\n+#define MVPP22_XLG_EXT_INT_MASK_GIG\t\tBIT(2)\n #define MVPP22_XLG_CTRL4_REG\t\t\t0x184\n #define MVPP22_XLG_CTRL4_FWD_FC\t\tBIT(5)\n #define MVPP22_XLG_CTRL4_FWD_PFC\t\tBIT(6)\n@@ -837,6 +853,8 @@ struct mvpp2_port {\n \t */\n \tint gop_id;\n \n+\tint link_irq;\n+\n \tstruct mvpp2 *priv;\n \n \t/* Per-port registers' base address */\n@@ -4422,6 +4440,68 @@ static int mvpp22_gop_init(struct mvpp2_port *port)\n \treturn -EINVAL;\n }\n \n+static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)\n+{\n+\tu32 val;\n+\n+\tif (phy_interface_mode_is_rgmii(port->phy_interface) ||\n+\t port->phy_interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\t/* Enable the GMAC link status irq for this port */\n+\t\tval = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);\n+\t\tval |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;\n+\t\twritel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);\n+\t}\n+\n+\tif (port->gop_id == 0) {\n+\t\t/* Enable the XLG/GIG irqs for this port */\n+\t\tval = readl(port->base + MVPP22_XLG_EXT_INT_MASK);\n+\t\tif (port->phy_interface == PHY_INTERFACE_MODE_10GKR)\n+\t\t\tval |= MVPP22_XLG_EXT_INT_MASK_XLG;\n+\t\telse\n+\t\t\tval |= MVPP22_XLG_EXT_INT_MASK_GIG;\n+\t\twritel(val, port->base + MVPP22_XLG_EXT_INT_MASK);\n+\t}\n+}\n+\n+static void mvpp22_gop_mask_irq(struct mvpp2_port *port)\n+{\n+\tu32 val;\n+\n+\tif (port->gop_id == 0) {\n+\t\tval = readl(port->base + MVPP22_XLG_EXT_INT_MASK);\n+\t\tval &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |\n+\t\t MVPP22_XLG_EXT_INT_MASK_GIG);\n+\t\twritel(val, port->base + MVPP22_XLG_EXT_INT_MASK);\n+\t}\n+\n+\tif (phy_interface_mode_is_rgmii(port->phy_interface) ||\n+\t port->phy_interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\tval = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);\n+\t\tval &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;\n+\t\twritel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);\n+\t}\n+}\n+\n+static void mvpp22_gop_setup_irq(struct mvpp2_port *port)\n+{\n+\tu32 val;\n+\n+\tif (phy_interface_mode_is_rgmii(port->phy_interface) ||\n+\t port->phy_interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\tval = readl(port->base + MVPP22_GMAC_INT_MASK);\n+\t\tval |= MVPP22_GMAC_INT_MASK_LINK_STAT;\n+\t\twritel(val, port->base + MVPP22_GMAC_INT_MASK);\n+\t}\n+\n+\tif (port->gop_id == 0) {\n+\t\tval = readl(port->base + MVPP22_XLG_INT_MASK);\n+\t\tval |= MVPP22_XLG_INT_MASK_LINK;\n+\t\twritel(val, port->base + MVPP22_XLG_INT_MASK);\n+\t}\n+\n+\tmvpp22_gop_unmask_irq(port);\n+}\n+\n static int mvpp22_comphy_init(struct mvpp2_port *port)\n {\n \tenum phy_mode mode;\n@@ -5726,6 +5806,60 @@ static irqreturn_t mvpp2_isr(int irq, void *dev_id)\n \treturn IRQ_HANDLED;\n }\n \n+/* Per-port interrupt for link status changes */\n+static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)\n+{\n+\tstruct mvpp2_port *port = (struct mvpp2_port *)dev_id;\n+\tstruct net_device *dev = port->dev;\n+\tbool event = false, link = false;\n+\tu32 val;\n+\n+\tmvpp22_gop_mask_irq(port);\n+\n+\tif (port->gop_id == 0 &&\n+\t port->phy_interface == PHY_INTERFACE_MODE_10GKR) {\n+\t\tval = readl(port->base + MVPP22_XLG_INT_STAT);\n+\t\tif (val & MVPP22_XLG_INT_STAT_LINK) {\n+\t\t\tevent = true;\n+\t\t\tval = readl(port->base + MVPP22_XLG_STATUS);\n+\t\t\tif (val & MVPP22_XLG_STATUS_LINK_UP)\n+\t\t\t\tlink = true;\n+\t\t}\n+\t} else if (phy_interface_mode_is_rgmii(port->phy_interface) ||\n+\t\t port->phy_interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\tval = readl(port->base + MVPP22_GMAC_INT_STAT);\n+\t\tif (val & MVPP22_GMAC_INT_STAT_LINK) {\n+\t\t\tevent = true;\n+\t\t\tval = readl(port->base + MVPP2_GMAC_STATUS0);\n+\t\t\tif (val & MVPP2_GMAC_STATUS0_LINK_UP)\n+\t\t\t\tlink = true;\n+\t\t}\n+\t}\n+\n+\tif (!netif_running(dev) || !event)\n+\t\tgoto handled;\n+\n+\tif (link) {\n+\t\tmvpp2_interrupts_enable(port);\n+\n+\t\tmvpp2_egress_enable(port);\n+\t\tmvpp2_ingress_enable(port);\n+\t\tnetif_carrier_on(dev);\n+\t\tnetif_tx_wake_all_queues(dev);\n+\t} else {\n+\t\tnetif_tx_stop_all_queues(dev);\n+\t\tnetif_carrier_off(dev);\n+\t\tmvpp2_ingress_disable(port);\n+\t\tmvpp2_egress_disable(port);\n+\n+\t\tmvpp2_interrupts_disable(port);\n+\t}\n+\n+handled:\n+\tmvpp22_gop_unmask_irq(port);\n+\treturn IRQ_HANDLED;\n+}\n+\n static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port,\n \t\t\t\t struct phy_device *phydev)\n {\n@@ -5754,7 +5888,6 @@ static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port,\n \t\tval |= MVPP2_GMAC_CONFIG_MII_SPEED;\n \n \twritel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);\n-\n }\n \n /* Adjust link */\n@@ -6633,6 +6766,7 @@ static void mvpp2_irqs_deinit(struct mvpp2_port *port)\n static int mvpp2_open(struct net_device *dev)\n {\n \tstruct mvpp2_port *port = netdev_priv(dev);\n+\tstruct mvpp2 *priv = port->priv;\n \tunsigned char mac_bcast[ETH_ALEN] = {\n \t\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff };\n \tint err;\n@@ -6678,12 +6812,24 @@ static int mvpp2_open(struct net_device *dev)\n \t\tgoto err_cleanup_txqs;\n \t}\n \n+\tif (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) {\n+\t\terr = request_irq(port->link_irq, mvpp2_link_status_isr, 0,\n+\t\t\t\t dev->name, port);\n+\t\tif (err) {\n+\t\t\tnetdev_err(port->dev, \"cannot request link IRQ %d\\n\",\n+\t\t\t\t port->link_irq);\n+\t\t\tgoto err_free_irq;\n+\t\t}\n+\n+\t\tmvpp22_gop_setup_irq(port);\n+\t}\n+\n \t/* In default link is down */\n \tnetif_carrier_off(port->dev);\n \n \terr = mvpp2_phy_connect(port);\n \tif (err < 0)\n-\t\tgoto err_free_irq;\n+\t\tgoto err_free_link_irq;\n \n \t/* Unmask interrupts on all CPUs */\n \ton_each_cpu(mvpp2_interrupts_unmask, port, 1);\n@@ -6693,6 +6839,9 @@ static int mvpp2_open(struct net_device *dev)\n \n \treturn 0;\n \n+err_free_link_irq:\n+\tif (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq)\n+\t\tfree_irq(port->link_irq, port);\n err_free_irq:\n \tmvpp2_irqs_deinit(port);\n err_cleanup_txqs:\n@@ -6706,6 +6855,7 @@ static int mvpp2_stop(struct net_device *dev)\n {\n \tstruct mvpp2_port *port = netdev_priv(dev);\n \tstruct mvpp2_port_pcpu *port_pcpu;\n+\tstruct mvpp2 *priv = port->priv;\n \tint cpu;\n \n \tmvpp2_stop_dev(port);\n@@ -6715,6 +6865,9 @@ static int mvpp2_stop(struct net_device *dev)\n \ton_each_cpu(mvpp2_interrupts_mask, port, 1);\n \tmvpp2_shared_interrupt_mask_unmask(port, true);\n \n+\tif (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq)\n+\t\tfree_irq(port->link_irq, port);\n+\n \tmvpp2_irqs_deinit(port);\n \tif (!port->has_tx_irqs) {\n \t\tfor_each_present_cpu(cpu) {\n@@ -7413,6 +7566,15 @@ static int mvpp2_port_probe(struct platform_device *pdev,\n \tif (err)\n \t\tgoto err_free_netdev;\n \n+\tport->link_irq = of_irq_get_byname(port_node, \"link\");\n+\tif (port->link_irq == -EPROBE_DEFER) {\n+\t\terr = -EPROBE_DEFER;\n+\t\tgoto err_deinit_qvecs;\n+\t}\n+\tif (port->link_irq <= 0)\n+\t\t/* the link irq is optional */\n+\t\tport->link_irq = 0;\n+\n \tif (of_property_read_bool(port_node, \"marvell,loopback\"))\n \t\tport->flags |= MVPP2_F_LOOPBACK;\n \n@@ -7431,7 +7593,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,\n \t\tport->base = devm_ioremap_resource(&pdev->dev, res);\n \t\tif (IS_ERR(port->base)) {\n \t\t\terr = PTR_ERR(port->base);\n-\t\t\tgoto err_deinit_qvecs;\n+\t\t\tgoto err_free_irq;\n \t\t}\n \t} else {\n \t\tif (of_property_read_u32(port_node, \"gop-port-id\",\n@@ -7448,7 +7610,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,\n \tport->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);\n \tif (!port->stats) {\n \t\terr = -ENOMEM;\n-\t\tgoto err_deinit_qvecs;\n+\t\tgoto err_free_irq;\n \t}\n \n \tmvpp2_port_copy_mac_addr(dev, priv, port_node, &mac_from);\n@@ -7518,6 +7680,9 @@ static int mvpp2_port_probe(struct platform_device *pdev,\n \t\tfree_percpu(port->txqs[i]->pcpu);\n err_free_stats:\n \tfree_percpu(port->stats);\n+err_free_irq:\n+\tif (port->link_irq)\n+\t\tirq_dispose_mapping(port->link_irq);\n err_deinit_qvecs:\n \tmvpp2_queue_vectors_deinit(port);\n err_free_netdev:\n@@ -7538,6 +7703,8 @@ static void mvpp2_port_remove(struct mvpp2_port *port)\n \tfor (i = 0; i < port->ntxqs; i++)\n \t\tfree_percpu(port->txqs[i]->pcpu);\n \tmvpp2_queue_vectors_deinit(port);\n+\tif (port->link_irq)\n+\t\tirq_dispose_mapping(port->link_irq);\n \tfree_netdev(port->dev);\n }\n \n", "prefixes": [ "net-next", "v2", "3/4" ] }