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GET /api/patches/808572/?format=api
{ "id": 808572, "url": "http://patchwork.ozlabs.org/api/patches/808572/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1504252841-2445-11-git-send-email-bmeng.cn@gmail.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504252841-2445-11-git-send-email-bmeng.cn@gmail.com>", "list_archive_url": null, "date": "2017-09-01T08:00:41", "name": "[10/10] spi-nor: intel-spi: Fall back to use SW sequencer to erase", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "bf338be08b87ca5ab8c9ca969bbd4a60d5886f54", "submitter": { "id": 64981, "url": "http://patchwork.ozlabs.org/api/people/64981/?format=api", "name": "Bin Meng", "email": "bmeng.cn@gmail.com" }, "delegate": { "id": 63396, "url": "http://patchwork.ozlabs.org/api/users/63396/?format=api", "username": "cpitchen", "first_name": "Cyrille", "last_name": "Pitchen", "email": "cyrille.pitchen@atmel.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1504252841-2445-11-git-send-email-bmeng.cn@gmail.com/mbox/", "series": [ { "id": 969, "url": "http://patchwork.ozlabs.org/api/series/969/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=969", "date": "2017-09-01T08:00:33", "name": "spi-nor: intel-spi: Various fixes and enhancements", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/969/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808572/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808572/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; 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charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "According to the datasheet, the HW sequencer has a predefined list\nof opcodes, with only the erase opcode being programmable in LVSCC\nand UVSCC registers. If these registers don't contain a valid erase\nopcode (eg: BIOS does not program it), erase cannot be done using\nthe HW sequencer, even though the erase operation does not report\nany error, the flash remains not erased.\n\nIf such register setting is detected, let's fall back to use the SW\nsequencer to erase instead.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\n\n---\n\n drivers/mtd/spi-nor/intel-spi.c | 50 ++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 49 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c\nindex 5e7a389..f1e2c5f 100644\n--- a/drivers/mtd/spi-nor/intel-spi.c\n+++ b/drivers/mtd/spi-nor/intel-spi.c\n@@ -111,6 +111,13 @@\n #define BXT_FREG_NUM\t\t\t12\n #define BXT_PR_NUM\t\t\t6\n \n+#define LVSCC\t\t\t\t0xc4\n+#define UVSCC\t\t\t\t0xc8\n+#define ERASE_OPCODE_SHIFT\t\t8\n+#define ERASE_OPCODE_MASK\t\t(0xff << ERASE_OPCODE_SHIFT)\n+#define ERASE_64K_OPCODE_SHIFT\t\t16\n+#define ERASE_64K_OPCODE_MASK\t\t(0xff << ERASE_OPCODE_SHIFT)\n+\n #define INTEL_SPI_TIMEOUT\t\t5000 /* ms */\n #define INTEL_SPI_FIFO_SZ\t\t64\n \n@@ -127,6 +134,7 @@\n * @writeable: Is the chip writeable\n * @locked: Is SPI setting locked\n * @swseq_reg: Use SW sequencer in register reads/writes\n+ * @swseq_erase: Use SW sequencer in erase operation\n * @erase_64k: 64k erase supported\n * @opcodes: Opcodes which are supported. This are programmed by BIOS\n * before it locks down the controller.\n@@ -144,6 +152,7 @@ struct intel_spi {\n \tbool writeable;\n \tbool locked;\n \tbool swseq_reg;\n+\tbool swseq_erase;\n \tbool erase_64k;\n \tu8 opcodes[8];\n \tu8 preopcodes[2];\n@@ -191,6 +200,9 @@ static void intel_spi_dump_regs(struct intel_spi *ispi)\n \tif (ispi->info->type == INTEL_SPI_BYT)\n \t\tdev_dbg(ispi->dev, \"BCR=0x%08x\\n\", readl(ispi->base + BYT_BCR));\n \n+\tdev_dbg(ispi->dev, \"LVSCC=0x%08x\\n\", readl(ispi->base + LVSCC));\n+\tdev_dbg(ispi->dev, \"UVSCC=0x%08x\\n\", readl(ispi->base + UVSCC));\n+\n \tdev_dbg(ispi->dev, \"Protected regions:\\n\");\n \tfor (i = 0; i < ispi->pr_num; i++) {\n \t\tu32 base, limit;\n@@ -225,6 +237,8 @@ static void intel_spi_dump_regs(struct intel_spi *ispi)\n \n \tdev_dbg(ispi->dev, \"Using %cW sequencer for register access\\n\",\n \t\tispi->swseq_reg ? 'S' : 'H');\n+\tdev_dbg(ispi->dev, \"Using %cW sequencer for erase operation\\n\",\n+\t\tispi->swseq_erase ? 'S' : 'H');\n }\n \n /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */\n@@ -288,7 +302,7 @@ static int intel_spi_wait_sw_busy(struct intel_spi *ispi)\n \n static int intel_spi_init(struct intel_spi *ispi)\n {\n-\tu32 opmenu0, opmenu1, val;\n+\tu32 opmenu0, opmenu1, lvscc, uvscc, val;\n \tint i;\n \n \tswitch (ispi->info->type) {\n@@ -339,6 +353,24 @@ static int intel_spi_init(struct intel_spi *ispi)\n \twritel(val, ispi->base + HSFSTS_CTL);\n \n \t/*\n+\t * Determine whether erase operatoin should use HW or SW sequencer.\n+\t *\n+\t * The HW sequencer has a predefined list of opcodes, with only the\n+\t * erase opcode being programmable in LVSCC and UVSCC registers.\n+\t * If these registers don't contain a valid erase opcode, erase\n+\t * cannot be done using HW sequencer.\n+\t */\n+\tlvscc = readl(ispi->base + LVSCC);\n+\tuvscc = readl(ispi->base + UVSCC);\n+\tif (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK))\n+\t\tispi->swseq_erase = true;\n+\t/* SPI controller on Intel BXT supports 64K erase opcode */\n+\tif (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)\n+\t\tif (!(lvscc & ERASE_64K_OPCODE_MASK) ||\n+\t\t !(uvscc & ERASE_64K_OPCODE_MASK))\n+\t\t\tispi->erase_64k = false;\n+\n+\t/*\n \t * Some controllers can only do basic operations using hardware\n \t * sequencer. All other operations are supposed to be carried out\n \t * using software sequencer.\n@@ -665,6 +697,22 @@ static int intel_spi_erase(struct spi_nor *nor, loff_t offs)\n \t\terase_size = SZ_4K;\n \t}\n \n+\tif (ispi->swseq_erase) {\n+\t\twhile (len > 0) {\n+\t\t\twritel(offs, ispi->base + FADDR);\n+\n+\t\t\tret = intel_spi_sw_cycle(ispi, nor->erase_opcode,\n+\t\t\t\t\t\t 0, OPTYPE_WRITE_WITH_ADDR);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\n+\t\t\toffs += erase_size;\n+\t\t\tlen -= erase_size;\n+\t\t}\n+\n+\t\treturn 0;\n+\t}\n+\n \twhile (len > 0) {\n \t\twritel(offs, ispi->base + FADDR);\n \n", "prefixes": [ "10/10" ] }