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GET /api/patches/808570/?format=api
{ "id": 808570, "url": "http://patchwork.ozlabs.org/api/patches/808570/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1504252841-2445-8-git-send-email-bmeng.cn@gmail.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504252841-2445-8-git-send-email-bmeng.cn@gmail.com>", "list_archive_url": null, "date": "2017-09-01T08:00:38", "name": "[07/10] spi-nor: intel-spi: Don't assume OPMENU0/1 to be programmed by BIOS", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "1fe127625449c44c6038f0f99656f59f89920467", "submitter": { "id": 64981, "url": "http://patchwork.ozlabs.org/api/people/64981/?format=api", "name": "Bin Meng", "email": "bmeng.cn@gmail.com" }, "delegate": { "id": 63396, "url": "http://patchwork.ozlabs.org/api/users/63396/?format=api", "username": "cpitchen", "first_name": "Cyrille", "last_name": "Pitchen", "email": "cyrille.pitchen@atmel.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1504252841-2445-8-git-send-email-bmeng.cn@gmail.com/mbox/", "series": [ { "id": 969, "url": "http://patchwork.ozlabs.org/api/series/969/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=969", "date": "2017-09-01T08:00:33", "name": "spi-nor: intel-spi: Various fixes and enhancements", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/969/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808570/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808570/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; 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charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "At present the driver relies on valid OPMENU0/OPMENU1 register values\nthat are programmed by BIOS to function correctly. However in a real\nworld it's absolutely legitimate for a bootloader to leave these two\nregisters untouched. Intel FSP for Baytrail exactly does like this.\nWhen we are booting from any Intel FSP based bootloaders like U-Boot,\nthe driver refuses to work.\n\nWe can of course program various flash opcodes in the OPMENU0/OPMENU1\nregisters, and such workaround can be added in either the bootloader\ncodes, or the kernel driver itself.\n\nBut a graceful solution would be to update the kernel driver to remove\nsuch limitation of OPMENU0/1 register dependency. The SPI controller\nsettings are not locked under such configuration. So we can first check\nthe controller locking status, and if it is not locked that means the\ndriver job can be fulfilled by using a chosen OPMENU index to set up\nthe flash opcode every time.\n\nWhile we are here, the missing 'Atomic Cycle Sequence' handling in the\nSW sequencer codes is also added.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\n---\n\n drivers/mtd/spi-nor/intel-spi.c | 91 +++++++++++++++++++++++++++++------------\n 1 file changed, 65 insertions(+), 26 deletions(-)", "diff": "diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c\nindex 757b9f1..07146ab 100644\n--- a/drivers/mtd/spi-nor/intel-spi.c\n+++ b/drivers/mtd/spi-nor/intel-spi.c\n@@ -88,6 +88,11 @@\n #define OPMENU0\t\t\t\t0x08\n #define OPMENU1\t\t\t\t0x0c\n \n+#define OPTYPE_READ_NO_ADDR\t\t0\n+#define OPTYPE_WRITE_NO_ADDR\t\t1\n+#define OPTYPE_READ_WITH_ADDR\t\t2\n+#define OPTYPE_WRITE_WITH_ADDR\t\t3\n+\n /* CPU specifics */\n #define BYT_PR\t\t\t\t0x74\n #define BYT_SSFSTS_CTL\t\t\t0x90\n@@ -120,6 +125,7 @@\n * @nregions: Maximum number of regions\n * @pr_num: Maximum number of protected range registers\n * @writeable: Is the chip writeable\n+ * @locked: Is SPI setting locked\n * @swseq: Use SW sequencer in register reads/writes\n * @erase_64k: 64k erase supported\n * @opcodes: Opcodes which are supported. This are programmed by BIOS\n@@ -136,6 +142,7 @@ struct intel_spi {\n \tsize_t nregions;\n \tsize_t pr_num;\n \tbool writeable;\n+\tbool locked;\n \tbool swseq;\n \tbool erase_64k;\n \tu8 opcodes[8];\n@@ -343,23 +350,29 @@ static int intel_spi_init(struct intel_spi *ispi)\n \t\twritel(val, ispi->sregs + SSFSTS_CTL);\n \t}\n \n-\t/*\n-\t * BIOS programs allowed opcodes and then locks down the register.\n-\t * So read back what opcodes it decided to support. That's the set\n-\t * we are going to support as well.\n-\t */\n-\topmenu0 = readl(ispi->sregs + OPMENU0);\n-\topmenu1 = readl(ispi->sregs + OPMENU1);\n+\t/* Check controller's lock status */\n+\tval = readl(ispi->base + HSFSTS_CTL);\n+\tispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);\n \n-\tif (opmenu0 && opmenu1) {\n-\t\tfor (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {\n-\t\t\tispi->opcodes[i] = opmenu0 >> i * 8;\n-\t\t\tispi->opcodes[i + 4] = opmenu1 >> i * 8;\n-\t\t}\n+\tif (ispi->locked) {\n+\t\t/*\n+\t\t * BIOS programs allowed opcodes and then locks down the\n+\t\t * register. So read back what opcodes it decided to support.\n+\t\t * That's the set we are going to support as well.\n+\t\t */\n+\t\topmenu0 = readl(ispi->sregs + OPMENU0);\n+\t\topmenu1 = readl(ispi->sregs + OPMENU1);\n \n-\t\tval = readl(ispi->sregs + PREOP_OPTYPE);\n-\t\tispi->preopcodes[0] = val;\n-\t\tispi->preopcodes[1] = val >> 8;\n+\t\tif (opmenu0 && opmenu1) {\n+\t\t\tfor (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {\n+\t\t\t\tispi->opcodes[i] = opmenu0 >> i * 8;\n+\t\t\t\tispi->opcodes[i + 4] = opmenu1 >> i * 8;\n+\t\t\t}\n+\n+\t\t\tval = readl(ispi->sregs + PREOP_OPTYPE);\n+\t\t\tispi->preopcodes[0] = val;\n+\t\t\tispi->preopcodes[1] = val >> 8;\n+\t\t}\n \t}\n \n \tintel_spi_dump_regs(ispi);\n@@ -367,14 +380,25 @@ static int intel_spi_init(struct intel_spi *ispi)\n \treturn 0;\n }\n \n-static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode)\n+static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)\n {\n \tint i;\n+\tint preop;\n \n-\tfor (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)\n-\t\tif (ispi->opcodes[i] == opcode)\n-\t\t\treturn i;\n-\treturn -EINVAL;\n+\tif (ispi->locked) {\n+\t\tfor (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)\n+\t\t\tif (ispi->opcodes[i] == opcode)\n+\t\t\t\treturn i;\n+\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* The lock is off, so just use index 0 */\n+\twritel(opcode, ispi->sregs + OPMENU0);\n+\tpreop = readw(ispi->sregs + PREOP_OPTYPE);\n+\twritel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);\n+\n+\treturn 0;\n }\n \n static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)\n@@ -420,12 +444,14 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)\n \treturn 0;\n }\n \n-static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len)\n+static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len,\n+\t\t\t int optype)\n {\n \tu32 val = 0, status;\n+\tu16 preop;\n \tint ret;\n \n-\tret = intel_spi_opcode_index(ispi, opcode);\n+\tret = intel_spi_opcode_index(ispi, opcode, optype);\n \tif (ret < 0)\n \t\treturn ret;\n \n@@ -438,6 +464,12 @@ static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len)\n \tval |= ret << SSFSTS_CTL_COP_SHIFT;\n \tval |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;\n \tval |= SSFSTS_CTL_SCGO;\n+\tpreop = readw(ispi->sregs + PREOP_OPTYPE);\n+\tif (preop) {\n+\t\tval |= SSFSTS_CTL_ACS;\n+\t\tif (preop >> 8)\n+\t\t\tval |= SSFSTS_CTL_SPOP;\n+\t}\n \twritel(val, ispi->sregs + SSFSTS_CTL);\n \n \tret = intel_spi_wait_sw_busy(ispi);\n@@ -462,7 +494,8 @@ static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)\n \twritel(0, ispi->base + FADDR);\n \n \tif (ispi->swseq)\n-\t\tret = intel_spi_sw_cycle(ispi, opcode, len);\n+\t\tret = intel_spi_sw_cycle(ispi, opcode, len,\n+\t\t\t\t\t OPTYPE_READ_NO_ADDR);\n \telse\n \t\tret = intel_spi_hw_cycle(ispi, opcode, len);\n \n@@ -479,10 +512,15 @@ static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)\n \n \t/*\n \t * This is handled with atomic operation and preop code in Intel\n-\t * controller so skip it here now.\n+\t * controller so skip it here now. If the controller is not locked,\n+\t * program the opcode to the PREOP register for later use.\n \t */\n-\tif (opcode == SPINOR_OP_WREN)\n+\tif (opcode == SPINOR_OP_WREN) {\n+\t\tif (!ispi->locked)\n+\t\t\twritel(opcode, ispi->sregs + PREOP_OPTYPE);\n+\n \t\treturn 0;\n+\t}\n \n \twritel(0, ispi->base + FADDR);\n \n@@ -492,7 +530,8 @@ static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)\n \t\treturn ret;\n \n \tif (ispi->swseq)\n-\t\treturn intel_spi_sw_cycle(ispi, opcode, len);\n+\t\treturn intel_spi_sw_cycle(ispi, opcode, len,\n+\t\t\t\t\t OPTYPE_WRITE_NO_ADDR);\n \treturn intel_spi_hw_cycle(ispi, opcode, len);\n }\n \n", "prefixes": [ "07/10" ] }