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GET /api/patches/808567/?format=api
{ "id": 808567, "url": "http://patchwork.ozlabs.org/api/patches/808567/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1504252841-2445-6-git-send-email-bmeng.cn@gmail.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504252841-2445-6-git-send-email-bmeng.cn@gmail.com>", "list_archive_url": null, "date": "2017-09-01T08:00:36", "name": "[05/10] spi-nor: intel-spi: Use SW sequencer for BYT/LPT", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "202f0a2a45a7005affc8ca590f1c61f7495770f7", "submitter": { "id": 64981, "url": "http://patchwork.ozlabs.org/api/people/64981/?format=api", "name": "Bin Meng", "email": "bmeng.cn@gmail.com" }, "delegate": { "id": 63396, "url": "http://patchwork.ozlabs.org/api/users/63396/?format=api", "username": "cpitchen", "first_name": "Cyrille", "last_name": "Pitchen", "email": "cyrille.pitchen@atmel.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1504252841-2445-6-git-send-email-bmeng.cn@gmail.com/mbox/", "series": [ { "id": 969, "url": "http://patchwork.ozlabs.org/api/series/969/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=969", "date": "2017-09-01T08:00:33", "name": "spi-nor: intel-spi: Various fixes and enhancements", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/969/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808567/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808567/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; 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charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "Baytrail/Lynx Point SPI controller's HW sequencer only supports basic\noperations. This is determined by the chipset design, however current\ncodes try to use register values in OPMENU0/OPMENU1 to see whether SW\nsequencer should be used, which is wrong. In fact OPMENU0/OPMENU1 can\nremain unprogrammed by some bootloaders.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\n---\n\n drivers/mtd/spi-nor/intel-spi.c | 30 +++++++++++++++---------------\n 1 file changed, 15 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c\nindex c4a9de6..d0237fe 100644\n--- a/drivers/mtd/spi-nor/intel-spi.c\n+++ b/drivers/mtd/spi-nor/intel-spi.c\n@@ -290,6 +290,7 @@ static int intel_spi_init(struct intel_spi *ispi)\n \t\tispi->pregs = ispi->base + BYT_PR;\n \t\tispi->nregions = BYT_FREG_NUM;\n \t\tispi->pr_num = BYT_PR_NUM;\n+\t\tispi->swseq = true;\n \n \t\tif (writeable) {\n \t\t\t/* Disable write protection */\n@@ -310,6 +311,7 @@ static int intel_spi_init(struct intel_spi *ispi)\n \t\tispi->pregs = ispi->base + LPT_PR;\n \t\tispi->nregions = LPT_FREG_NUM;\n \t\tispi->pr_num = LPT_PR_NUM;\n+\t\tispi->swseq = true;\n \t\tbreak;\n \n \tcase INTEL_SPI_BXT:\n@@ -324,12 +326,24 @@ static int intel_spi_init(struct intel_spi *ispi)\n \t\treturn -EINVAL;\n \t}\n \n-\t/* Disable #SMI generation */\n+\t/* Disable #SMI generation from HW sequencer */\n \tval = readl(ispi->base + HSFSTS_CTL);\n \tval &= ~HSFSTS_CTL_FSMIE;\n \twritel(val, ispi->base + HSFSTS_CTL);\n \n \t/*\n+\t * Some controllers can only do basic operations using hardware\n+\t * sequencer. All other operations are supposed to be carried out\n+\t * using software sequencer.\n+\t */\n+\tif (ispi->swseq) {\n+\t\t/* Disable #SMI generation from SW sequencer */\n+\t\tval = readl(ispi->sregs + SSFSTS_CTL);\n+\t\tval &= ~SSFSTS_CTL_FSMIE;\n+\t\twritel(val, ispi->sregs + SSFSTS_CTL);\n+\t}\n+\n+\t/*\n \t * BIOS programs allowed opcodes and then locks down the register.\n \t * So read back what opcodes it decided to support. That's the set\n \t * we are going to support as well.\n@@ -337,13 +351,6 @@ static int intel_spi_init(struct intel_spi *ispi)\n \topmenu0 = readl(ispi->sregs + OPMENU0);\n \topmenu1 = readl(ispi->sregs + OPMENU1);\n \n-\t/*\n-\t * Some controllers can only do basic operations using hardware\n-\t * sequencer. All other operations are supposed to be carried out\n-\t * using software sequencer. If we find that BIOS has programmed\n-\t * opcodes for the software sequencer we use that over the hardware\n-\t * sequencer.\n-\t */\n \tif (opmenu0 && opmenu1) {\n \t\tfor (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {\n \t\t\tispi->opcodes[i] = opmenu0 >> i * 8;\n@@ -353,13 +360,6 @@ static int intel_spi_init(struct intel_spi *ispi)\n \t\tval = readl(ispi->sregs + PREOP_OPTYPE);\n \t\tispi->preopcodes[0] = val;\n \t\tispi->preopcodes[1] = val >> 8;\n-\n-\t\t/* Disable #SMI generation from SW sequencer */\n-\t\tval = readl(ispi->sregs + SSFSTS_CTL);\n-\t\tval &= ~SSFSTS_CTL_FSMIE;\n-\t\twritel(val, ispi->sregs + SSFSTS_CTL);\n-\n-\t\tispi->swseq = true;\n \t}\n \n \tintel_spi_dump_regs(ispi);\n", "prefixes": [ "05/10" ] }