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{
    "id": 808531,
    "url": "http://patchwork.ozlabs.org/api/patches/808531/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/kvm-ppc/patch/20170901061913.GB5644@fergus.ozlabs.ibm.com/",
    "project": {
        "id": 23,
        "url": "http://patchwork.ozlabs.org/api/projects/23/?format=api",
        "name": "KVM PowerPC development",
        "link_name": "kvm-ppc",
        "list_id": "kvm-ppc.vger.kernel.org",
        "list_email": "kvm-ppc@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170901061913.GB5644@fergus.ozlabs.ibm.com>",
    "list_archive_url": null,
    "date": "2017-09-01T06:19:13",
    "name": "KVM: PPC: Book3S HV: Handle unexpected interrupts better",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "bc72f0cc98c1c07454596b9dd6cca5d450e3328b",
    "submitter": {
        "id": 67079,
        "url": "http://patchwork.ozlabs.org/api/people/67079/?format=api",
        "name": "Paul Mackerras",
        "email": "paulus@ozlabs.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/kvm-ppc/patch/20170901061913.GB5644@fergus.ozlabs.ibm.com/mbox/",
    "series": [
        {
            "id": 952,
            "url": "http://patchwork.ozlabs.org/api/series/952/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/kvm-ppc/list/?series=952",
            "date": "2017-09-01T06:19:13",
            "name": "KVM: PPC: Book3S HV: Handle unexpected interrupts better",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/952/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/808531/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/808531/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<kvm-ppc-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
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        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1504246756; bh=ZE2z6zBZwV3LyWjXih688gyg+PuP1NqWFImtSbLXUVQ=;\n\th=Date:From:To:Subject:From;\n\tb=jgxTJdgY6kiuhYBxN2ifkNPmwLHg3WOD/PNNq2ATyY9XrdcwYTAvAjnycyGaPj5QC\n\txL4218TTAAQGjXEgQdYWUzNJfm4k5rFN4X6Gds0+ofpzIIceGUtTTCuxmZ1zY8uVg0\n\t2dqLK8yzQ4nnWdqa3pCagV94C+qsgCGJDydzM3v5zJyLwAbvYiLkyVsO/ziwA1wfwG\n\tAhh0dSCJYlJ40Q8Jw+l4HT0r5IHYAnidqI6hkQYgq+xCrxteqjtPCWUePyA5+WygtR\n\t+ypq6BnBf8/AGBnJFF+1c5m2BzS487abkDJaicDUItWGGk4OnuwCGCyxK9jeHPjlRb\n\tx9fKFs9vKkdyA==",
        "Date": "Fri, 1 Sep 2017 16:19:13 +1000",
        "From": "Paul Mackerras <paulus@ozlabs.org>",
        "To": "kvm-ppc@vger.kernel.org, kvm@vger.kernel.org",
        "Subject": "[PATCH] KVM: PPC: Book3S HV: Handle unexpected interrupts better",
        "Message-ID": "<20170901061913.GB5644@fergus.ozlabs.ibm.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=us-ascii",
        "Content-Disposition": "inline",
        "User-Agent": "Mutt/1.5.24 (2015-08-30)",
        "Sender": "kvm-ppc-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<kvm-ppc.vger.kernel.org>",
        "X-Mailing-List": "kvm-ppc@vger.kernel.org"
    },
    "content": "At present, if an interrupt (i.e. an exception or trap) occurs in the\ncode where KVM is switching the MMU to or from guest context, we jump\nto kvmppc_bad_host_intr, where we simply spin with interrupts disabled.\nIn this situation, it is hard to debug what happened because we get no\nindication as to which interrupt occurred or where.  Typically we get\na cascade of stall and soft lockup warnings from other CPUs.\n\nIn order to get more information for debugging, this adds code to\ncreate a stack frame on the emergency stack and save register values\nto it.  We start half-way down the emergency stack in order to give\nourselves some chance of being able to do a stack trace on secondary\nthreads that are already on the emergency stack.\n\nOn POWER7 or POWER8, we then just spin, as before, because we don't\nknow what state the MMU context is in or what other threads are doing,\nand we can't switch back to host context without coordinating with\nother threads.  On POWER9 we can do better; there we load up the host\nMMU context and jump to C code, which prints an oops message to the\nconsole and panics.\n\nSigned-off-by: Paul Mackerras <paulus@ozlabs.org>\n---\n arch/powerpc/kvm/book3s_hv_builtin.c    |   6 ++\n arch/powerpc/kvm/book3s_hv_rmhandlers.S | 132 +++++++++++++++++++++++++++++++-\n 2 files changed, 137 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c\nindex 90644db..2791922 100644\n--- a/arch/powerpc/kvm/book3s_hv_builtin.c\n+++ b/arch/powerpc/kvm/book3s_hv_builtin.c\n@@ -601,3 +601,9 @@ int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)\n \t\treturn xics_rm_h_eoi(vcpu, xirr);\n }\n #endif /* CONFIG_KVM_XICS */\n+\n+void kvmppc_bad_interrupt(struct pt_regs *regs)\n+{\n+\tdie(\"Bad interrupt in KVM entry/exit code\", regs, SIGABRT);\n+\tpanic(\"Bad KVM trap\");\n+}\ndiff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S\nindex 9dd6b54..e20861f 100644\n--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S\n+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S\n@@ -31,6 +31,7 @@\n #include <asm/tm.h>\n #include <asm/opal.h>\n #include <asm/xive-regs.h>\n+#include <asm/thread_info.h>\n \n /* Sign-extend HDEC if not on POWER9 */\n #define EXTEND_HDEC(reg)\t\t\t\\\n@@ -3104,10 +3105,139 @@ kvmppc_restore_tm:\n /*\n  * We come here if we get any exception or interrupt while we are\n  * executing host real mode code while in guest MMU context.\n- * For now just spin, but we should do something better.\n+ * r12 is (CR << 32) | vector\n+ * r13 points to our PACA\n+ * r12 is saved in HSTATE_SCRATCH0(r13)\n+ * ctr is saved in HSTATE_SCRATCH1(r13) if RELOCATABLE\n+ * r9 is saved in HSTATE_SCRATCH2(r13)\n+ * r13 is saved in HSPRG1\n+ * cfar is saved in HSTATE_CFAR(r13)\n+ * ppr is saved in HSTATE_PPR(r13)\n  */\n kvmppc_bad_host_intr:\n+\t/*\n+\t * Switch to the emergency stack, but start half-way down in\n+\t * case we were already on it.\n+\t */\n+\tmr\tr9, r1\n+\tstd\tr1, PACAR1(r13)\n+\tld\tr1, PACAEMERGSP(r13)\n+\tsubi\tr1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE\n+\tstd\tr9, 0(r1)\n+\tstd\tr0, GPR0(r1)\n+\tstd\tr9, GPR1(r1)\n+\tstd\tr2, GPR2(r1)\n+\tSAVE_4GPRS(3, r1)\n+\tSAVE_2GPRS(7, r1)\n+\tsrdi\tr0, r12, 32\n+\tclrldi\tr12, r12, 32\n+\tstd\tr0, _CCR(r1)\n+\tstd\tr12, _TRAP(r1)\n+\tandi.\tr0, r12, 2\n+\tbeq\t1f\n+\tmfspr\tr3, SPRN_HSRR0\n+\tmfspr\tr4, SPRN_HSRR1\n+\tmfspr\tr5, SPRN_HDAR\n+\tmfspr\tr6, SPRN_HDSISR\n+\tb\t2f\n+1:\tmfspr\tr3, SPRN_SRR0\n+\tmfspr\tr4, SPRN_SRR1\n+\tmfspr\tr5, SPRN_DAR\n+\tmfspr\tr6, SPRN_DSISR\n+2:\tstd\tr3, _NIP(r1)\n+\tstd\tr4, _MSR(r1)\n+\tstd\tr5, _DAR(r1)\n+\tstd\tr6, _DSISR(r1)\n+\tld\tr9, HSTATE_SCRATCH2(r13)\n+\tld\tr12, HSTATE_SCRATCH0(r13)\n+\tGET_SCRATCH0(r0)\n+\tSAVE_4GPRS(9, r1)\n+\tstd\tr0, GPR13(r1)\n+\tSAVE_NVGPRS(r1)\n+\tld\tr5, HSTATE_CFAR(r13)\n+\tstd\tr5, ORIG_GPR3(r1)\n+\tmflr\tr3\n+#ifdef CONFIG_RELOCATABLE\n+\tld\tr4, HSTATE_SCRATCH1(r13)\n+#else\n+\tmfctr\tr4\n+#endif\n+\tmfxer\tr5\n+\tlbz\tr6, PACASOFTIRQEN(r13)\n+\tstd\tr3, _LINK(r1)\n+\tstd\tr4, _CTR(r1)\n+\tstd\tr5, _XER(r1)\n+\tstd\tr6, SOFTE(r1)\n+\tld\tr2, PACATOC(r13)\n+\tLOAD_REG_IMMEDIATE(3, 0x7265677368657265)\n+\tstd\tr3, STACK_FRAME_OVERHEAD-16(r1)\n+\n+\t/*\n+\t * On POWER9 do a minimal restore of the MMU and call C code,\n+\t * which will print a message and panic.\n+\t * XXX On POWER7 and POWER8, we just spin here since we don't\n+\t * know what the other threads are doing (and we don't want to\n+\t * coordinate with them) - but at least we now have register state\n+\t * in memory that we might be able to look at from another CPU.\n+\t */\n+BEGIN_FTR_SECTION\n \tb\t.\n+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)\n+\tld\tr9, HSTATE_KVM_VCPU(r13)\n+\tld\tr10, VCPU_KVM(r9)\n+\n+\tli\tr0, 0\n+\tmtspr\tSPRN_AMR, r0\n+\tmtspr\tSPRN_IAMR, r0\n+\tmtspr\tSPRN_CIABR, r0\n+\tmtspr\tSPRN_DAWRX, r0\n+\n+\t/* Flush the ERAT on radix P9 DD1 guest exit */\n+BEGIN_FTR_SECTION\n+\tPPC_INVALIDATE_ERAT\n+END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)\n+\n+BEGIN_MMU_FTR_SECTION\n+\tb\t4f\n+END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)\n+\n+\tslbmte\tr0, r0\n+\tslbia\n+\tptesync\n+\tld\tr8, PACA_SLBSHADOWPTR(r13)\n+\t.rept\tSLB_NUM_BOLTED\n+\tli\tr3, SLBSHADOW_SAVEAREA\n+\tLDX_BE\tr5, r8, r3\n+\taddi\tr3, r3, 8\n+\tLDX_BE\tr6, r8, r3\n+\tandis.\tr7, r5, SLB_ESID_V@h\n+\tbeq\t3f\n+\tslbmte\tr6, r5\n+3:\taddi\tr8, r8, 16\n+\t.endr\n+\n+4:\tlwz\tr7, KVM_HOST_LPID(r10)\n+\tmtspr\tSPRN_LPID, r7\n+\tmtspr\tSPRN_PID, r0\n+\tld\tr8, KVM_HOST_LPCR(r10)\n+\tmtspr\tSPRN_LPCR, r8\n+\tisync\n+\tli\tr0, KVM_GUEST_MODE_NONE\n+\tstb\tr0, HSTATE_IN_GUEST(r13)\n+\n+\t/*\n+\t * Turn on the MMU and jump to C code\n+\t */\n+\tbcl\t20, 31, .+4\n+5:\tmflr\tr3\n+\taddi\tr3, r3, 9f - 5b\n+\tld\tr4, PACAKMSR(r13)\n+\tmtspr\tSPRN_SRR0, r3\n+\tmtspr\tSPRN_SRR1, r4\n+\trfid\n+9:\taddi\tr3, r1, STACK_FRAME_OVERHEAD\n+\tbl\tkvmppc_bad_interrupt\n+\tb\t9b\n \n /*\n  * This mimics the MSR transition on IRQ delivery.  The new guest MSR is taken\n",
    "prefixes": []
}