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GET /api/patches/808491/?format=api
{ "id": 808491, "url": "http://patchwork.ozlabs.org/api/patches/808491/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170901001502.29915-7-jsnow@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170901001502.29915-7-jsnow@redhat.com>", "list_archive_url": null, "date": "2017-09-01T00:14:59", "name": "[v3,6/9] AHCI: Replace DPRINTF with trace-events", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "72e01f8d312fcfb567b798a54a95913d0f7b2366", "submitter": { "id": 64343, "url": "http://patchwork.ozlabs.org/api/people/64343/?format=api", "name": "John Snow", "email": "jsnow@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170901001502.29915-7-jsnow@redhat.com/mbox/", "series": [ { "id": 931, "url": "http://patchwork.ozlabs.org/api/series/931/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=931", "date": "2017-09-01T00:14:53", "name": "IDE: replace printfs with tracing", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/931/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808491/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808491/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com", "ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=jsnow@redhat.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xk0L95ZXmz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 1 Sep 2017 10:22:09 +1000 (AEST)", "from localhost ([::1]:34730 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dnZip-0005eT-Sd\n\tfor incoming@patchwork.ozlabs.org; Thu, 31 Aug 2017 20:22:07 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:51786)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <jsnow@redhat.com>) id 1dnZcm-0000OD-6A\n\tfor qemu-devel@nongnu.org; Thu, 31 Aug 2017 20:15:54 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <jsnow@redhat.com>) id 1dnZcj-0004tJ-88\n\tfor qemu-devel@nongnu.org; Thu, 31 Aug 2017 20:15:52 -0400", "from mx1.redhat.com ([209.132.183.28]:36882)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <jsnow@redhat.com>)\n\tid 1dnZcc-0004fc-77; Thu, 31 Aug 2017 20:15:42 -0400", "from smtp.corp.redhat.com\n\t(int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 4FB4072F20;\n\tFri, 1 Sep 2017 00:15:41 +0000 (UTC)", "from probe.bos.redhat.com (dhcp-17-130.bos.redhat.com\n\t[10.18.17.130])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 1F14CA3961;\n\tFri, 1 Sep 2017 00:15:40 +0000 (UTC)" ], "DMARC-Filter": "OpenDMARC Filter v1.3.2 mx1.redhat.com 4FB4072F20", "From": "John Snow <jsnow@redhat.com>", "To": "qemu-block@nongnu.org", "Date": "Thu, 31 Aug 2017 20:14:59 -0400", "Message-Id": "<20170901001502.29915-7-jsnow@redhat.com>", "In-Reply-To": "<20170901001502.29915-1-jsnow@redhat.com>", "References": "<20170901001502.29915-1-jsnow@redhat.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "X-Scanned-By": "MIMEDefang 2.79 on 10.5.11.13", "X-Greylist": "Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.25]);\n\tFri, 01 Sep 2017 00:15:41 +0000 (UTC)", "Content-Transfer-Encoding": "quoted-printable", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "209.132.183.28", "Subject": "[Qemu-devel] [PATCH v3 6/9] AHCI: Replace DPRINTF with trace-events", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "John Snow <jsnow@redhat.com>, qemu-devel@nongnu.org, stefanha@redhat.com,\n\tf4bug@amsat.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "There are a few hangers-on that will be dealt with individually\nin forthcoming patches.\n\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nSigned-off-by: John Snow <jsnow@redhat.com>\n---\n hw/ide/ahci.c | 157 +++++++++++++++++++++++-----------------------------\n hw/ide/trace-events | 49 ++++++++++++++++\n 2 files changed, 117 insertions(+), 89 deletions(-)", "diff": "diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c\nindex 406a1b5..c60a000 100644\n--- a/hw/ide/ahci.c\n+++ b/hw/ide/ahci.c\n@@ -35,6 +35,7 @@\n #include \"hw/ide/ahci_internal.h\"\n \n #define DEBUG_AHCI 0\n+#include \"trace.h\"\n \n #define DPRINTF(port, fmt, ...) \\\n do { \\\n@@ -114,9 +115,9 @@ static uint32_t ahci_port_read(AHCIState *s, int port, int offset)\n default:\n val = 0;\n }\n- DPRINTF(port, \"offset: 0x%x val: 0x%x\\n\", offset, val);\n- return val;\n \n+ trace_ahci_port_read(s, port, offset, val);\n+ return val;\n }\n \n static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)\n@@ -125,7 +126,7 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)\n PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),\n TYPE_PCI_DEVICE);\n \n- DPRINTF(0, \"raise irq\\n\");\n+ trace_ahci_irq_raise(s);\n \n if (pci_dev && msi_enabled(pci_dev)) {\n msi_notify(pci_dev, 0);\n@@ -140,7 +141,7 @@ static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)\n PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),\n TYPE_PCI_DEVICE);\n \n- DPRINTF(0, \"lower irq\\n\");\n+ trace_ahci_irq_lower(s);\n \n if (!pci_dev || !msi_enabled(pci_dev)) {\n qemu_irq_lower(s->irq);\n@@ -150,8 +151,7 @@ static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)\n static void ahci_check_irq(AHCIState *s)\n {\n int i;\n-\n- DPRINTF(-1, \"check irq %#x\\n\", s->control_regs.irqstatus);\n+ uint32_t old_irq = s->control_regs.irqstatus;\n \n s->control_regs.irqstatus = 0;\n for (i = 0; i < s->ports; i++) {\n@@ -160,7 +160,7 @@ static void ahci_check_irq(AHCIState *s)\n s->control_regs.irqstatus |= (1 << i);\n }\n }\n-\n+ trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus);\n if (s->control_regs.irqstatus &&\n (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {\n ahci_irq_raise(s, NULL);\n@@ -240,7 +240,7 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)\n {\n AHCIPortRegs *pr = &s->dev[port].port_regs;\n \n- DPRINTF(port, \"offset: 0x%x val: 0x%x\\n\", offset, val);\n+ trace_ahci_port_write(s, port, offset, val);\n switch (offset) {\n case PORT_LST_ADDR:\n pr->lst_addr = val;\n@@ -341,8 +341,6 @@ static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)\n val = s->control_regs.version;\n break;\n }\n-\n- DPRINTF(-1, \"(addr 0x%08X), val 0x%08X\\n\", (unsigned) addr, val);\n } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&\n (addr < (AHCI_PORT_REGS_START_ADDR +\n (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {\n@@ -350,6 +348,7 @@ static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)\n addr & AHCI_PORT_ADDR_OFFSET_MASK);\n }\n \n+ trace_ahci_mem_read_32(s, addr, val);\n return val;\n }\n \n@@ -379,8 +378,7 @@ static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size)\n val = (hi << 32 | lo) >> (ofst * 8);\n }\n \n- DPRINTF(-1, \"addr=0x%\" HWADDR_PRIx \" val=0x%\" PRIx64 \", size=%d\\n\",\n- addr, val, size);\n+ trace_ahci_mem_read(opaque, size, addr, val);\n return val;\n }\n \n@@ -390,8 +388,7 @@ static void ahci_mem_write(void *opaque, hwaddr addr,\n {\n AHCIState *s = opaque;\n \n- DPRINTF(-1, \"addr=0x%\" HWADDR_PRIx \" val=0x%\" PRIx64 \", size=%d\\n\",\n- addr, val, size);\n+ trace_ahci_mem_write(s, size, addr, val);\n \n /* Only aligned reads are allowed on AHCI */\n if (addr & 3) {\n@@ -401,15 +398,12 @@ static void ahci_mem_write(void *opaque, hwaddr addr,\n }\n \n if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {\n- DPRINTF(-1, \"(addr 0x%08X), val 0x%08\"PRIX64\"\\n\", (unsigned) addr, val);\n-\n switch (addr) {\n case HOST_CAP: /* R/WO, RO */\n /* FIXME handle R/WO */\n break;\n case HOST_CTL: /* R/W */\n if (val & HOST_CTL_RESET) {\n- DPRINTF(-1, \"HBA Reset\\n\");\n ahci_reset(s);\n } else {\n s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;\n@@ -427,7 +421,7 @@ static void ahci_mem_write(void *opaque, hwaddr addr,\n /* FIXME report write? */\n break;\n default:\n- DPRINTF(-1, \"write to unknown register 0x%x\\n\", (unsigned)addr);\n+ trace_ahci_mem_write_unknown(s, size, addr, val);\n }\n } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&\n (addr < (AHCI_PORT_REGS_START_ADDR +\n@@ -559,7 +553,8 @@ static void ahci_set_signature(AHCIDevice *ad, uint32_t sig)\n s->sector = sig >> 8 & 0xFF;\n s->nsector = sig & 0xFF;\n \n- DPRINTF(ad->port_no, \"set hcyl:lcyl:sect:nsect = 0x%08x\\n\", sig);\n+ trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector,\n+ s->lcyl, s->hcyl, sig);\n }\n \n static void ahci_reset_port(AHCIState *s, int port)\n@@ -569,7 +564,7 @@ static void ahci_reset_port(AHCIState *s, int port)\n IDEState *ide_state = &d->port.ifs[0];\n int i;\n \n- DPRINTF(port, \"reset port\\n\");\n+ trace_ahci_reset_port(s, port);\n \n ide_bus_reset(&d->port);\n ide_state->ncq_queues = AHCI_MAX_CMDS;\n@@ -655,7 +650,7 @@ static bool ahci_map_fis_address(AHCIDevice *ad)\n static void ahci_unmap_fis_address(AHCIDevice *ad)\n {\n if (ad->res_fis == NULL) {\n- DPRINTF(ad->port_no, \"Attempt to unmap NULL FIS address\\n\");\n+ trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no);\n return;\n }\n ad->port_regs.cmd &= ~PORT_CMD_FIS_ON;\n@@ -682,7 +677,7 @@ static bool ahci_map_clb_address(AHCIDevice *ad)\n static void ahci_unmap_clb_address(AHCIDevice *ad)\n {\n if (ad->lst == NULL) {\n- DPRINTF(ad->port_no, \"Attempt to unmap NULL CLB address\\n\");\n+ trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no);\n return;\n }\n ad->port_regs.cmd &= ~PORT_CMD_LIST_ON;\n@@ -854,20 +849,22 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,\n IDEBus *bus = &ad->port;\n BusState *qbus = BUS(bus);\n \n+ trace_ahci_populate_sglist(ad->hba, ad->port_no);\n+\n if (!prdtl) {\n- DPRINTF(ad->port_no, \"no sg list given by guest: 0x%08x\\n\", opts);\n+ trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts);\n return -1;\n }\n \n /* map PRDT */\n if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len,\n DMA_DIRECTION_TO_DEVICE))){\n- DPRINTF(ad->port_no, \"map failed\\n\");\n+ trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no);\n return -1;\n }\n \n if (prdt_len < real_prdt_len) {\n- DPRINTF(ad->port_no, \"mapped less than expected\\n\");\n+ trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no);\n r = -1;\n goto out;\n }\n@@ -886,9 +883,8 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,\n sum += tbl_entry_size;\n }\n if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) {\n- DPRINTF(ad->port_no, \"%s: Incorrect offset! \"\n- \"off_idx: %d, off_pos: %\"PRId64\"\\n\",\n- __func__, off_idx, off_pos);\n+ trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no,\n+ off_idx, off_pos);\n r = -1;\n goto out;\n }\n@@ -934,8 +930,8 @@ static void ncq_finish(NCQTransferState *ncq_tfs)\n \n ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs);\n \n- DPRINTF(ncq_tfs->drive->port_no, \"NCQ transfer tag %d finished\\n\",\n- ncq_tfs->tag);\n+ trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,\n+ ncq_tfs->tag);\n \n block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk),\n &ncq_tfs->acct);\n@@ -999,12 +995,8 @@ static void execute_ncq_command(NCQTransferState *ncq_tfs)\n \n switch (ncq_tfs->cmd) {\n case READ_FPDMA_QUEUED:\n- DPRINTF(port, \"NCQ reading %d sectors from LBA %\"PRId64\", tag %d\\n\",\n- ncq_tfs->sector_count, ncq_tfs->lba, ncq_tfs->tag);\n-\n- DPRINTF(port, \"tag %d aio read %\"PRId64\"\\n\",\n- ncq_tfs->tag, ncq_tfs->lba);\n-\n+ trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag,\n+ ncq_tfs->sector_count, ncq_tfs->lba);\n dma_acct_start(ide_state->blk, &ncq_tfs->acct,\n &ncq_tfs->sglist, BLOCK_ACCT_READ);\n ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist,\n@@ -1013,12 +1005,8 @@ static void execute_ncq_command(NCQTransferState *ncq_tfs)\n ncq_cb, ncq_tfs);\n break;\n case WRITE_FPDMA_QUEUED:\n- DPRINTF(port, \"NCQ writing %d sectors to LBA %\"PRId64\", tag %d\\n\",\n- ncq_tfs->sector_count, ncq_tfs->lba, ncq_tfs->tag);\n-\n- DPRINTF(port, \"tag %d aio write %\"PRId64\"\\n\",\n- ncq_tfs->tag, ncq_tfs->lba);\n-\n+ trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag,\n+ ncq_tfs->sector_count, ncq_tfs->lba);\n dma_acct_start(ide_state->blk, &ncq_tfs->acct,\n &ncq_tfs->sglist, BLOCK_ACCT_WRITE);\n ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist,\n@@ -1027,8 +1015,8 @@ static void execute_ncq_command(NCQTransferState *ncq_tfs)\n ncq_cb, ncq_tfs);\n break;\n default:\n- DPRINTF(port, \"error: unsupported NCQ command (0x%02x) received\\n\",\n- ncq_tfs->cmd);\n+ trace_execute_ncq_command_unsup(ad->hba, port,\n+ ncq_tfs->tag, ncq_tfs->cmd);\n ncq_err(ncq_tfs);\n }\n }\n@@ -1038,7 +1026,6 @@ static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,\n uint8_t slot)\n {\n AHCIDevice *ad = &s->dev[port];\n- IDEState *ide_state = &ad->port.ifs[0];\n NCQFrame *ncq_fis = (NCQFrame*)cmd_fis;\n uint8_t tag = ncq_fis->tag >> 3;\n NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag];\n@@ -1066,21 +1053,20 @@ static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,\n \n /* Sanity-check the NCQ packet */\n if (tag != slot) {\n- DPRINTF(port, \"Warn: NCQ slot (%d) did not match the given tag (%d)\\n\",\n- slot, tag);\n+ trace_process_ncq_command_mismatch(s, port, tag, slot);\n }\n \n if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) {\n- DPRINTF(port, \"Warn: Attempt to use NCQ auxiliary fields.\\n\");\n+ trace_process_ncq_command_aux(s, port, tag);\n }\n if (ncq_fis->prio || ncq_fis->icc) {\n- DPRINTF(port, \"Warn: Unsupported attempt to use PRIO/ICC fields\\n\");\n+ trace_process_ncq_command_prioicc(s, port, tag);\n }\n if (ncq_fis->fua & NCQ_FIS_FUA_MASK) {\n- DPRINTF(port, \"Warn: Unsupported attempt to use Force Unit Access\\n\");\n+ trace_process_ncq_command_fua(s, port, tag);\n }\n if (ncq_fis->tag & NCQ_FIS_RARC_MASK) {\n- DPRINTF(port, \"Warn: Unsupported attempt to use Rebuild Assist\\n\");\n+ trace_process_ncq_command_rarc(s, port, tag);\n }\n \n ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) |\n@@ -1099,16 +1085,14 @@ static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,\n ahci_trigger_irq(ad->hba, ad, PORT_IRQ_OVERFLOW);\n return;\n } else if (ncq_tfs->sglist.size != size) {\n- DPRINTF(port, \"Warn: PRDTL (0x%zx)\"\n- \" does not match requested size (0x%zx)\",\n- ncq_tfs->sglist.size, size);\n+ trace_process_ncq_command_large(s, port, tag,\n+ ncq_tfs->sglist.size, size);\n }\n \n- DPRINTF(port, \"NCQ transfer LBA from %\"PRId64\" to %\"PRId64\", \"\n- \"drive max %\"PRId64\"\\n\",\n- ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 1,\n- ide_state->nb_sectors - 1);\n-\n+ trace_process_ncq_command(s, port, tag,\n+ ncq_fis->command,\n+ ncq_tfs->lba,\n+ ncq_tfs->lba + ncq_tfs->sector_count - 1);\n execute_ncq_command(ncq_tfs);\n }\n \n@@ -1129,16 +1113,14 @@ static void handle_reg_h2d_fis(AHCIState *s, int port,\n uint16_t opts = le16_to_cpu(cmd->opts);\n \n if (cmd_fis[1] & 0x0F) {\n- DPRINTF(port, \"Port Multiplier not supported.\"\n- \" cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\\n\",\n- cmd_fis[0], cmd_fis[1], cmd_fis[2]);\n+ trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1],\n+ cmd_fis[2], cmd_fis[3]);\n return;\n }\n \n if (cmd_fis[1] & 0x70) {\n- DPRINTF(port, \"Reserved flags set in H2D Register FIS.\"\n- \" cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\\n\",\n- cmd_fis[0], cmd_fis[1], cmd_fis[2]);\n+ trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1],\n+ cmd_fis[2], cmd_fis[3]);\n return;\n }\n \n@@ -1216,12 +1198,12 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot)\n \n if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {\n /* Engine currently busy, try again later */\n- DPRINTF(port, \"engine busy\\n\");\n+ trace_handle_cmd_busy(s, port);\n return -1;\n }\n \n if (!s->dev[port].lst) {\n- DPRINTF(port, \"error: lst not given but cmd handled\");\n+ trace_handle_cmd_nolist(s, port);\n return -1;\n }\n cmd = get_cmd_header(s, port, slot);\n@@ -1231,7 +1213,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot)\n /* The device we are working for */\n ide_state = &s->dev[port].port.ifs[0];\n if (!ide_state->blk) {\n- DPRINTF(port, \"error: guest accessed unused port\");\n+ trace_handle_cmd_badport(s, port);\n return -1;\n }\n \n@@ -1240,13 +1222,11 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot)\n cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len,\n DMA_DIRECTION_FROM_DEVICE);\n if (!cmd_fis) {\n- DPRINTF(port, \"error: guest passed us an invalid cmd fis\\n\");\n+ trace_handle_cmd_badfis(s, port);\n return -1;\n } else if (cmd_len != 0x80) {\n ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_HBUS_ERR);\n- DPRINTF(port, \"error: dma_memory_map failed: \"\n- \"(len(%02\"PRIx64\") != 0x80)\\n\",\n- cmd_len);\n+ trace_handle_cmd_badmap(s, port, cmd_len);\n goto out;\n }\n debug_print_fis(cmd_fis, 0x80);\n@@ -1256,9 +1236,8 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot)\n handle_reg_h2d_fis(s, port, slot, cmd_fis);\n break;\n default:\n- DPRINTF(port, \"unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x \"\n- \"cmd_fis[2]=%02x\\n\", cmd_fis[0], cmd_fis[1],\n- cmd_fis[2]);\n+ trace_handle_cmd_unhandled_fis(s, port,\n+ cmd_fis[0], cmd_fis[1], cmd_fis[2]);\n break;\n }\n \n@@ -1299,9 +1278,9 @@ static void ahci_start_transfer(IDEDMA *dma)\n has_sglist = 1;\n }\n \n- DPRINTF(ad->port_no, \"%sing %d bytes on %s w/%s sglist\\n\",\n- is_write ? \"writ\" : \"read\", size, is_atapi ? \"atapi\" : \"ata\",\n- has_sglist ? \"\" : \"o\");\n+ trace_ahci_start_transfer(ad->hba, ad->port_no, is_write ? \"writ\" : \"read\",\n+ size, is_atapi ? \"atapi\" : \"ata\",\n+ has_sglist ? \"\" : \"o\");\n \n if (has_sglist && size) {\n if (is_write) {\n@@ -1330,7 +1309,7 @@ static void ahci_start_dma(IDEDMA *dma, IDEState *s,\n BlockCompletionFunc *dma_cb)\n {\n AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);\n- DPRINTF(ad->port_no, \"\\n\");\n+ trace_ahci_start_dma(ad->hba, ad->port_no);\n s->io_buffer_offset = 0;\n dma_cb(s, 0);\n }\n@@ -1368,12 +1347,12 @@ static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit)\n \n if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd,\n limit, s->io_buffer_offset) == -1) {\n- DPRINTF(ad->port_no, \"ahci_dma_prepare_buf failed.\\n\");\n+ trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no);\n return -1;\n }\n s->io_buffer_size = s->sg.size;\n \n- DPRINTF(ad->port_no, \"len=%#x\\n\", s->io_buffer_size);\n+ trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size);\n return s->io_buffer_size;\n }\n \n@@ -1409,11 +1388,9 @@ static int ahci_dma_rw_buf(IDEDMA *dma, int is_write)\n \n /* free sglist, update byte count */\n dma_buf_commit(s, l);\n-\n s->io_buffer_index += l;\n \n- DPRINTF(ad->port_no, \"len=%#x\\n\", l);\n-\n+ trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l);\n return 1;\n }\n \n@@ -1421,7 +1398,7 @@ static void ahci_cmd_done(IDEDMA *dma)\n {\n AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);\n \n- DPRINTF(ad->port_no, \"cmd done\\n\");\n+ trace_ahci_cmd_done(ad->hba, ad->port_no);\n \n /* update d2h status */\n ahci_write_fis_d2h(ad);\n@@ -1505,6 +1482,8 @@ void ahci_reset(AHCIState *s)\n AHCIPortRegs *pr;\n int i;\n \n+ trace_ahci_reset(s);\n+\n s->control_regs.irqstatus = 0;\n /* AHCI Enable (AE)\n * The implementation of this bit is dependent upon the value of the\n@@ -1755,6 +1734,7 @@ static uint64_t allwinner_ahci_mem_read(void *opaque, hwaddr addr,\n unsigned size)\n {\n AllwinnerAHCIState *a = opaque;\n+ AHCIState *s = &(SYSBUS_AHCI(a)->ahci);\n uint64_t val = a->regs[addr/4];\n \n switch (addr / 4) {\n@@ -1765,8 +1745,7 @@ static uint64_t allwinner_ahci_mem_read(void *opaque, hwaddr addr,\n val &= ~(0x1 << 24);\n break;\n }\n- DPRINTF(-1, \"addr=0x%\" HWADDR_PRIx \" val=0x%\" PRIx64 \", size=%d\\n\",\n- addr, val, size);\n+ trace_allwinner_ahci_mem_read(s, a, addr, val, size);\n return val;\n }\n \n@@ -1774,9 +1753,9 @@ static void allwinner_ahci_mem_write(void *opaque, hwaddr addr,\n uint64_t val, unsigned size)\n {\n AllwinnerAHCIState *a = opaque;\n+ AHCIState *s = &(SYSBUS_AHCI(a)->ahci);\n \n- DPRINTF(-1, \"addr=0x%\" HWADDR_PRIx \" val=0x%\" PRIx64 \", size=%d\\n\",\n- addr, val, size);\n+ trace_allwinner_ahci_mem_write(s, a, addr, val, size);\n a->regs[addr/4] = val;\n }\n \ndiff --git a/hw/ide/trace-events b/hw/ide/trace-events\nindex cc8949c..0b61c5d 100644\n--- a/hw/ide/trace-events\n+++ b/hw/ide/trace-events\n@@ -56,3 +56,52 @@ ide_atapi_cmd(void *s, uint8_t cmd) \"IDEState: %p; cmd: 0x%02x\"\n ide_atapi_cmd_read_dma_cb_aio(void *s, int lba, int n) \"IDEState: %p; aio read: lba=%d n=%d\"\n # Warning: Verbose\n ide_atapi_cmd_packet(void *s, uint16_t limit, const char *packet) \"IDEState: %p; limit=0x%x packet: %s\"\n+\n+# hw/ide/ahci.c\n+ahci_port_read(void *s, int port, int offset, uint32_t ret) \"ahci(%p)[%d]: port read @ 0x%x: 0x%08x\"\n+ahci_irq_raise(void *s) \"ahci(%p): raise irq\"\n+ahci_irq_lower(void *s) \"ahci(%p): lower irq\"\n+ahci_check_irq(void *s, uint32_t old, uint32_t new) \"ahci(%p): check irq 0x%08x --> 0x%08x\"\n+\n+ahci_port_write(void *s, int port, int offset, uint32_t val) \"ahci(%p)[%d]: port write @ 0x%x: 0x%08x\"\n+ahci_mem_read_32(void *s, uint64_t addr, uint32_t val) \"ahci(%p): mem read @ 0x%\"PRIx64\": 0x%08x\"\n+ahci_mem_read(void *s, unsigned size, uint64_t addr, uint64_t val) \"ahci(%p): read%u @ 0x%\"PRIx64\": 0x%016\"PRIx64\n+ahci_mem_write(void *s, unsigned size, uint64_t addr, uint64_t val) \"ahci(%p): write%u @ 0x%\"PRIx64\": 0x%016\"PRIx64\n+ahci_mem_write_unknown(void *s, unsigned size, uint64_t addr, uint64_t val) \"ahci(%p): write%u to unknown register 0x%\"PRIx64\": 0x%016\"PRIx64\n+ahci_set_signature(void *s, int port, uint8_t nsector, uint8_t sector, uint8_t lcyl, uint8_t hcyl, uint32_t sig) \"ahci(%p)[%d]: set signature sector:0x%02x nsector:0x%02x lcyl:0x%02x hcyl:0x%02x (cumulatively: 0x%08x)\"\n+ahci_reset_port(void *s, int port) \"ahci(%p)[%d]: reset port\"\n+ahci_unmap_fis_address_null(void *s, int port) \"ahci(%p)[%d]: Attempt to unmap NULL FIS address\"\n+ahci_unmap_clb_address_null(void *s, int port) \"ahci(%p)[%d]: Attempt to unmap NULL CLB address\"\n+ahci_populate_sglist(void *s, int port) \"ahci(%p)[%d]\"\n+ahci_populate_sglist_no_prdtl(void *s, int port, uint16_t opts) \"ahci(%p)[%d]: no sg list given by guest: 0x%04x\"\n+ahci_populate_sglist_no_map(void *s, int port) \"ahci(%p)[%d]: DMA mapping failed\"\n+ahci_populate_sglist_short_map(void *s, int port) \"ahci(%p)[%d]: mapped less than expected\"\n+ahci_populate_sglist_bad_offset(void *s, int port, int off_idx, int64_t off_pos) \"ahci(%p)[%d]: Incorrect offset! off_idx: %d, off_pos: %\"PRId64\n+ncq_finish(void *s, int port, uint8_t tag) \"ahci(%p)[%d][tag:%d]: NCQ transfer finished\"\n+execute_ncq_command_read(void *s, int port, uint8_t tag, int count, int64_t lba) \"ahci(%p)[%d][tag:%d]: NCQ reading %d sectors from LBA %\"PRId64\n+execute_ncq_command_write(void *s, int port, uint8_t tag, int count, int64_t lba) \"ahci(%p)[%d][tag:%d]: NCQ writing %d sectors to LBA %\"PRId64\n+execute_ncq_command_unsup(void *s, int port, uint8_t tag, uint8_t cmd) \"ahci(%p)[%d][tag:%d]: error: unsupported NCQ command (0x%02x) received\"\n+process_ncq_command_mismatch(void *s, int port, uint8_t tag, uint8_t slot) \"ahci(%p)[%d][tag:%d]: Warning: NCQ slot (%d) did not match the given tag\"\n+process_ncq_command_aux(void *s, int port, uint8_t tag) \"ahci(%p)[%d][tag:%d]: Warn: Attempt to use NCQ auxiliary fields\"\n+process_ncq_command_prioicc(void *s, int port, uint8_t tag) \"ahci(%p)[%d][tag:%d]: Warn: Unsupported attempt to use PRIO/ICC fields\"\n+process_ncq_command_fua(void *s, int port, uint8_t tag) \"ahci(%p)[%d][tag:%d]: Warn: Unsupported attempt to use Force Unit Access\"\n+process_ncq_command_rarc(void *s, int port, uint8_t tag) \"ahci(%p)[%d][tag:%d]: Warn: Unsupported attempt to use Rebuild Assist\"\n+process_ncq_command_large(void *s, int port, uint8_t tag, size_t prdtl, size_t size) \"ahci(%p)[%d][tag:%d]: Warn: PRDTL (0x%zx) does not match requested size (0x%zx)\"\n+process_ncq_command(void *s, int port, uint8_t tag, uint8_t cmd, uint64_t lba, uint64_t end) \"ahci(%p)[%d][tag:%d]: NCQ op 0x%02x on sectors [%\"PRId64\",%\"PRId64\"]\"\n+handle_reg_h2d_fis_pmp(void *s, int port, char b0, char b1, char b2) \"ahci(%p)[%d]: Port Multiplier not supported, FIS: 0x%02x-%02x-%02x\"\n+handle_reg_h2d_fis_res(void *s, int port, char b0, char b1, char b2) \"ahci(%p)[%d]: Reserved flags set in H2D Register FIS, FIS: 0x%02x-%02x-%02x\"\n+handle_cmd_busy(void *s, int port) \"ahci(%p)[%d]: engine busy\"\n+handle_cmd_nolist(void *s, int port) \"ahci(%p)[%d]: handle_cmd called without s->dev[port].lst\"\n+handle_cmd_badport(void *s, int port) \"ahci(%p)[%d]: guest accessed unused port\"\n+handle_cmd_badfis(void *s, int port) \"ahci(%p)[%d]: guest provided an invalid cmd FIS\"\n+handle_cmd_badmap(void *s, int port, uint64_t len) \"ahci(%p)[%d]: dma_memory_map failed, 0x%02\"PRIx64\" != 0x80\"\n+handle_cmd_unhandled_fis(void *s, int port, uint8_t b0, uint8_t b1, uint8_t b2) \"ahci(%p)[%d]: unhandled FIS type. cmd_fis: 0x%02x-%02x-%02x\"\n+ahci_start_transfer(void *s, int port, const char *rw, uint32_t size, const char *tgt, const char *sgl) \"ahci(%p)[%d]: %sing %d bytes on %s w/%s sglist\"\n+ahci_start_dma(void *s, int port) \"ahci(%p)[%d]: start dma\"\n+ahci_dma_prepare_buf(void *s, int port, int32_t io_buffer_size, int32_t limit) \"ahci(%p)[%d]: prepare buf limit=%\"PRId32\" prepared=%\"PRId32\n+ahci_dma_prepare_buf_fail(void *s, int port) \"ahci(%p)[%d]: sglist population failed\"\n+ahci_dma_rw_buf(void *s, int port, int l) \"ahci(%p)[%d] len=0x%x\"\n+ahci_cmd_done(void *s, int port) \"ahci(%p)[%d]: cmd done\"\n+ahci_reset(void *s) \"ahci(%p): HBA reset\"\n+allwinner_ahci_mem_read(void *s, void *a, uint64_t addr, uint64_t val, unsigned size) \"ahci(%p): read a=%p addr=0x%\"HWADDR_PRIx\" val=0x%\"PRIx64\", size=%d\"\n+allwinner_ahci_mem_write(void *s, void *a, uint64_t addr, uint64_t val, unsigned size) \"ahci(%p): write a=%p addr=0x%\"HWADDR_PRIx\" val=0x%\"PRIx64\", size=%d\"\n", "prefixes": [ "v3", "6/9" ] }