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GET /api/patches/808451/?format=api
{ "id": 808451, "url": "http://patchwork.ozlabs.org/api/patches/808451/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/patch/20170831225400.19756-2-brendanhiggins@google.com/", "project": { "id": 56, "url": "http://patchwork.ozlabs.org/api/projects/56/?format=api", "name": "OpenBMC development", "link_name": "openbmc", "list_id": "openbmc.lists.ozlabs.org", "list_email": "openbmc@lists.ozlabs.org", "web_url": "http://github.com/openbmc/", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170831225400.19756-2-brendanhiggins@google.com>", "list_archive_url": null, "date": "2017-08-31T22:53:58", "name": "[v2,1/3] arm: npcm: add basic support for Nuvoton BMCs", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "d3f9155faf8533a3a352b9561e57d2aa57aeb843", "submitter": { "id": 69647, "url": "http://patchwork.ozlabs.org/api/people/69647/?format=api", "name": "Brendan Higgins", "email": "brendanhiggins@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/openbmc/patch/20170831225400.19756-2-brendanhiggins@google.com/mbox/", "series": [ { "id": 916, "url": "http://patchwork.ozlabs.org/api/series/916/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/list/?series=916", "date": "2017-08-31T22:53:57", "name": "arm: npcm: add basic support for Nuvoton BMCs", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/916/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808451/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808451/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Received": [ "from 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linux@armlinux.org.uk,\n\tavifishman70@gmail.com, tmaimon77@gmail.com, raltherr@google.com", "Subject": "[PATCH v2 1/3] arm: npcm: add basic support for Nuvoton BMCs", "Date": "Thu, 31 Aug 2017 15:53:58 -0700", "Message-Id": "<20170831225400.19756-2-brendanhiggins@google.com>", "X-Mailer": "git-send-email 2.14.1.581.gf28d330327-goog", "In-Reply-To": "<20170831225400.19756-1-brendanhiggins@google.com>", "References": "<20170831225400.19756-1-brendanhiggins@google.com>", "X-BeenThere": "openbmc@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Development list for OpenBMC <openbmc.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/openbmc>,\n\t<mailto:openbmc-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/openbmc/>", "List-Post": "<mailto:openbmc@lists.ozlabs.org>", "List-Help": "<mailto:openbmc-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/openbmc>,\n\t<mailto:openbmc-request@lists.ozlabs.org?subject=subscribe>", "Cc": "devicetree@vger.kernel.org, openbmc@lists.ozlabs.org,\n\tBrendan Higgins <brendanhiggins@google.com>,\n\tlinux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org", "Errors-To": "openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"openbmc\"\n\t<openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "Adds basic support for the Nuvoton NPCM750 BMC.\n\nSigned-off-by: Brendan Higgins <brendanhiggins@google.com>\n---\n arch/arm/Kconfig | 2 +\n arch/arm/Makefile | 1 +\n arch/arm/mach-npcm/Kconfig | 58 +++++++++++++++\n arch/arm/mach-npcm/Makefile | 3 +\n arch/arm/mach-npcm/headsmp.S | 120 +++++++++++++++++++++++++++++++\n arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++\n arch/arm/mach-npcm/platsmp.c | 168 +++++++++++++++++++++++++++++++++++++++++++\n 7 files changed, 386 insertions(+)\n create mode 100644 arch/arm/mach-npcm/Kconfig\n create mode 100644 arch/arm/mach-npcm/Makefile\n create mode 100644 arch/arm/mach-npcm/headsmp.S\n create mode 100644 arch/arm/mach-npcm/npcm7xx.c\n create mode 100644 arch/arm/mach-npcm/platsmp.c", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex 61a0cb15067e..05543f1cfbde 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -782,6 +782,8 @@ source \"arch/arm/mach-netx/Kconfig\"\n \n source \"arch/arm/mach-nomadik/Kconfig\"\n \n+source \"arch/arm/mach-npcm/Kconfig\"\n+\n source \"arch/arm/mach-nspire/Kconfig\"\n \n source \"arch/arm/plat-omap/Kconfig\"\ndiff --git a/arch/arm/Makefile b/arch/arm/Makefile\nindex 47d3a1ab08d2..60ca50c7d762 100644\n--- a/arch/arm/Makefile\n+++ b/arch/arm/Makefile\n@@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK)\t\t+= mediatek\n machine-$(CONFIG_ARCH_MXS)\t\t+= mxs\n machine-$(CONFIG_ARCH_NETX)\t\t+= netx\n machine-$(CONFIG_ARCH_NOMADIK)\t\t+= nomadik\n+machine-$(CONFIG_ARCH_NPCM)\t\t+= npcm\n machine-$(CONFIG_ARCH_NSPIRE)\t\t+= nspire\n machine-$(CONFIG_ARCH_OXNAS)\t\t+= oxnas\n machine-$(CONFIG_ARCH_OMAP1)\t\t+= omap1\ndiff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig\nnew file mode 100644\nindex 000000000000..a45670e516b4\n--- /dev/null\n+++ b/arch/arm/mach-npcm/Kconfig\n@@ -0,0 +1,58 @@\n+menuconfig ARCH_NPCM\n+\tbool \"Nuvoton NPCM Architecture\"\n+\tselect ARCH_REQUIRE_GPIOLIB\n+\tselect USE_OF\n+\tselect PINCTRL\n+\tselect PINCTRL_NPCM7XX\n+\n+if ARCH_NPCM\n+\n+comment \"NPCMX50 CPU type\"\n+\n+config CPU_NPCM750\n+\tdepends on ARCH_NPCM && ARCH_MULTI_V7 && !CPU_V6 && !CPU_V6K\n+\tbool \"Support for NPCM750 BMC CPU (Poleg)\"\n+\tselect CACHE_L2X0\n+\tselect CPU_V7\n+\tselect ARM_GIC\n+\tselect ARM_ERRATA_754322\n+\tselect ARM_ERRATA_764369\n+\tselect USB_EHCI_ROOT_HUB_TT\n+\tselect USB_ARCH_HAS_HCD\n+\tselect USB_ARCH_HAS_EHCI\n+\tselect USB_EHCI_HCD\n+\tselect USB_ARCH_HAS_OHCI\n+\tselect USB_OHCI_HCD\n+\tselect USB\n+\tselect FIQ\n+\tselect CPU_USE_DOMAINS\n+\tselect COMMON_CLK if OF\n+\tselect NPCM750_TIMER\n+\tselect MFD_SYSCON\n+\thelp\n+\t Support for single core NPCM750 BMC CPU (Poleg).\n+\n+\t Single core variant of the Nuvoton NPCM750 BMC based on the Cortex A9.\n+\n+config CPU_NPCM750_SMP\n+\tdepends on CPU_NPCM750\n+\tbool \"Support for NPCM750 BMC CPU SMP (Poleg)\"\n+\tselect HAVE_SMP\n+\tselect HAVE_ARM_SCU\n+\tselect ARM_ERRATA_794072\n+\tselect PL310_ERRATA_588369\n+\tselect PL310_ERRATA_727915\n+\tselect ARM_ERRATA_720789\n+\tselect DEBUG_SPINLOCK\n+\tselect GENERIC_CLOCKEVENTS\n+\tselect SMP\n+\tselect HAVE_ARM_TWD if SMP\n+\tselect HAVE_ARM_SCU if SMP\n+\tselect CLKDEV_LOOKUP\n+\tselect COMMON_CLK if OF\n+\thelp\n+\t Support for dual core NPCM750 BMC CPU (Poleg).\n+\n+\t Dual core variant of the Nuvoton NPCM750 BMC based on the Cortex A9.\n+\n+endif\ndiff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile\nnew file mode 100644\nindex 000000000000..634e7c4d6b98\n--- /dev/null\n+++ b/arch/arm/mach-npcm/Makefile\n@@ -0,0 +1,3 @@\n+obj-$(CONFIG_CPU_NPCM750_SMP)\t+= platsmp.o headsmp.o\n+\n+obj-$(CONFIG_CPU_NPCM750)\t+= npcm7xx.o\ndiff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S\nnew file mode 100644\nindex 000000000000..d22d2fc1a35c\n--- /dev/null\n+++ b/arch/arm/mach-npcm/headsmp.S\n@@ -0,0 +1,120 @@\n+/*\n+ * linux/arch/arm/mach-realview/headsmp.S\n+ *\n+ * Copyright (c) 2003 ARM Limited\n+ * Copyright 2017 Google, Inc.\n+ * All Rights Reserved\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include <linux/linkage.h>\n+#include <linux/init.h>\n+\n+.equ SVC_MODE, 0x13\n+.equ I_BIT, 0x80\n+.equ F_BIT, 0x40\n+\n+ENTRY(npcm7xx_wakeup_z1)\n+\tstmfd\tsp!, {r0-r12, lr}\n+\tldr\tr0, =0x01\n+\tldr\tr1, =0x01\n+\tldr\tr2, =0x01\n+\n+\tand\tr3, r0, #0x0F /* Mask off unused bits of ID, and move to r3 */\n+\tand\tr1, r1, #0x0F /* Mask off unused bits of target_filter */\n+\tand\tr2, r2, #0x0F /* Mask off unused bits of filter_list */\n+\n+\torr\tr3, r3, r1, LSL #16 /* Combine ID and target_filter */\n+\torr\tr3, r3, r2, LSL #24 /* and now the filter list */\n+\n+\t/* Get the address of the GIC */\n+\tmrc\tp15, 4, r0, c15, c0, 0 /* Read periph base address */\n+\tadd\tr0, r0, #0x1F00 /* Add offset of the sgi_trigger reg */\n+\n+\t/* Write to the Software Generated Interrupt Register (ICDSGIR) */\n+\tstr\tr3, [r0]\n+\n+\tldmfd\tsp!, {r0-r12, pc}\n+ENDPROC(npcm7xx_wakeup_z1)\n+\n+ENTRY(v7_invalidate_l1_npcmX50)\n+\tmov\tr0, #0\n+\tmcr\tp15, 0, r0, c7, c5, 0 /* invalidate I cache */\n+\tmcr\tp15, 2, r0, c0, c0, 0\n+\tmrc\tp15, 1, r0, c0, c0, 0\n+\n+\tldr\tr1, =0x7fff\n+\tand\tr2, r1, r0, lsr #13\n+\n+\tldr\tr1, =0x3ff\n+\n+\tand\tr3, r1, r0, lsr #3 /* NumWays - 1 */\n+\tadd\tr2, r2, #1 /* NumSets */\n+\n+\tand\tr0, r0, #0x7\n+\tadd\tr0, r0, #4 /* SetShift */\n+\n+\tclz\tr1, r3 /* WayShift */\n+\tadd\tr4, r3, #1 /* NumWays */\n+1:\tsub\tr2, r2, #1 /* NumSets-- */\n+\tmov\tr3, r4 /* Temp = NumWays */\n+2:\tsubs\tr3, r3, #1 /* Temp-- */\n+\tmov\tr5, r3, lsl r1\n+\tmov\tr6, r2, lsl r0\n+\t/* Reg = (Temp << WayShift) | (NumSets << SetShift) */\n+\torr\tr5, r5, r6\n+\tmcr\tp15, 0, r5, c7, c6, 2\n+\tbgt\t2b\n+\tcmp\tr2, #0\n+\tbgt\t1b\n+\tdsb\n+\tisb\n+\tmov\tpc, lr\n+ENDPROC(v7_invalidate_l1_npcmX50)\n+\n+/*\n+ * MSM specific entry point for secondary CPUs. This provides\n+ * a \"holding pen\" into which all secondary cores are held until we're\n+ * ready for them to initialise.\n+ */\n+ENTRY(npcm7xx_secondary_startup)\n+\tmsr\tCPSR_c, #(SVC_MODE)\n+\n+\tbl\tv7_invalidate_l1_npcmX50\n+\t/* disable vector table remapping */\n+\tmrc\tp15, 0,r0, c1, c0, 0\n+\tand\tr0, #0xffffdfff\n+\tmcr\tp15, 0,r0, c1, c0, 0\n+\n+#ifdef CONFIG_CACHE_L2X0\n+\t/* Enable L1 & L2 prefetch + Zero line */\n+\tmrc\tp15, 0, r0, c1, c0, 1\n+\torr\tr0, r0, #(7 << 1)\n+\tmcr\tp15, 0, r0, c1, c0, 1\n+#endif /* CONFIG_CACHE_L2X0 */\n+\n+\tmrc\tp15, 0, r0, c0, c0, 5\n+\tand\tr0, r0, #15\n+\tadr\tr4, 1f\n+\tldmia\tr4, {r5, r6}\n+\tsub\tr4, r4, r5\n+\tadd\tr6, r6, r4\n+\tstr r3,[r2]\n+\n+pen:\tldr\tr7, [r6]\n+\tcmp\tr7, r0\n+\tbne\tpen\n+\n+\t/*\n+\t * we've been released from the holding pen: secondary_stack\n+\t * should now contain the SVC stack for this core\n+\t */\n+\tb\tsecondary_startup\n+ENDPROC(npcm7xx_secondary_startup)\n+\n+\t.align\n+1:\t.long\t.\n+\t.long\tpen_release\ndiff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c\nnew file mode 100644\nindex 000000000000..106dc62dd62b\n--- /dev/null\n+++ b/arch/arm/mach-npcm/npcm7xx.c\n@@ -0,0 +1,34 @@\n+/*\n+ * Copyright (c) 2014 Nuvoton Technology corporation.\n+ * Copyright 2017 Google, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation;version 2 of the License.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/types.h>\n+#include <asm/mach/arch.h>\n+#include <asm/mach-types.h>\n+#include <asm/mach/map.h>\n+#include <asm/hardware/cache-l2x0.h>\n+\n+#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH |\t\t\t \\\n+\t\t\t L310_AUX_CTRL_DATA_PREFETCH |\t\t\t \\\n+\t\t\t L310_AUX_CTRL_NS_LOCKDOWN |\t\t\t \\\n+\t\t\t L310_AUX_CTRL_CACHE_REPLACE_RR |\t\t \\\n+\t\t\t L2C_AUX_CTRL_SHARED_OVERRIDE |\t\t\t \\\n+\t\t\t L310_AUX_CTRL_FULL_LINE_ZERO)\n+\n+static const char *const npcm7xx_dt_match[] = {\n+\t\"nuvoton,npcm750\",\n+\tNULL\n+};\n+\n+DT_MACHINE_START(NPCM7XX_DT, \"NPCMX50 Chip family\")\n+\t.atag_offset\t= 0x100,\n+\t.dt_compat\t= npcm7xx_dt_match,\n+\t.l2c_aux_val\t= NPCM7XX_AUX_VAL,\n+\t.l2c_aux_mask\t= ~NPCM7XX_AUX_VAL,\n+MACHINE_END\ndiff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c\nnew file mode 100644\nindex 000000000000..4b53adb467fc\n--- /dev/null\n+++ b/arch/arm/mach-npcm/platsmp.c\n@@ -0,0 +1,168 @@\n+/*\n+ * Copyright (C) 2002 ARM Ltd.\n+ * Copyright (C) 2008 STMicroelctronics.\n+ * Copyright (C) 2009 ST-Ericsson.\n+ * Copyright 2017 Google, Inc.\n+ *\n+ * This file is based on arm realview platform\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#define pr_fmt(fmt) \"PLATSMP: \" fmt\n+\n+#include <linux/delay.h>\n+#include <linux/device.h>\n+#include <linux/smp.h>\n+#include <linux/io.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/of_platform.h>\n+#include <linux/of_address.h>\n+#include <asm/cacheflush.h>\n+#include <asm/smp.h>\n+#include <asm/smp_plat.h>\n+#include <asm/smp_scu.h>\n+\n+#define NPCM7XX_SCRPAD_REG 0x13c\n+\n+static void __iomem *gcr_base;\n+static void __iomem *scu_base;\n+\n+/* This is called from headsmp.S to wakeup the secondary core */\n+extern void npcm7xx_secondary_startup(void);\n+extern void npcm7xx_wakeup_z1(void);\n+\n+/*\n+ * Write pen_release in a way that is guaranteed to be visible to all\n+ * observers, irrespective of whether they're taking part in coherency\n+ * or not. This is necessary for the hotplug code to work reliably.\n+ */\n+static void npcm7xx_write_pen_release(int val)\n+{\n+\tpen_release = val;\n+\t/* write to pen_release must be visible to all observers. */\n+\tsmp_wmb();\n+\t__cpuc_flush_dcache_area((void *) &pen_release, sizeof(pen_release));\n+\touter_clean_range(__pa(&pen_release), __pa(&pen_release + 1));\n+}\n+\n+static DEFINE_SPINLOCK(boot_lock);\n+\n+static void npcm7xx_smp_secondary_init(unsigned int cpu)\n+{\n+\t/*\n+\t * let the primary processor know we're out of the\n+\t * pen, then head off into the C entry point\n+\t */\n+\tnpcm7xx_write_pen_release(-1);\n+\n+\t/*\n+\t * Synchronise with the boot thread.\n+\t */\n+\tspin_lock(&boot_lock);\n+\tspin_unlock(&boot_lock);\n+}\n+\n+static int npcm7xx_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)\n+{\n+\tunsigned long timeout;\n+\n+\tif (!gcr_base)\n+\t\treturn -EIO;\n+\n+\t/*\n+\t * set synchronisation state between this boot processor\n+\t * and the secondary one\n+\t */\n+\tspin_lock(&boot_lock);\n+\n+\t/*\n+\t * The secondary processor is waiting to be released from\n+\t * the holding pen - release it, then wait for it to flag\n+\t * that it has been released by resetting pen_release.\n+\t */\n+\tnpcm7xx_write_pen_release(cpu_logical_map(cpu));\n+\tiowrite32(virt_to_phys(npcm7xx_secondary_startup),\n+\t\t gcr_base + NPCM7XX_SCRPAD_REG);\n+\t/* make npcm7xx_secondary_startup visible to all observers. */\n+\tsmp_rmb();\n+\n+\tarch_send_wakeup_ipi_mask(cpumask_of(cpu));\n+\ttimeout = jiffies + (HZ * 1);\n+\twhile (time_before(jiffies, timeout)) {\n+\t\t/* make sure we see any writes to pen_release. */\n+\t\tsmp_rmb();\n+\t\tif (pen_release == -1)\n+\t\t\tbreak;\n+\n+\t\tudelay(10);\n+\t}\n+\n+\t/*\n+\t * now the secondary core is starting up let it run its\n+\t * calibrations, then wait for it to finish\n+\t */\n+\tspin_unlock(&boot_lock);\n+\n+\treturn pen_release != -1 ? -EIO : 0;\n+}\n+\n+\n+static void __init npcm7xx_wakeup_secondary(void)\n+{\n+\t/*\n+\t * write the address of secondary startup into the backup ram register\n+\t * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the\n+\t * backup ram register at offset 0x1FF0, which is what boot rom code\n+\t * is waiting for. This would wake up the secondary core from WFE\n+\t */\n+\tiowrite32(virt_to_phys(npcm7xx_secondary_startup), gcr_base +\n+\t\t NPCM7XX_SCRPAD_REG);\n+\t/* make sure npcm7xx_secondary_startup is seen by all observers. */\n+\tsmp_wmb();\n+\tdsb_sev();\n+\n+\t/* make sure write buffer is drained */\n+\tmb();\n+}\n+\n+static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)\n+{\n+\tstruct device_node *gcr_np, *scu_np;\n+\n+\tgcr_np = of_find_compatible_node(NULL, NULL, \"nuvoton,npcm750-gcr\");\n+\tif (!gcr_np) {\n+\t\tpr_err(\"no gcr device node\\n\");\n+\t\treturn;\n+\t}\n+\tgcr_base = of_iomap(gcr_np, 0);\n+\tif (!gcr_base) {\n+\t\tpr_err(\"could not iomap gcr at: 0x%llx\\n\", gcr_base);\n+\t\treturn;\n+\t}\n+\n+\tscu_np = of_find_compatible_node(NULL, NULL, \"arm,cortex-a9-scu\");\n+\tif (!scu_np) {\n+\t\tpr_err(\"no scu device node\\n\");\n+\t\treturn;\n+\t}\n+\tscu_base = of_iomap(scu_np, 0);\n+\tif (!scu_base) {\n+\t\tpr_err(\"could not iomap gcr at: 0x%llx\\n\", scu_base);\n+\t\treturn;\n+\t}\n+\n+\tscu_enable(scu_base);\n+\tnpcm7xx_wakeup_secondary();\n+}\n+\n+static struct smp_operations npcm7xx_smp_ops __initdata = {\n+\t.smp_prepare_cpus = npcm7xx_smp_prepare_cpus,\n+\t.smp_boot_secondary = npcm7xx_smp_boot_secondary,\n+\t.smp_secondary_init = npcm7xx_smp_secondary_init,\n+};\n+\n+CPU_METHOD_OF_DECLARE(npcm7xx_smp, \"nuvoton,npcm7xx-smp\", &npcm7xx_smp_ops);\n", "prefixes": [ "v2", "1/3" ] }