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GET /api/patches/808449/?format=api
{ "id": 808449, "url": "http://patchwork.ozlabs.org/api/patches/808449/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170831225400.19756-3-brendanhiggins@google.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170831225400.19756-3-brendanhiggins@google.com>", "list_archive_url": null, "date": "2017-08-31T22:53:59", "name": "[v2,2/3] arm: dts: add Nuvoton NPCM750 device tree", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a4067977568d44af45edd1f4dd7f000a60637f3a", "submitter": { "id": 69647, "url": "http://patchwork.ozlabs.org/api/people/69647/?format=api", "name": "Brendan Higgins", "email": "brendanhiggins@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170831225400.19756-3-brendanhiggins@google.com/mbox/", "series": [ { "id": 915, "url": "http://patchwork.ozlabs.org/api/series/915/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=915", "date": "2017-08-31T22:53:57", "name": "arm: npcm: add basic support for Nuvoton BMCs", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/915/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808449/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808449/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=google.com header.i=@google.com\n\theader.b=\"Bo3jjass\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjyPW2ywKz9t2W\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tFri, 1 Sep 2017 08:54:55 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751849AbdHaWy2 (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tThu, 31 Aug 2017 18:54:28 -0400", "from mail-pg0-f44.google.com ([74.125.83.44]:36586 \"EHLO\n\tmail-pg0-f44.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751074AbdHaWyX (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Thu, 31 Aug 2017 18:54:23 -0400", "by mail-pg0-f44.google.com with SMTP id r133so2922512pgr.3\n\tfor <devicetree@vger.kernel.org>;\n\tThu, 31 Aug 2017 15:54:23 -0700 (PDT)", "from mactruck.svl.corp.google.com ([100.123.242.94])\n\tby smtp.gmail.com with ESMTPSA id\n\tm66sm888461pfc.22.2017.08.31.15.54.20\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tThu, 31 Aug 2017 15:54:21 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;\n\ts=20161025; \n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=L/HMq/Ry7hLBz4Lt22s3Ecew1z4s9xSiVQPrGlGREuk=;\n\tb=Bo3jjassc7D7PHF/l0JgJKeOHD/Xl5rVOsiow3k7/qZjjg0j1nixc5Le7nbWDpT4nA\n\tTvkTmQMmj1VEJsHlq9tV7BKlduBOls8SA1KMhb/u1ISRMsrJs1/RxSIr6fp8bLg/e8Zz\n\tO8P0L/VS1u+90DFCxI01rryfnVCkyyUA5hQJ0JGdBscSHXyIUQlMUgruTWNT0stsg5sk\n\trQPKyRhIt/Kaaf1WnEgK+jaZrb7cNG6tQFbg3HflcJr2p14b76FSDxNI1dfW+BdMhujG\n\tc9Tf2tu/Tbf0F/dTAs8C9Qoxn2OsZ4ilE7/u2GjQCmq5YgTp5lE0dRsfdew5LZ50y0lF\n\t0REw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=L/HMq/Ry7hLBz4Lt22s3Ecew1z4s9xSiVQPrGlGREuk=;\n\tb=O/gS0BGDV0odg2dzI8Hk0aiGQcFV2uI6DQnTVSr6Tz+/Aq1EcRCKXXEzKpD/KemCjG\n\tulmZeHZyAg6fj+PesIG+vK6ffYZCHZ0dYvsFTWH5Q2PHpNLWhMjZG7DVBntuHU9WR74a\n\t6ThXiA/j0wqMPwsBnqXu8Fa6FlmzCM3kyyfHmXq3s1T/IR9vMc8ICnNRlJNMGh2OikVE\n\tk6GikIprRgj0weH8bdd5lyPcqzTvbsQBVCl9c3004jkOvYs2XI+LvhhVskmWocCLIKqX\n\tyHavUZrD9EKbRmo/flB+blWKN0xP0OhiFsVviNciPh0wbQ6vGBTLuq5Oas1H/hJY5Kqu\n\t+I7Q==", "X-Gm-Message-State": "AHPjjUg/aaLbHr0Yy6tsX09HnGcALcZne/4vHSWgpApa1HEKyIZe5nAB\n\tv17HlKtY4GfMvDos", "X-Google-Smtp-Source": "ADKCNb5FBsKtwdLEC86x+9wg+OdCpU3dB3W7r3Uq1c+2An7gDNkCGO8uN5ZbOWTpxN0Vp3UdIIH/pA==", "X-Received": "by 10.84.229.69 with SMTP id d5mr43442pln.194.1504220062354;\n\tThu, 31 Aug 2017 15:54:22 -0700 (PDT)", "From": "Brendan Higgins <brendanhiggins@google.com>", "To": "robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk,\n\tavifishman70@gmail.com, tmaimon77@gmail.com, raltherr@google.com", "Cc": "devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, openbmc@lists.ozlabs.org,\n\tBrendan Higgins <brendanhiggins@google.com>", "Subject": "[PATCH v2 2/3] arm: dts: add Nuvoton NPCM750 device tree", "Date": "Thu, 31 Aug 2017 15:53:59 -0700", "Message-Id": "<20170831225400.19756-3-brendanhiggins@google.com>", "X-Mailer": "git-send-email 2.14.1.581.gf28d330327-goog", "In-Reply-To": "<20170831225400.19756-1-brendanhiggins@google.com>", "References": "<20170831225400.19756-1-brendanhiggins@google.com>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Add a common device tree for all Nuvoton NPCM750 BMCs and a board\nspecific device tree for the NPCM750 (Poleg) evaluation board.\n\nSigned-off-by: Brendan Higgins <brendanhiggins@google.com>\n---\n .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 +++++\n .../devicetree/bindings/arm/npcm/npcm.txt | 6 +\n arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 59 +++++++\n arch/arm/boot/dts/nuvoton-npcm750.dtsi | 177 +++++++++++++++++++++\n include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 +++++\n 5 files changed, 323 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt\n create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi\n create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h", "diff": "diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\nnew file mode 100644\nindex 000000000000..e81f85b400cf\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n@@ -0,0 +1,42 @@\n+=========================================================\n+Secondary CPU enable-method \"nuvoton,npcm7xx-smp\" binding\n+=========================================================\n+\n+To apply to all CPUs, a single \"nuvoton,npcm7xx-smp\" enable method should be\n+defined in the \"cpus\" node.\n+\n+Enable method name:\t\"nuvoton,npcm7xx-smp\"\n+Compatible machines:\t\"nuvoton,npcm750\"\n+Compatible CPUs:\t\"arm,cortex-a9\"\n+Related properties:\t(none)\n+\n+Note:\n+This enable method needs valid nodes compatible with \"arm,cortex-a9-scu\" and\n+\"nuvoton,npcm750-gcr\".\n+\n+Example:\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tenable-method = \"nuvoton,npcm7xx-smp\";\n+\n+\t\tcpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a9\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n+\t\t\tclock-names = \"clk_cpu\";\n+\t\t\treg = <0>;\n+\t\t\tnext-level-cache = <&L2>;\n+\t\t};\n+\n+\t\tcpu@1 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a9\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n+\t\t\tclock-names = \"clk_cpu\";\n+\t\t\treg = <1>;\n+\t\t\tnext-level-cache = <&L2>;\n+\t\t};\n+\t};\n+\ndiff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\nnew file mode 100644\nindex 000000000000..2d87d9ecea85\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n@@ -0,0 +1,6 @@\n+NPCM Platforms Device Tree Bindings\n+-----------------------------------\n+NPCM750 SoC\n+Required root node properties:\n+\t- compatible = \"nuvoton,npcm750\";\n+\ndiff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\nnew file mode 100644\nindex 000000000000..54df32cff21b\n--- /dev/null\n+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n@@ -0,0 +1,59 @@\n+/*\n+ * DTS file for all NPCM750 SoCs\n+ *\n+ * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com>\n+ *\n+ * The code contained herein is licensed under the GNU General Public\n+ * License. You may obtain a copy of the GNU General Public License\n+ * Version 2 or later at the following locations:\n+ *\n+ * http://www.opensource.org/licenses/gpl-license.html\n+ * http://www.gnu.org/copyleft/gpl.html\n+ */\n+\n+/dts-v1/;\n+#include \"nuvoton-npcm750.dtsi\"\n+\n+/ {\n+\tmodel = \"Nuvoton npcm750 Development Board (Device Tree)\";\n+\tcompatible = \"nuvoton,npcm750\";\n+\n+\tchosen {\n+\t\tstdout-path = &serial3;\n+\t\tbootargs = \"earlyprintk=serial,serial3,115200\";\n+\t};\n+\n+\tmemory {\n+\t\treg = <0 0x40000000>;\n+\t};\n+\n+\tcpus {\n+\t\tenable-method = \"nuvoton,npcm7xx-smp\";\n+\t};\n+\n+\tclk: clock-controller@f0801000 {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tapb {\n+\t\twatchdog1: watchdog@f0009000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tserial0: serial0@f0001000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tserial1: serial1@f0002000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tserial2: serial2@f0003000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tserial3: serial3@f0004000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\nnew file mode 100644\nindex 000000000000..bca96b3ae9d3\n--- /dev/null\n+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n@@ -0,0 +1,177 @@\n+/*\n+ * DTSi file for the NPCM750 SoC\n+ *\n+ * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com>\n+ *\n+ * The code contained herein is licensed under the GNU General Public\n+ * License. You may obtain a copy of the GNU General Public License\n+ * Version 2 or later at the following locations:\n+ *\n+ * http://www.opensource.org/licenses/gpl-license.html\n+ * http://www.gnu.org/copyleft/gpl.html\n+ */\n+\n+#include \"skeleton.dtsi\"\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/clock/nuvoton,npcm7xx-clks.h>\n+\n+/ {\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\tinterrupt-parent = <&gic>;\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a9\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n+\t\t\tclock-names = \"clk_cpu\";\n+\t\t\treg = <0>;\n+\t\t\tnext-level-cache = <&l2>;\n+\t\t};\n+\n+\t\tcpu@1 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a9\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n+\t\t\tclock-names = \"clk_cpu\";\n+\t\t\treg = <1>;\n+\t\t\tnext-level-cache = <&l2>;\n+\t\t};\n+\t};\n+\n+\tgcr: gcr@f0800000 {\n+\t\tcompatible = \"nuvoton,npcm750-gcr\", \"syscon\",\n+\t\t\t\"simple-mfd\";\n+\t\treg = <0xf0800000 0x1000>;\n+\t};\n+\n+\tscu: scu@f03fe000 {\n+\t\tcompatible = \"arm,cortex-a9-scu\";\n+\t\treg = <0xf03fe000 0x1000>;\n+\t};\n+\n+\tl2: l2-cache@f03fc000 {\n+\t\tcompatible = \"arm,pl310-cache\";\n+\t\treg = <0xf03fc000 0x1000>;\n+\t\tinterrupts = <0 21 4>;\n+\t\tcache-unified;\n+\t\tcache-level = <2>;\n+\t\tclocks = <&clk NPCM7XX_CLK_AXI>;\n+\t};\n+\n+\tgic: interrupt-controller@f03ff000 {\n+\t\tcompatible = \"arm,cortex-a9-gic\";\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <3>;\n+\t\treg = <0xf03ff000 0x1000>,\n+\t\t <0xf03fe100 0x100>;\n+\t};\n+\n+\tclk: clock-controller@f0801000 {\n+\t\tcompatible = \"nuvoton,npcm750-clk\";\n+\t\t#clock-cells = <1>;\n+\t\treg = <0xf0801000 0x1000>;\n+\t};\n+\n+\t/* external clock signal rg1refck, supplied by the phy */\n+\tclk-rg1refck {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <125000000>;\n+\t};\n+\n+\t/* external clock signal rg2refck, supplied by the phy */\n+\tclk-rg2refck {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <125000000>;\n+\t};\n+\n+\tclk-xin {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <50000000>;\n+\t};\n+\n+\ttimer@f03fe600 {\n+\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n+\t\treg = <0xf03fe600 0x20>;\n+\t\tinterrupts = <1 13 0x304>;\n+\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n+\t};\n+\n+\tapb {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"simple-bus\";\n+\t\tinterrupt-parent = <&gic>;\n+\t\tranges;\n+\n+\t\ttimer0: timer@f0000000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-timer\";\n+\t\t\tinterrupts = <0 32 4>;\n+\t\t\treg = <0xf0000000 0x1000>;\n+\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n+\t\t};\n+\n+\t\twatchdog0: watchdog@f0008000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n+\t\t\tinterrupts = <0 47 4>;\n+\t\t\treg = <0xf0008000 0x1000>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n+\t\t};\n+\n+\t\twatchdog1: watchdog@f0009000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n+\t\t\tinterrupts = <0 48 4>;\n+\t\t\treg = <0xf0009000 0x1000>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n+\t\t};\n+\n+\t\twatchdog2: watchdog@f000a000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n+\t\t\tinterrupts = <0 49 4>;\n+\t\t\treg = <0xf000a000 0x1000>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n+\t\t};\n+\n+\t\tserial0: serial0@f0001000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n+\t\t\treg = <0xf0001000 0x1000>;\n+\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n+\t\t\tinterrupts = <0 2 4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tserial1: serial1@f0002000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n+\t\t\treg = <0xf0002000 0x1000>;\n+\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n+\t\t\tinterrupts = <0 3 4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tserial2: serial2@f0003000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n+\t\t\treg = <0xf0003000 0x1000>;\n+\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n+\t\t\tinterrupts = <0 4 4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tserial3: serial3@f0004000 {\n+\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n+\t\t\treg = <0xf0004000 0x1000>;\n+\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n+\t\t\tinterrupts = <0 5 4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+};\ndiff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\nnew file mode 100644\nindex 000000000000..c69d3bbf7e42\n--- /dev/null\n+++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n@@ -0,0 +1,39 @@\n+/*\n+ * Copyright (C) 2016 Nuvoton Technologies, tali.perry@nuvoton.com\n+ *\n+ * This software is licensed under the terms of the GNU General Public\n+ * License version 2, as published by the Free Software Foundation, and\n+ * may be copied, distributed, and modified under those terms.\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_NPCM7XX_H\n+#define _DT_BINDINGS_CLK_NPCM7XX_H\n+\n+#define NPCM7XX_CLK_PLL0\t0\n+#define NPCM7XX_CLK_PLL1\t1\n+#define NPCM7XX_CLK_PLL2\t2\n+#define NPCM7XX_CLK_GFX\t\t3\n+#define NPCM7XX_CLK_APB1\t4\n+#define NPCM7XX_CLK_APB2\t5\n+#define NPCM7XX_CLK_APB3\t6\n+#define NPCM7XX_CLK_APB4\t7\n+#define NPCM7XX_CLK_APB5\t8\n+#define NPCM7XX_CLK_MC\t\t9\n+#define NPCM7XX_CLK_CPU\t\t10\n+#define NPCM7XX_CLK_SPI0\t11\n+#define NPCM7XX_CLK_SPI3\t12\n+#define NPCM7XX_CLK_SPIX\t13\n+#define NPCM7XX_CLK_UART_CORE\t14\n+#define NPCM7XX_CLK_TIMER\t15\n+#define NPCM7XX_CLK_HOST_UART\t16\n+#define NPCM7XX_CLK_MMC\t\t17\n+#define NPCM7XX_CLK_SDHC\t18\n+#define NPCM7XX_CLK_ADC\t\t19\n+#define NPCM7XX_CLK_GFX_MEM\t20\n+#define NPCM7XX_CLK_USB_BRIDGE\t21\n+#define NPCM7XX_CLK_AXI\t\t22\n+#define NPCM7XX_CLK_AHB\t\t23\n+#define NPCM7XX_CLK_EMC\t\t24\n+#define NPCM7XX_CLK_GMAC\t25\n+\n+#endif\n", "prefixes": [ "v2", "2/3" ] }