Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/808370/?format=api
{ "id": 808370, "url": "http://patchwork.ozlabs.org/api/patches/808370/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-22-git-send-email-Dave.Martin@arm.com/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504198860-12951-22-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-08-31T17:00:53", "name": "[v2,21/28] arm64/sve: Add sysctl to set the default vector length for new processes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "94071d7734196911838e458da4f296b31c352cec", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-22-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 882, "url": "http://patchwork.ozlabs.org/api/series/882/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=882", "date": "2017-08-31T17:00:32", "name": "ARM Scalable Vector Extension (SVE)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/882/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808370/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808370/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<libc-alpha-return-83991-incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list libc-alpha@sourceware.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-83991-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"upn1v/Sy\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjpyl1b2Fz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 1 Sep 2017 03:19:43 +1000 (AEST)", "(qmail 20810 invoked by alias); 31 Aug 2017 17:19:18 -0000", "(qmail 20629 invoked by uid 89); 31 Aug 2017 17:19:17 -0000" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=a27U91khCVk+IJaqMuhKFwyHfXzkw59mBB1WhS9krZE\n\t0XWl+kmup2R2gPY8inphYi4Yk27L8Px3kotU47/Q9yQOWseK16aD+1VAqbhB4V1i\n\t1cS7Z+ncj/IEbIHaGwVV8rM7rsfj2dp4bMdn0kMF0pdO72csUFkrgADU3tMfJ4iQ\n\t=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=VEvsZvtzGorwTIVdExsbN79BjWg=; b=upn1v/SyaXLN7C91F\n\t7056qLFoCnuW0VIovhsULbyZ4kgsvHw0Dwpua4ShbAUekTOcDe2fwBk6WIpg0BqP\n\tEhxKgu2MrFekDWH/OT4S7WuplqXq70FKdBNS/UsxTU9d37m3FXDyxZ72PNJWhaID\n\tT187jcu8V/e3qejTGz0oGihbMQ=", "Mailing-List": "contact libc-alpha-help@sourceware.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<libc-alpha.sourceware.org>", "List-Unsubscribe": "<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>", "List-Subscribe": "<mailto:libc-alpha-subscribe@sourceware.org>", "List-Archive": "<http://sourceware.org/ml/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>", "Sender": "libc-alpha-owner@sourceware.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=", "X-HELO": "foss.arm.com", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Cc": "Catalin Marinas <catalin.marinas@arm.com>, Will Deacon\n\t<will.deacon@arm.com>, \tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= <alex.bennee@linaro.org>,\n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, Richard Sandiford\n\t<richard.sandiford@arm.com>, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org", "Subject": "[PATCH v2 21/28] arm64/sve: Add sysctl to set the default vector\n\tlength for new processes", "Date": "Thu, 31 Aug 2017 18:00:53 +0100", "Message-Id": "<1504198860-12951-22-git-send-email-Dave.Martin@arm.com>", "In-Reply-To": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "References": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit" }, "content": "Because of the effect of SVE on the size of the signal frame, the\ndefault vector length used for new processes involves a tradeoff\nbetween performance of SVE-enabled software on the one hand, and\nreliability of non-SVE-aware software on the other hand.\n\nFor this reason, the best choice depends on the repertoire of\nuserspace software in use and is thus best left up to distro\nmaintainers, sysadmins and developers.\n\nIf CONFIG_SYSCTL is enabled, this patch exposes the default vector\nlength in /proc/sys/abi/sve_default_vector_length, where boot\nscripts or the adventurous can poke it.\n\nIn common with other arm64 ABI sysctls, this control is currently\nglobal: setting it requires CAP_SYS_ADMIN in the root user\nnamespace, but the value set is effective for subsequent execs in\nall namespaces. The control only affects _new_ processes, however:\nchanging it does not affect the vector length of any existing\nprocess.\n\nThe intended usage model is that if userspace is known to be fully\nSVE-tolerant (or a developer is curious to find out) then init\nscripts can crank this up during startup.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nCc: Alex Bennée <alex.bennee@linaro.org>\n\n---\n\nChanges since v1\n----------------\n\nChanges requested by Alex Bennée:\n\n* Thin out BUG_ON()s:\nRedundant BUG_ON()s and ones that just check invariants are removed.\nImportant sanity-checks are migrated to WARN_ON()s, with some\nminimal best-effort patch-up code.\n---\n arch/arm64/kernel/fpsimd.c | 62 +++++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 61 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\nindex 42e8331..b430ee0 100644\n--- a/arch/arm64/kernel/fpsimd.c\n+++ b/arch/arm64/kernel/fpsimd.c\n@@ -34,6 +34,7 @@\n #include <linux/sched/signal.h>\n #include <linux/signal.h>\n #include <linux/slab.h>\n+#include <linux/sysctl.h>\n \n #include <asm/fpsimd.h>\n #include <asm/cputype.h>\n@@ -244,6 +245,65 @@ static unsigned int find_supported_vector_length(unsigned int vl)\n \treturn sve_vl_from_vq(bit_to_vq(bit));\n }\n \n+#ifdef CONFIG_SYSCTL\n+\n+static int sve_proc_do_default_vl(struct ctl_table *table, int write,\n+\t\t\t\t void __user *buffer, size_t *lenp,\n+\t\t\t\t loff_t *ppos)\n+{\n+\tint ret;\n+\tint vl = sve_default_vl;\n+\tstruct ctl_table tmp_table = {\n+\t\t.data = &vl,\n+\t\t.maxlen = sizeof(vl),\n+\t};\n+\n+\tret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos);\n+\tif (ret || !write)\n+\t\treturn ret;\n+\n+\t/* Writing -1 has the special meaning \"set to max\": */\n+\tif (vl == -1) {\n+\t\t/* Fail safe if sve_max_vl wasn't initialised */\n+\t\tif (WARN_ON(!sve_vl_valid(sve_max_vl)))\n+\t\t\tvl = SVE_VL_MIN;\n+\t\telse\n+\t\t\tvl = sve_max_vl;\n+\n+\t\tgoto chosen;\n+\t}\n+\n+\tif (!sve_vl_valid(vl))\n+\t\treturn -EINVAL;\n+\n+\tvl = find_supported_vector_length(vl);\n+chosen:\n+\tsve_default_vl = vl;\n+\treturn 0;\n+}\n+\n+static struct ctl_table sve_default_vl_table[] = {\n+\t{\n+\t\t.procname\t= \"sve_default_vector_length\",\n+\t\t.mode\t\t= 0644,\n+\t\t.proc_handler\t= sve_proc_do_default_vl,\n+\t},\n+\t{ }\n+};\n+\n+static int __init sve_sysctl_init(void)\n+{\n+\tif (system_supports_sve())\n+\t\tif (!register_sysctl(\"abi\", sve_default_vl_table))\n+\t\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+#else /* ! CONFIG_SYSCTL */\n+static int __init sve_sysctl_init(void) { return 0; }\n+#endif /* ! CONFIG_SYSCTL */\n+\n #define ZREG(sve_state, vq, n) ((char *)(sve_state) +\t\t\\\n \t(SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))\n \n@@ -1030,6 +1090,6 @@ static int __init fpsimd_init(void)\n \tif (!(elf_hwcap & HWCAP_ASIMD))\n \t\tpr_notice(\"Advanced SIMD is not implemented\\n\");\n \n-\treturn 0;\n+\treturn sve_sysctl_init();\n }\n late_initcall(fpsimd_init);\n", "prefixes": [ "v2", "21/28" ] }