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GET /api/patches/808369/?format=api
{ "id": 808369, "url": "http://patchwork.ozlabs.org/api/patches/808369/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-11-git-send-email-Dave.Martin@arm.com/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504198860-12951-11-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-08-31T17:00:42", "name": "[v2,10/28] arm64/sve: Low-level CPU setup", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6b548e710ce00b91ee69bc3ccdde8b283e721e24", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-11-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 882, "url": "http://patchwork.ozlabs.org/api/series/882/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=882", "date": "2017-08-31T17:00:32", "name": "ARM Scalable Vector Extension (SVE)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/882/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808369/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808369/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<libc-alpha-return-83990-incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list libc-alpha@sourceware.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-83990-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"AV9zUgjQ\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjpyW1wX2z9sD5\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 1 Sep 2017 03:19:31 +1000 (AEST)", "(qmail 20708 invoked by alias); 31 Aug 2017 17:19:18 -0000", "(qmail 20627 invoked by uid 89); 31 Aug 2017 17:19:17 -0000" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=U81XdCMqUxV+q6Mu9ZMWNhNrL0E4cPOYQR29BgS73L+\n\tWLExV63N45a8JIcVvj2hkj6GpSkVgdO2qdpI6O5tErOP+oPhO0d/eNMqpb5/T0Zq\n\teAH2Hb2clhslSTm68U0ggTlxj+6mC8HpQ2a31WpIIz0mLJYl6dIF+ERpeT5HYLyk\n\t=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=asaHPi9ZlxKrecAfsAYVE+Tgzc8=; b=AV9zUgjQdewwc+3O5\n\tFeHhb/c/tHPHEPOrp35sUi5HvTy5j75tOpwmj+3fZsC3of8kzVu9LjIrzEEMqQ0n\n\tEyacK4dTFjXBPVm02/A/N1qZSkIa0diVjJ7WCWmP0dboOUkB5p4bzFVu8FiVwlWy\n\tplJ5v33CQNYdgk4XMOn5IoAn+4=", "Mailing-List": "contact libc-alpha-help@sourceware.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<libc-alpha.sourceware.org>", "List-Unsubscribe": "<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>", "List-Subscribe": "<mailto:libc-alpha-subscribe@sourceware.org>", "List-Archive": "<http://sourceware.org/ml/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>", "Sender": "libc-alpha-owner@sourceware.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=", "X-HELO": "foss.arm.com", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Cc": "Catalin Marinas <catalin.marinas@arm.com>, Will Deacon\n\t<will.deacon@arm.com>, \tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= <alex.bennee@linaro.org>,\n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, Richard Sandiford\n\t<richard.sandiford@arm.com>, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org", "Subject": "[PATCH v2 10/28] arm64/sve: Low-level CPU setup", "Date": "Thu, 31 Aug 2017 18:00:42 +0100", "Message-Id": "<1504198860-12951-11-git-send-email-Dave.Martin@arm.com>", "In-Reply-To": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "References": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit" }, "content": "To enable the kernel to use SVE, all SVE traps from EL1 must be\ndisabled. To take maximum advantage of the hardware, the full\navailable vector length also needs to be enabled for EL1 by\nprogramming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as\nrequired, but this cannot override the limit set by ZCR_EL2.)\n\nIn advance of full SVE support being implemented for userspace, it\nalso necessary to ensure that SVE traps from EL0 are enabled.\n\nThis patch makes the appropriate changes to the primary and\nsecondary CPU initialisation code.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\n---\n arch/arm64/kernel/head.S | 13 ++++++++++++-\n arch/arm64/mm/proc.S | 14 ++++++++++++--\n 2 files changed, 24 insertions(+), 3 deletions(-)", "diff": "diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S\nindex 7434ec0..f411f71 100644\n--- a/arch/arm64/kernel/head.S\n+++ b/arch/arm64/kernel/head.S\n@@ -516,8 +516,19 @@ CPU_LE(\tmovk\tx0, #0x30d0, lsl #16\t)\t// Clear EE and E0E on LE systems\n \tmov\tx0, #0x33ff\n \tmsr\tcptr_el2, x0\t\t\t// Disable copro. traps to EL2\n \n+\t/* SVE register access */\n+\tmrs\tx1, id_aa64pfr0_el1\n+\tubfx\tx1, x1, #ID_AA64PFR0_SVE_SHIFT, #4\n+\tcbz\tx1, 7f\n+\n+\tbic\tx0, x0, #CPTR_EL2_TZ\t\t// Also disable SVE traps\n+\tmsr\tcptr_el2, x0\t\t\t// Disable copro. traps to EL2\n+\tisb\n+\tmov\tx1, #ZCR_ELx_LEN_MASK\t\t// SVE: Enable full vector\n+\tmsr_s\tSYS_ZCR_EL2, x1\t\t\t// length for EL1.\n+\n \t/* Hypervisor stub */\n-\tadr_l\tx0, __hyp_stub_vectors\n+7:\tadr_l\tx0, __hyp_stub_vectors\n \tmsr\tvbar_el2, x0\n \n \t/* spsr */\ndiff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S\nindex 877d42f..dd22ef2 100644\n--- a/arch/arm64/mm/proc.S\n+++ b/arch/arm64/mm/proc.S\n@@ -27,6 +27,7 @@\n #include <asm/pgtable-hwdef.h>\n #include <asm/cpufeature.h>\n #include <asm/alternative.h>\n+#include <asm/sysreg.h>\n \n #ifdef CONFIG_ARM64_64K_PAGES\n #define TCR_TG_FLAGS\tTCR_TG0_64K | TCR_TG1_64K\n@@ -186,8 +187,17 @@ ENTRY(__cpu_setup)\n \ttlbi\tvmalle1\t\t\t\t// Invalidate local TLB\n \tdsb\tnsh\n \n-\tmov\tx0, #3 << 20\n-\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n+\tmov\tx0, #3 << 20\t\t\t// FEN\n+\n+\t/* SVE */\n+\tmrs\tx5, id_aa64pfr0_el1\n+\tubfx\tx5, x5, #ID_AA64PFR0_SVE_SHIFT, #4\n+\tcbz\tx5, 1f\n+\n+\tbic\tx0, x0, #CPACR_EL1_ZEN\n+\torr\tx0, x0, #CPACR_EL1_ZEN_EL1EN\t// SVE: trap for EL0, not EL1\n+1:\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n+\n \tmov\tx0, #1 << 12\t\t\t// Reset mdscr_el1 and disable\n \tmsr\tmdscr_el1, x0\t\t\t// access to the DCC from EL0\n \tisb\t\t\t\t\t// Unmask debug exceptions now,\n", "prefixes": [ "v2", "10/28" ] }