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GET /api/patches/808363/?format=api
{ "id": 808363, "url": "http://patchwork.ozlabs.org/api/patches/808363/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-23-git-send-email-Dave.Martin@arm.com/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504198860-12951-23-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-08-31T17:00:54", "name": "[v2,22/28] arm64/sve: KVM: Prevent guests from using SVE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3bf3a42fe72b647ffa86c26b7687968e35d94687", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-23-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 882, "url": "http://patchwork.ozlabs.org/api/series/882/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=882", "date": "2017-08-31T17:00:32", "name": "ARM Scalable Vector Extension (SVE)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/882/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808363/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808363/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<libc-alpha-return-83987-incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list libc-alpha@sourceware.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-83987-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"VAXlTy7S\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjplz2bMFz9sD5\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 1 Sep 2017 03:10:23 +1000 (AEST)", "(qmail 124019 invoked by alias); 31 Aug 2017 17:09:29 -0000", "(qmail 123942 invoked by uid 89); 31 Aug 2017 17:09:29 -0000" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references; q=dns; s=default; b=nH1tjd+C/YFzEImrTQzov3uLmd9sgUY\n\tgbmsVa6fN7oQVYotvQOtHHUMw/Bt4sBAugpOXw6fsQ7jMFQBn6YIgW/6+zXe/9Ka\n\t6+wtxKe50agReVGKpewMQrtPxeUIJ8wMSbnhnMLmdCw87oLR9MMLVA0TyfIQjdfa\n\tSRobsF5/v+xE=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references; s=default; bh=iKiji02aFponh2bmwbdfEPjvibk=; b=VAXlT\n\ty7SShyS4E2I17DZvqcsKZrCj6xML9iokWKoHGC9H7gwSJC9GKAvIg/OTh7UbuxBU\n\tSxb/IKzei3iNEzlJC67SyEfCQmAZxeIMSn12yWIqCsqfCSgBKbTYofBgy4Acopln\n\tVoQrCY9AqItwAlfzKf+Ip/Aa4CPYM7M8Aacb2E=", "Mailing-List": "contact libc-alpha-help@sourceware.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<libc-alpha.sourceware.org>", "List-Unsubscribe": "<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>", "List-Subscribe": "<mailto:libc-alpha-subscribe@sourceware.org>", "List-Archive": "<http://sourceware.org/ml/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>", "Sender": "libc-alpha-owner@sourceware.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=survive", "X-HELO": "foss.arm.com", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Cc": "Catalin Marinas <catalin.marinas@arm.com>, Will Deacon\n\t<will.deacon@arm.com>, \tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= <alex.bennee@linaro.org>,\n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, Richard Sandiford\n\t<richard.sandiford@arm.com>, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org, Christoffer Dall\n\t<christoffer.dall@linaro.org>, \tMarc Zyngier <marc.zyngier@arm.com>", "Subject": "[PATCH v2 22/28] arm64/sve: KVM: Prevent guests from using SVE", "Date": "Thu, 31 Aug 2017 18:00:54 +0100", "Message-Id": "<1504198860-12951-23-git-send-email-Dave.Martin@arm.com>", "In-Reply-To": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "References": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>" }, "content": "Until KVM has full SVE support, guests must not be allowed to\nexecute SVE instructions.\n\nThis patch enables the necessary traps, and also ensures that the\ntraps are disabled again on exit from the guest so that the host\ncan still use SVE if it wants to.\n\nThis patch introduces another instance of\n__this_cpu_write(fpsimd_last_state, NULL), so this flush operation\nis abstracted out as a separate helper fpsimd_flush_cpu_state().\nOther instances are ported appropriately.\n\nAs a side effect of this refactoring, a this_cpu_write() in\nfpsimd_cpu_pm_notifier() is changed to __this_cpu_write(). This\nshould be fine, since cpu_pm_enter() is supposed to be called only\nwith interrupts disabled.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nCc: Marc Zyngier <marc.zyngier@arm.com>\nCc: Ard Biesheuvel <ard.biesheuvel@linaro.org>\n\n---\n\nChanges since v1\n----------------\n\nRequested by Marc Zyngier:\n\n* Avoid the verbose arithmetic for CPTR_EL2_DEFAULT, and just\ndescribe it in terms of the set of bits known to be RES1 in\nCPTR_EL2.\n\nOther:\n\n* Fixup to drop task SVE state cached in the CPU registers across\nguest entry/exit.\n\nWithout this, we may enter an EL0 process with wrong data in the\nextended SVE bits and/or wrong trap configuration.\n\nThis is not a problem for the FPSIMD part of the state because KVM\nexplicitly restores the host FPSIMD state on guest exit; but this\nrestore is sufficient to corrupt the extra SVE bits even if nothing\nelse does.\n\n* The fpsimd_flush_cpu_state() function, which was supposed to abstract\nthe underlying flush operation, wasn't used. [sparse]\n\nThis patch is now ported to use it. Other users of the same idiom are\nported too (which was the original intention).\n\nfpsimd_flush_cpu_state() is marked inline, since all users are\nifdef'd and the function may be unused. Plus, it's trivially\nsuitable for inlining.\n---\n arch/arm/include/asm/kvm_host.h | 3 +++\n arch/arm64/include/asm/fpsimd.h | 1 +\n arch/arm64/include/asm/kvm_arm.h | 4 +++-\n arch/arm64/include/asm/kvm_host.h | 11 +++++++++++\n arch/arm64/kernel/fpsimd.c | 31 +++++++++++++++++++++++++++++--\n arch/arm64/kvm/hyp/switch.c | 6 +++---\n virt/kvm/arm/arm.c | 3 +++\n 7 files changed, 53 insertions(+), 6 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h\nindex 127e2dd..fa4a442 100644\n--- a/arch/arm/include/asm/kvm_host.h\n+++ b/arch/arm/include/asm/kvm_host.h\n@@ -299,4 +299,7 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,\n int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,\n \t\t\t struct kvm_device_attr *attr);\n \n+/* All host FP/SIMD state is restored on guest exit, so nothing to save: */\n+static inline void kvm_fpsimd_flush_cpu_state(void) {}\n+\n #endif /* __ARM_KVM_HOST_H__ */\ndiff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\nindex d084968..5605fc1 100644\n--- a/arch/arm64/include/asm/fpsimd.h\n+++ b/arch/arm64/include/asm/fpsimd.h\n@@ -74,6 +74,7 @@ extern void fpsimd_restore_current_state(void);\n extern void fpsimd_update_current_state(struct fpsimd_state *state);\n \n extern void fpsimd_flush_task_state(struct task_struct *target);\n+extern void sve_flush_cpu_state(void);\n \n /* Maximum VL that SVE VL-agnostic software can transparently support */\n #define SVE_VL_ARCH_MAX 0x100\ndiff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h\nindex dbf0537..7f069ff 100644\n--- a/arch/arm64/include/asm/kvm_arm.h\n+++ b/arch/arm64/include/asm/kvm_arm.h\n@@ -186,7 +186,8 @@\n #define CPTR_EL2_TTA\t(1 << 20)\n #define CPTR_EL2_TFP\t(1 << CPTR_EL2_TFP_SHIFT)\n #define CPTR_EL2_TZ\t(1 << 8)\n-#define CPTR_EL2_DEFAULT\t0x000033ff\n+#define CPTR_EL2_RES1\t0x000032ff /* known RES1 bits in CPTR_EL2 */\n+#define CPTR_EL2_DEFAULT\tCPTR_EL2_RES1\n \n /* Hyp Debug Configuration Register bits */\n #define MDCR_EL2_TPMS\t\t(1 << 14)\n@@ -237,5 +238,6 @@\n \n #define CPACR_EL1_FPEN\t\t(3 << 20)\n #define CPACR_EL1_TTA\t\t(1 << 28)\n+#define CPACR_EL1_DEFAULT\t(CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN)\n \n #endif /* __ARM64_KVM_ARM_H__ */\ndiff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h\nindex d686300..05d8373 100644\n--- a/arch/arm64/include/asm/kvm_host.h\n+++ b/arch/arm64/include/asm/kvm_host.h\n@@ -25,6 +25,7 @@\n #include <linux/types.h>\n #include <linux/kvm_types.h>\n #include <asm/cpufeature.h>\n+#include <asm/fpsimd.h>\n #include <asm/kvm.h>\n #include <asm/kvm_asm.h>\n #include <asm/kvm_mmio.h>\n@@ -390,4 +391,14 @@ static inline void __cpu_init_stage2(void)\n \t\t \"PARange is %d bits, unsupported configuration!\", parange);\n }\n \n+/*\n+ * All host FP/SIMD state is restored on guest exit, so nothing needs\n+ * doing here except in the SVE case:\n+*/\n+static inline void kvm_fpsimd_flush_cpu_state(void)\n+{\n+\tif (system_supports_sve())\n+\t\tsve_flush_cpu_state();\n+}\n+\n #endif /* __ARM64_KVM_HOST_H__ */\ndiff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\nindex b430ee0..7837ced 100644\n--- a/arch/arm64/kernel/fpsimd.c\n+++ b/arch/arm64/kernel/fpsimd.c\n@@ -875,6 +875,33 @@ void fpsimd_flush_task_state(struct task_struct *t)\n \tt->thread.fpsimd_state.cpu = NR_CPUS;\n }\n \n+static inline void fpsimd_flush_cpu_state(void)\n+{\n+\t__this_cpu_write(fpsimd_last_state, NULL);\n+}\n+\n+/*\n+ * Invalidate any task SVE state currently held in this CPU's regs.\n+ *\n+ * This is used to prevent the kernel from trying to reuse SVE register data\n+ * that is detroyed by KVM guest enter/exit. This function should go away when\n+ * KVM SVE support is implemented. Don't use it for anything else.\n+ */\n+#ifdef CONFIG_ARM64_SVE\n+void sve_flush_cpu_state(void)\n+{\n+\tstruct fpsimd_state *const fpstate = __this_cpu_read(fpsimd_last_state);\n+\tstruct task_struct *tsk;\n+\n+\tif (!fpstate)\n+\t\treturn;\n+\n+\ttsk = container_of(fpstate, struct task_struct, thread.fpsimd_state);\n+\tif (test_tsk_thread_flag(tsk, TIF_SVE))\n+\t\tfpsimd_flush_cpu_state();\n+}\n+#endif /* CONFIG_ARM64_SVE */\n+\n #ifdef CONFIG_KERNEL_MODE_NEON\n \n DEFINE_PER_CPU(bool, kernel_neon_busy);\n@@ -915,7 +942,7 @@ void kernel_neon_begin(void)\n \t}\n \n \t/* Invalidate any task state remaining in the fpsimd regs: */\n-\t__this_cpu_write(fpsimd_last_state, NULL);\n+\tfpsimd_flush_cpu_state();\n \n \tpreempt_disable();\n \n@@ -1032,7 +1059,7 @@ static int fpsimd_cpu_pm_notifier(struct notifier_block *self,\n \tcase CPU_PM_ENTER:\n \t\tif (current->mm)\n \t\t\ttask_fpsimd_save();\n-\t\tthis_cpu_write(fpsimd_last_state, NULL);\n+\t\tfpsimd_flush_cpu_state();\n \t\tbreak;\n \tcase CPU_PM_EXIT:\n \t\tif (current->mm)\ndiff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c\nindex 35a90b8..951f3eb 100644\n--- a/arch/arm64/kvm/hyp/switch.c\n+++ b/arch/arm64/kvm/hyp/switch.c\n@@ -48,7 +48,7 @@ static void __hyp_text __activate_traps_vhe(void)\n \n \tval = read_sysreg(cpacr_el1);\n \tval |= CPACR_EL1_TTA;\n-\tval &= ~CPACR_EL1_FPEN;\n+\tval &= ~(CPACR_EL1_FPEN | CPACR_EL1_ZEN);\n \twrite_sysreg(val, cpacr_el1);\n \n \twrite_sysreg(__kvm_hyp_vector, vbar_el1);\n@@ -59,7 +59,7 @@ static void __hyp_text __activate_traps_nvhe(void)\n \tu64 val;\n \n \tval = CPTR_EL2_DEFAULT;\n-\tval |= CPTR_EL2_TTA | CPTR_EL2_TFP;\n+\tval |= CPTR_EL2_TTA | CPTR_EL2_TFP | CPTR_EL2_TZ;\n \twrite_sysreg(val, cptr_el2);\n }\n \n@@ -117,7 +117,7 @@ static void __hyp_text __deactivate_traps_vhe(void)\n \n \twrite_sysreg(mdcr_el2, mdcr_el2);\n \twrite_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);\n-\twrite_sysreg(CPACR_EL1_FPEN, cpacr_el1);\n+\twrite_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);\n \twrite_sysreg(vectors, vbar_el1);\n }\n \ndiff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c\nindex a39a1e1..af9f5da 100644\n--- a/virt/kvm/arm/arm.c\n+++ b/virt/kvm/arm/arm.c\n@@ -647,6 +647,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)\n \t\t */\n \t\tpreempt_disable();\n \n+\t\t/* Flush FP/SIMD state that can't survive guest entry/exit */\n+\t\tkvm_fpsimd_flush_cpu_state();\n+\n \t\tkvm_pmu_flush_hwstate(vcpu);\n \n \t\tkvm_timer_flush_hwstate(vcpu);\n", "prefixes": [ "v2", "22/28" ] }