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GET /api/patches/808358/?format=api
{ "id": 808358, "url": "http://patchwork.ozlabs.org/api/patches/808358/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-15-git-send-email-Dave.Martin@arm.com/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504198860-12951-15-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-08-31T17:00:46", "name": "[v2,14/28] arm64/sve: Backend logic for setting the vector length", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2af224511f62be2629c6bc5789826c0581057b95", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-15-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 882, "url": "http://patchwork.ozlabs.org/api/series/882/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=882", "date": "2017-08-31T17:00:32", "name": "ARM Scalable Vector Extension (SVE)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/882/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808358/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808358/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<libc-alpha-return-83984-incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list libc-alpha@sourceware.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-83984-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"JkVc0HL6\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjpl92vnZz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 1 Sep 2017 03:09:41 +1000 (AEST)", "(qmail 122248 invoked by alias); 31 Aug 2017 17:09:18 -0000", "(qmail 122129 invoked by uid 89); 31 Aug 2017 17:09:17 -0000" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=GbsJ/GC648UbHR12PQxtMbdTTGAMtdDz7SRK7DWUz9d\n\tlQqRtXZlMx0SRFHRBPYy8UYiO2xeqKKyiTab7iZvNbS8pJJRTL7iPAF7C46+tdfJ\n\tOXoV5v3Ts6Z2lH5RE0tEePxA7fzot/0W1ua6/xz0NwsaSIcug2t4ybX8bKfHgJoU\n\t=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=sVoXrBia3Ok5F7bBGbvpgsFl8a4=; b=JkVc0HL6MduofjY1W\n\t4kOsr4rUUdYD+MBH7uDVHHSXJ+MJNxwZeila95L3gSeGWw4f2aOv5e4deavIlK2c\n\tfpshLsFPZoyjAZtu98ICaAg54RVmV6dkKM3TszBvfAw1Wt7RXEfFrolwBW2Q+Mkr\n\t4cHqznA2z/qYvBYfjxno803Ccg=", "Mailing-List": "contact libc-alpha-help@sourceware.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<libc-alpha.sourceware.org>", "List-Unsubscribe": "<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>", "List-Subscribe": "<mailto:libc-alpha-subscribe@sourceware.org>", "List-Archive": "<http://sourceware.org/ml/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>", "Sender": "libc-alpha-owner@sourceware.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=", "X-Spam-User": "qpsmtpd, 2 recipients", "X-HELO": "foss.arm.com", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Cc": "Catalin Marinas <catalin.marinas@arm.com>, Will Deacon\n\t<will.deacon@arm.com>, \tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= <alex.bennee@linaro.org>,\n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, Richard Sandiford\n\t<richard.sandiford@arm.com>, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org,\n\tgdb@sourceware.org, \tAlan Hayward <alan.hayward@arm.com>,\n\tYao Qi <Yao.Qi@arm.com>", "Subject": "[PATCH v2 14/28] arm64/sve: Backend logic for setting the vector\n\tlength", "Date": "Thu, 31 Aug 2017 18:00:46 +0100", "Message-Id": "<1504198860-12951-15-git-send-email-Dave.Martin@arm.com>", "In-Reply-To": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "References": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit" }, "content": "This patch implements the core logic for changing a task's vector\nlength on request from userspace. This will be used by the ptrace\nand prctl frontends that are implemented in later patches.\n\nThe SVE architecture permits, but does not require, implementations\nto support vector lengths that are not a power of two. To handle\nthis, logic is added to check a requested vector length against a\npossibly sparse bitmap of available vector lengths at runtime, so\nthat the best supported value can be chosen.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nCc: Alex Bennée <alex.bennee@linaro.org>\n\n---\n\nChanges since v1\n----------------\n\nRequested by Alex Bennée:\n\n* Comment the definition of SVE_VL_ARCH_MAX.\n\n* Thin out BUG_ON()s:\nRedundant BUG_ON()s and ones that just check invariants are removed.\nImportant sanity-checks are migrated to WARN_ON()s, with some\nminimal best-effort patch-up code.\n\nOther changes related Alex Bennée's comments:\n\n* sve_max_vl is definitely not supposed to be changed after boot.\nMake it official by marking it __ro_after_init.\n\n* Migrate away from magic number for SVE_VQ_BYTES.\n---\n arch/arm64/include/asm/fpsimd.h | 8 +++\n arch/arm64/kernel/fpsimd.c | 128 +++++++++++++++++++++++++++++++++++++++-\n include/uapi/linux/prctl.h | 5 ++\n 3 files changed, 140 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\nindex 7efd04e..32c8e19 100644\n--- a/arch/arm64/include/asm/fpsimd.h\n+++ b/arch/arm64/include/asm/fpsimd.h\n@@ -20,6 +20,7 @@\n \n #ifndef __ASSEMBLY__\n \n+#include <linux/cache.h>\n #include <linux/stddef.h>\n \n /*\n@@ -70,11 +71,16 @@ extern void fpsimd_update_current_state(struct fpsimd_state *state);\n \n extern void fpsimd_flush_task_state(struct task_struct *target);\n \n+/* Maximum VL that SVE VL-agnostic software can transparently support */\n+#define SVE_VL_ARCH_MAX 0x100\n+\n extern void sve_save_state(void *state, u32 *pfpsr);\n extern void sve_load_state(void const *state, u32 const *pfpsr,\n \t\t\t unsigned long vq_minus_1);\n extern unsigned int sve_get_vl(void);\n \n+extern int __ro_after_init sve_max_vl;\n+\n #ifdef CONFIG_ARM64_SVE\n \n extern size_t sve_state_size(struct task_struct const *task);\n@@ -83,6 +89,8 @@ extern void sve_alloc(struct task_struct *task);\n extern void fpsimd_release_thread(struct task_struct *task);\n extern void fpsimd_dup_sve(struct task_struct *dst,\n \t\t\t struct task_struct const *src);\n+extern int sve_set_vector_length(struct task_struct *task,\n+\t\t\t\t unsigned long vl, unsigned long flags);\n \n #else /* ! CONFIG_ARM64_SVE */\n \ndiff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\nindex f82cde8..713476e 100644\n--- a/arch/arm64/kernel/fpsimd.c\n+++ b/arch/arm64/kernel/fpsimd.c\n@@ -17,8 +17,10 @@\n * along with this program. If not, see <http://www.gnu.org/licenses/>.\n */\n \n+#include <linux/bitmap.h>\n #include <linux/bottom_half.h>\n #include <linux/bug.h>\n+#include <linux/cache.h>\n #include <linux/compat.h>\n #include <linux/cpu.h>\n #include <linux/cpu_pm.h>\n@@ -26,6 +28,7 @@\n #include <linux/init.h>\n #include <linux/percpu.h>\n #include <linux/preempt.h>\n+#include <linux/prctl.h>\n #include <linux/ptrace.h>\n #include <linux/sched/signal.h>\n #include <linux/signal.h>\n@@ -109,6 +112,20 @@ static DEFINE_PER_CPU(struct fpsimd_state *, fpsimd_last_state);\n /* Default VL for tasks that don't set it explicitly: */\n static int sve_default_vl = SVE_VL_MIN;\n \n+#ifdef CONFIG_ARM64_SVE\n+\n+/* Maximum supported vector length across all CPUs (initially poisoned) */\n+int __ro_after_init sve_max_vl = -1;\n+/* Set of available vector lengths, as vq_to_bit(vq): */\n+static DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX);\n+\n+#else /* ! CONFIG_ARM64_SVE */\n+\n+/* Dummy declaration for code that will be optimised out: */\n+extern DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX);\n+\n+#endif /* ! CONFIG_ARM64_SVE */\n+\n static void sve_free(struct task_struct *task)\n {\n \tkfree(task->thread.sve_state);\n@@ -186,6 +203,44 @@ static void task_fpsimd_save(void)\n \t}\n }\n \n+static unsigned int vq_to_bit(unsigned int vq)\n+{\n+\treturn SVE_VQ_MAX - vq;\n+}\n+\n+static unsigned int bit_to_vq(unsigned int bit)\n+{\n+\tif (WARN_ON(bit >= SVE_VQ_MAX))\n+\t\tbit = SVE_VQ_MAX - 1;\n+\n+\treturn SVE_VQ_MAX - bit;\n+}\n+\n+/*\n+ * All vector length selection from userspace comes through here.\n+ * We're on a slow path, so some sanity-checks are included.\n+ * If things go wrong there's a bug somewhere, but try to fall back to a\n+ * safe choice.\n+ */\n+static unsigned int find_supported_vector_length(unsigned int vl)\n+{\n+\tint bit;\n+\tint max_vl = sve_max_vl;\n+\n+\tif (WARN_ON(!sve_vl_valid(vl)))\n+\t\tvl = SVE_VL_MIN;\n+\n+\tif (WARN_ON(!sve_vl_valid(max_vl)))\n+\t\tmax_vl = SVE_VL_MIN;\n+\n+\tif (vl > max_vl)\n+\t\tvl = max_vl;\n+\n+\tbit = find_next_bit(sve_vq_map, SVE_VQ_MAX,\n+\t\t\t vq_to_bit(sve_vq_from_vl(vl)));\n+\treturn sve_vl_from_vq(bit_to_vq(bit));\n+}\n+\n #define ZREG(sve_state, vq, n) ((char *)(sve_state) +\t\t\\\n \t(SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))\n \n@@ -265,6 +320,73 @@ void fpsimd_dup_sve(struct task_struct *dst, struct task_struct const *src)\n \tdst->thread.sve_state = NULL;\n }\n \n+int sve_set_vector_length(struct task_struct *task,\n+\t\t\t unsigned long vl, unsigned long flags)\n+{\n+\tWARN_ON(task == current && preemptible());\n+\n+\tif (flags & ~(unsigned long)(PR_SVE_VL_INHERIT |\n+\t\t\t\t PR_SVE_SET_VL_ONEXEC))\n+\t\treturn -EINVAL;\n+\n+\tif (!sve_vl_valid(vl))\n+\t\treturn -EINVAL;\n+\n+\t/*\n+\t * Clamp to the maximum vector length that VL-agnostic SVE code can\n+\t * work with. A flag may be assigned in the future to allow setting\n+\t * of larger vector lengths without confusing older software.\n+\t */\n+\tif (vl > SVE_VL_ARCH_MAX)\n+\t\tvl = SVE_VL_ARCH_MAX;\n+\n+\tvl = find_supported_vector_length(vl);\n+\n+\tif (flags & (PR_SVE_VL_INHERIT |\n+\t\t PR_SVE_SET_VL_ONEXEC))\n+\t\ttask->thread.sve_vl_onexec = vl;\n+\telse\n+\t\t/* Reset VL to system default on next exec: */\n+\t\ttask->thread.sve_vl_onexec = 0;\n+\n+\t/* Only actually set the VL if not deferred: */\n+\tif (flags & PR_SVE_SET_VL_ONEXEC)\n+\t\tgoto out;\n+\n+\t/*\n+\t * To ensure the FPSIMD bits of the SVE vector registers are preserved,\n+\t * write any live register state back to task_struct, and convert to a\n+\t * non-SVE thread.\n+\t */\n+\tif (vl != task->thread.sve_vl) {\n+\t\tif (task == current) {\n+\t\t\ttask_fpsimd_save();\n+\t\t\tset_thread_flag(TIF_FOREIGN_FPSTATE);\n+\t\t}\n+\n+\t\tif (test_and_clear_tsk_thread_flag(task, TIF_SVE))\n+\t\t\tsve_to_fpsimd(task);\n+\n+\t\t/*\n+\t\t * Force reallocation of task SVE state to the correct size\n+\t\t * on next use:\n+\t\t */\n+\t\tsve_free(task);\n+\t}\n+\n+\ttask->thread.sve_vl = vl;\n+\n+\tfpsimd_flush_task_state(task);\n+\n+out:\n+\tif (flags & PR_SVE_VL_INHERIT)\n+\t\tset_thread_flag(TIF_SVE_VL_INHERIT);\n+\telse\n+\t\tclear_thread_flag(TIF_SVE_VL_INHERIT);\n+\n+\treturn 0;\n+}\n+\n void fpsimd_release_thread(struct task_struct *dead_task)\n {\n \tsve_free(dead_task);\n@@ -361,7 +483,7 @@ void fpsimd_thread_switch(struct task_struct *next)\n \n void fpsimd_flush_thread(void)\n {\n-\tint vl;\n+\tint vl, supported_vl;\n \n \tif (!system_supports_fpsimd())\n \t\treturn;\n@@ -389,6 +511,10 @@ void fpsimd_flush_thread(void)\n \t\tif (WARN_ON(!sve_vl_valid(vl)))\n \t\t\tvl = SVE_VL_MIN;\n \n+\t\tsupported_vl = find_supported_vector_length(vl);\n+\t\tif (WARN_ON(supported_vl != vl))\n+\t\t\tvl = supported_vl;\n+\n \t\tcurrent->thread.sve_vl = vl;\n \n \t\t/*\ndiff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h\nindex a8d0759..1b64901 100644\n--- a/include/uapi/linux/prctl.h\n+++ b/include/uapi/linux/prctl.h\n@@ -197,4 +197,9 @@ struct prctl_mm_map {\n # define PR_CAP_AMBIENT_LOWER\t\t3\n # define PR_CAP_AMBIENT_CLEAR_ALL\t4\n \n+/* arm64 Scalable Vector Extension controls */\n+# define PR_SVE_SET_VL_ONEXEC\t\t(1 << 18) /* defer effect until exec */\n+# define PR_SVE_VL_LEN_MASK\t\t0xffff\n+# define PR_SVE_VL_INHERIT\t\t(1 << 17) /* inherit across exec */\n+\n #endif /* _LINUX_PRCTL_H */\n", "prefixes": [ "v2", "14/28" ] }