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GET /api/patches/808338/?format=api
{ "id": 808338, "url": "http://patchwork.ozlabs.org/api/patches/808338/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1504198860-12951-11-git-send-email-Dave.Martin@arm.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504198860-12951-11-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-08-31T17:00:42", "name": "[v2,10/28] arm64/sve: Low-level CPU setup", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6b548e710ce00b91ee69bc3ccdde8b283e721e24", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1504198860-12951-11-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 883, "url": "http://patchwork.ozlabs.org/api/series/883/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/list/?series=883", "date": "2017-08-31T17:00:33", "name": "ARM Scalable Vector Extension (SVE)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/883/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808338/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808338/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"k433138t\"; dkim-atps=neutral" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjpcn3TtRz9s81\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tFri, 1 Sep 2017 03:04:09 +1000 (AEST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnSsv-0000a0-Fj; Thu, 31 Aug 2017 17:04:05 +0000", "from foss.arm.com ([217.140.101.70])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnSqt-0007JY-Ma for linux-arm-kernel@lists.infradead.org;\n\tThu, 31 Aug 2017 17:02:07 +0000", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 81A0416EA;\n\tThu, 31 Aug 2017 10:01:34 -0700 (PDT)", "from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\tD5B833F58F; Thu, 31 Aug 2017 10:01:32 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=O+7CePWunVq3dDJWY6Ml8GDTruQ5qEpctLAH0/LhM/I=;\n\tb=k433138tamfW/8\n\tMWGiANNXSmS/KjC4CaWjrUPZQdc7MSDrwSX4Nzk62HaHaKKifmzisSmK4RiAGMnOJXQ4mzyQrf2Hk\n\tw8Z+Kgj476zvke4h66Oy9T4lP2pA954eHo2yok5UoCF3xkkdsmkJvLC4u0zSFSSLGRYFSWeORY2Gr\n\tcf3hnpDYiF4x+SO4hSwqe+KJr/9hPErxFcdhI+lNBGMyzft88iYf+XM/eknXTay3zG+bRTzK7Bbb1\n\tncVXG+Tr+i1diFLkknn+fY+SI4xJnyFlJT1t9niPhnnK8okgibRc0YF7lptGbYxTlQ4PSRuLoEcwl\n\t9Hr8KInHKGm1aMqoCIyw==;", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Subject": "[PATCH v2 10/28] arm64/sve: Low-level CPU setup", "Date": "Thu, 31 Aug 2017 18:00:42 +0100", "Message-Id": "<1504198860-12951-11-git-send-email-Dave.Martin@arm.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "References": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "MIME-Version": "1.0", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20170831_100200_082050_467197BD ", "X-CRM114-Status": "UNSURE ( 9.63 )", "X-CRM114-Notice": "Please train this message.", "X-Spam-Score": "-6.9 (------)", "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Cc": "linux-arch@vger.kernel.org, libc-alpha@sourceware.org, Ard Biesheuvel\n\t<ard.biesheuvel@linaro.org>, Szabolcs Nagy <szabolcs.nagy@arm.com>,\n\tCatalin Marinas\n\t<catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Richard\n\tSandiford <richard.sandiford@arm.com>, =?utf-8?q?Alex_Benn=C3=A9e?=\n\t<alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "To enable the kernel to use SVE, all SVE traps from EL1 must be\ndisabled. To take maximum advantage of the hardware, the full\navailable vector length also needs to be enabled for EL1 by\nprogramming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as\nrequired, but this cannot override the limit set by ZCR_EL2.)\n\nIn advance of full SVE support being implemented for userspace, it\nalso necessary to ensure that SVE traps from EL0 are enabled.\n\nThis patch makes the appropriate changes to the primary and\nsecondary CPU initialisation code.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\n---\n arch/arm64/kernel/head.S | 13 ++++++++++++-\n arch/arm64/mm/proc.S | 14 ++++++++++++--\n 2 files changed, 24 insertions(+), 3 deletions(-)", "diff": "diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S\nindex 7434ec0..f411f71 100644\n--- a/arch/arm64/kernel/head.S\n+++ b/arch/arm64/kernel/head.S\n@@ -516,8 +516,19 @@ CPU_LE(\tmovk\tx0, #0x30d0, lsl #16\t)\t// Clear EE and E0E on LE systems\n \tmov\tx0, #0x33ff\n \tmsr\tcptr_el2, x0\t\t\t// Disable copro. traps to EL2\n \n+\t/* SVE register access */\n+\tmrs\tx1, id_aa64pfr0_el1\n+\tubfx\tx1, x1, #ID_AA64PFR0_SVE_SHIFT, #4\n+\tcbz\tx1, 7f\n+\n+\tbic\tx0, x0, #CPTR_EL2_TZ\t\t// Also disable SVE traps\n+\tmsr\tcptr_el2, x0\t\t\t// Disable copro. traps to EL2\n+\tisb\n+\tmov\tx1, #ZCR_ELx_LEN_MASK\t\t// SVE: Enable full vector\n+\tmsr_s\tSYS_ZCR_EL2, x1\t\t\t// length for EL1.\n+\n \t/* Hypervisor stub */\n-\tadr_l\tx0, __hyp_stub_vectors\n+7:\tadr_l\tx0, __hyp_stub_vectors\n \tmsr\tvbar_el2, x0\n \n \t/* spsr */\ndiff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S\nindex 877d42f..dd22ef2 100644\n--- a/arch/arm64/mm/proc.S\n+++ b/arch/arm64/mm/proc.S\n@@ -27,6 +27,7 @@\n #include <asm/pgtable-hwdef.h>\n #include <asm/cpufeature.h>\n #include <asm/alternative.h>\n+#include <asm/sysreg.h>\n \n #ifdef CONFIG_ARM64_64K_PAGES\n #define TCR_TG_FLAGS\tTCR_TG0_64K | TCR_TG1_64K\n@@ -186,8 +187,17 @@ ENTRY(__cpu_setup)\n \ttlbi\tvmalle1\t\t\t\t// Invalidate local TLB\n \tdsb\tnsh\n \n-\tmov\tx0, #3 << 20\n-\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n+\tmov\tx0, #3 << 20\t\t\t// FEN\n+\n+\t/* SVE */\n+\tmrs\tx5, id_aa64pfr0_el1\n+\tubfx\tx5, x5, #ID_AA64PFR0_SVE_SHIFT, #4\n+\tcbz\tx5, 1f\n+\n+\tbic\tx0, x0, #CPACR_EL1_ZEN\n+\torr\tx0, x0, #CPACR_EL1_ZEN_EL1EN\t// SVE: trap for EL0, not EL1\n+1:\tmsr\tcpacr_el1, x0\t\t\t// Enable FP/ASIMD\n+\n \tmov\tx0, #1 << 12\t\t\t// Reset mdscr_el1 and disable\n \tmsr\tmdscr_el1, x0\t\t\t// access to the DCC from EL0\n \tisb\t\t\t\t\t// Unmask debug exceptions now,\n", "prefixes": [ "v2", "10/28" ] }