Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/808329/?format=api
{ "id": 808329, "url": "http://patchwork.ozlabs.org/api/patches/808329/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1504198860-12951-7-git-send-email-Dave.Martin@arm.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504198860-12951-7-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-08-31T17:00:38", "name": "[v2,06/28] arm64/sve: System register and exception syndrome definitions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ce5738d199d93b3dd599d16cdecdef9c042d2425", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1504198860-12951-7-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 883, "url": "http://patchwork.ozlabs.org/api/series/883/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/list/?series=883", "date": "2017-08-31T17:00:33", "name": "ARM Scalable Vector Extension (SVE)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/883/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808329/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808329/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"X2j8SeDc\"; dkim-atps=neutral" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjpbg3vMlz9sPm\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tFri, 1 Sep 2017 03:03:11 +1000 (AEST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnSrz-0008B4-C5; Thu, 31 Aug 2017 17:03:07 +0000", "from foss.arm.com ([217.140.101.70])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnSqo-0007Gy-Mk for linux-arm-kernel@lists.infradead.org;\n\tThu, 31 Aug 2017 17:01:59 +0000", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 515C5165D;\n\tThu, 31 Aug 2017 10:01:26 -0700 (PDT)", "from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\tA58693F58F; Thu, 31 Aug 2017 10:01:24 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=XLkwMJAE43ElMv35gIdnmMGlC4k3SR4w/DRRkoQuUq0=;\n\tb=X2j8SeDcnW5P6k\n\tO8i8qIjK91xCoJ9idC8/PnheSsyFx53xN9+DZF9Meo2XGSQO+BuZ9jJtuLYAx8QLfKTS7rqMkg/8G\n\t6cNSIwinhuuvJBKIZtxPCROdEsjF4Q5lNG39WNXu6m/t+3tQ7rrbqecNBp3Cc5iVbCTEX+0gsvmNS\n\tD84qzRYaMFyy9g+TkoAB8Y3rUzfRVTuiFkCa5xRsI7Zf4rUwh4nST/RztrIjQ6vkuDH30B2fkdUb0\n\tEqsrkwNB3Gjog3wbw0BymAQ2nmugB6wAbsrTEGf8BYYUB9Rjn0RTeavqtn6iDlCiOhtBWaaWVXmKQ\n\tr6IboqOc36I6rKYNlzEg==;", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Subject": "[PATCH v2 06/28] arm64/sve: System register and exception syndrome\n\tdefinitions", "Date": "Thu, 31 Aug 2017 18:00:38 +0100", "Message-Id": "<1504198860-12951-7-git-send-email-Dave.Martin@arm.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "References": "<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>", "MIME-Version": "1.0", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20170831_100154_943670_759E3424 ", "X-CRM114-Status": "GOOD ( 10.79 )", "X-Spam-Score": "-6.9 (------)", "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Cc": "linux-arch@vger.kernel.org, libc-alpha@sourceware.org, Ard Biesheuvel\n\t<ard.biesheuvel@linaro.org>, Szabolcs Nagy <szabolcs.nagy@arm.com>,\n\tCatalin Marinas\n\t<catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Richard\n\tSandiford <richard.sandiford@arm.com>, =?utf-8?q?Alex_Benn=C3=A9e?=\n\t<alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "The SVE architecture adds some system registers, ID register fields\nand a dedicated ESR exception class.\n\nThis patch adds the appropriate definitions that will be needed by\nthe kernel.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nCc: Alex Bennée <alex.bennee@linaro.org>\n\n---\n\nChanges since v1\n----------------\n\nRequested by Alex Bennée:\n\n* Add comments to clarify CPACR_EL1_ZEN_ELxEN bit meanings.\n* Add comment clarifying the status of the LEN field expansion bits.\n---\n arch/arm64/include/asm/esr.h | 3 ++-\n arch/arm64/include/asm/kvm_arm.h | 1 +\n arch/arm64/include/asm/sysreg.h | 21 +++++++++++++++++++++\n arch/arm64/kernel/traps.c | 1 +\n 4 files changed, 25 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h\nindex 66ed8b6..014d7d8 100644\n--- a/arch/arm64/include/asm/esr.h\n+++ b/arch/arm64/include/asm/esr.h\n@@ -43,7 +43,8 @@\n #define ESR_ELx_EC_HVC64\t(0x16)\n #define ESR_ELx_EC_SMC64\t(0x17)\n #define ESR_ELx_EC_SYS64\t(0x18)\n-/* Unallocated EC: 0x19 - 0x1E */\n+#define ESR_ELx_EC_SVE\t\t(0x19)\n+/* Unallocated EC: 0x1A - 0x1E */\n #define ESR_ELx_EC_IMP_DEF\t(0x1f)\n #define ESR_ELx_EC_IABT_LOW\t(0x20)\n #define ESR_ELx_EC_IABT_CUR\t(0x21)\ndiff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h\nindex 61d694c..dbf0537 100644\n--- a/arch/arm64/include/asm/kvm_arm.h\n+++ b/arch/arm64/include/asm/kvm_arm.h\n@@ -185,6 +185,7 @@\n #define CPTR_EL2_TCPAC\t(1 << 31)\n #define CPTR_EL2_TTA\t(1 << 20)\n #define CPTR_EL2_TFP\t(1 << CPTR_EL2_TFP_SHIFT)\n+#define CPTR_EL2_TZ\t(1 << 8)\n #define CPTR_EL2_DEFAULT\t0x000033ff\n \n /* Hyp Debug Configuration Register bits */\ndiff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h\nindex 480ecd6..36fe2ae 100644\n--- a/arch/arm64/include/asm/sysreg.h\n+++ b/arch/arm64/include/asm/sysreg.h\n@@ -145,6 +145,7 @@\n \n #define SYS_ID_AA64PFR0_EL1\t\tsys_reg(3, 0, 0, 4, 0)\n #define SYS_ID_AA64PFR1_EL1\t\tsys_reg(3, 0, 0, 4, 1)\n+#define SYS_ID_AA64ZFR0_EL1\t\tsys_reg(3, 0, 0, 4, 4)\n \n #define SYS_ID_AA64DFR0_EL1\t\tsys_reg(3, 0, 0, 5, 0)\n #define SYS_ID_AA64DFR1_EL1\t\tsys_reg(3, 0, 0, 5, 1)\n@@ -163,6 +164,8 @@\n #define SYS_ACTLR_EL1\t\t\tsys_reg(3, 0, 1, 0, 1)\n #define SYS_CPACR_EL1\t\t\tsys_reg(3, 0, 1, 0, 2)\n \n+#define SYS_ZCR_EL1\t\t\tsys_reg(3, 0, 1, 2, 0)\n+\n #define SYS_TTBR0_EL1\t\t\tsys_reg(3, 0, 2, 0, 0)\n #define SYS_TTBR1_EL1\t\t\tsys_reg(3, 0, 2, 0, 1)\n #define SYS_TCR_EL1\t\t\tsys_reg(3, 0, 2, 0, 2)\n@@ -253,6 +256,8 @@\n \n #define SYS_PMCCFILTR_EL0\t\tsys_reg (3, 3, 14, 15, 7)\n \n+#define SYS_ZCR_EL2\t\t\tsys_reg(3, 4, 1, 2, 0)\n+\n #define SYS_DACR32_EL2\t\t\tsys_reg(3, 4, 3, 0, 0)\n #define SYS_IFSR32_EL2\t\t\tsys_reg(3, 4, 5, 0, 1)\n #define SYS_FPEXC32_EL2\t\t\tsys_reg(3, 4, 5, 3, 0)\n@@ -335,6 +340,7 @@\n #define ID_AA64ISAR1_DPB_SHIFT\t\t0\n \n /* id_aa64pfr0 */\n+#define ID_AA64PFR0_SVE_SHIFT\t\t32\n #define ID_AA64PFR0_GIC_SHIFT\t\t24\n #define ID_AA64PFR0_ASIMD_SHIFT\t\t20\n #define ID_AA64PFR0_FP_SHIFT\t\t16\n@@ -343,6 +349,7 @@\n #define ID_AA64PFR0_EL1_SHIFT\t\t4\n #define ID_AA64PFR0_EL0_SHIFT\t\t0\n \n+#define ID_AA64PFR0_SVE\t\t\t0x1\n #define ID_AA64PFR0_FP_NI\t\t0xf\n #define ID_AA64PFR0_FP_SUPPORTED\t0x0\n #define ID_AA64PFR0_ASIMD_NI\t\t0xf\n@@ -444,6 +451,20 @@\n #endif\n \n \n+/*\n+ * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which\n+ * are reserved by the SVE architecture for future expansion of the LEN\n+ * field, with compatible semantics.\n+ */\n+#define ZCR_ELx_LEN_SHIFT\t0\n+#define ZCR_ELx_LEN_SIZE\t9\n+#define ZCR_ELx_LEN_MASK\t0x1ff\n+\n+#define CPACR_EL1_ZEN_EL1EN\t(1 << 16) /* enable EL1 access */\n+#define CPACR_EL1_ZEN_EL0EN\t(1 << 17) /* enable EL0 access, if EL1EN set */\n+#define CPACR_EL1_ZEN\t\t(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)\n+\n+\n /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */\n #define SYS_MPIDR_SAFE_VAL\t\t(1UL << 31)\n \ndiff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c\nindex 5ea4b85..f202932 100644\n--- a/arch/arm64/kernel/traps.c\n+++ b/arch/arm64/kernel/traps.c\n@@ -603,6 +603,7 @@ static const char *esr_class_str[] = {\n \t[ESR_ELx_EC_HVC64]\t\t= \"HVC (AArch64)\",\n \t[ESR_ELx_EC_SMC64]\t\t= \"SMC (AArch64)\",\n \t[ESR_ELx_EC_SYS64]\t\t= \"MSR/MRS (AArch64)\",\n+\t[ESR_ELx_EC_SVE]\t\t= \"SVE\",\n \t[ESR_ELx_EC_IMP_DEF]\t\t= \"EL3 IMP DEF\",\n \t[ESR_ELx_EC_IABT_LOW]\t\t= \"IABT (lower EL)\",\n \t[ESR_ELx_EC_IABT_CUR]\t\t= \"IABT (current EL)\",\n", "prefixes": [ "v2", "06/28" ] }