Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/808239/?format=api
{ "id": 808239, "url": "http://patchwork.ozlabs.org/api/patches/808239/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/1504186749-8926-3-git-send-email-lipeng321@huawei.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504186749-8926-3-git-send-email-lipeng321@huawei.com>", "list_archive_url": null, "date": "2017-08-31T13:39:03", "name": "[net-next,2/8] net: hns3: update ring and vector map command", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "8f3c200908963cb40685c79ea2908aeb7a7980bf", "submitter": { "id": 71468, "url": "http://patchwork.ozlabs.org/api/people/71468/?format=api", "name": "lipeng (Y)", "email": "lipeng321@huawei.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/1504186749-8926-3-git-send-email-lipeng321@huawei.com/mbox/", "series": [ { "id": 823, "url": "http://patchwork.ozlabs.org/api/series/823/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=823", "date": "2017-08-31T13:39:02", "name": "Bug fixes & Code improvements in HNS driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/823/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808239/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808239/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjjV25wCjz9sMN\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 31 Aug 2017 23:12:58 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751777AbdHaNMr (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tThu, 31 Aug 2017 09:12:47 -0400", "from szxga05-in.huawei.com ([45.249.212.191]:5072 \"EHLO\n\tszxga05-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751250AbdHaNLZ (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Thu, 31 Aug 2017 09:11:25 -0400", "from 172.30.72.60 (EHLO DGGEMS404-HUB.china.huawei.com)\n\t([172.30.72.60])\n\tby dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGI62431; Thu, 31 Aug 2017 21:11:22 +0800 (CST)", "from linux-ioko.site (10.71.200.31) by\n\tDGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP\n\tServer id 14.3.301.0; Thu, 31 Aug 2017 21:11:09 +0800" ], "From": "Lipeng <lipeng321@huawei.com>", "To": "<davem@davemloft.net>", "CC": "<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<linuxarm@huawei.com>, <yisen.zhuang@huawei.com>,\n\t<salil.mehta@huawei.com>, <lipeng321@huawei.com>", "Subject": "[PATCH net-next 2/8] net: hns3: update ring and vector map command", "Date": "Thu, 31 Aug 2017 21:39:03 +0800", "Message-ID": "<1504186749-8926-3-git-send-email-lipeng321@huawei.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1504186749-8926-1-git-send-email-lipeng321@huawei.com>", "References": "<1504186749-8926-1-git-send-email-lipeng321@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.71.200.31]", "X-CFilter-Loop": "Reflected", "X-Mirapoint-Virus-RAPID-Raw": "score=unknown(0),\n\trefid=str=0001.0A020202.59A80AFA.0234, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32", "X-Mirapoint-Loop-Id": "dedd303cc14ec64e8589067ea3a5f2a5", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "Add INT_GL and VF id to vector configure when bind ring with vector.\nINT_GL means Interrupt Gap Limiting.Vector id starts from 0 in each\nVF, so the bind command must specify VF id.\n\nSigned-off-by: Lipeng <lipeng321@huawei.com>\nSigned-off-by: Mingguang Qu <qumingguang@huawei.com>\n---\n drivers/net/ethernet/hisilicon/hns3/hnae3.h | 4 +\n .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 8 +-\n .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 105 ++++++++-------------\n .../net/ethernet/hisilicon/hns3/hns3pf/hns3_enet.c | 9 ++\n 4 files changed, 60 insertions(+), 66 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h\nindex e23e028..3617372 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h\n@@ -108,11 +108,15 @@ struct hnae3_vector_info {\n #define HNAE3_RING_TYPE_B 0\n #define HNAE3_RING_TYPE_TX 0\n #define HNAE3_RING_TYPE_RX 1\n+#define HNAE3_RING_GL_IDX_B 0\n+#define HNAE3_RING_GL_RX 0\n+#define HNAE3_RING_GL_TX 1\n \n struct hnae3_ring_chain_node {\n \tstruct hnae3_ring_chain_node *next;\n \tu32 tqp_index;\n \tu32 flag;\n+\tu32 int_gl_idx;\n };\n \n #define HNAE3_IS_TX_RING(node) \\\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\nindex 91ae013..c2b613b 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\n@@ -238,7 +238,7 @@ struct hclge_tqp_map {\n \tu8 rsv[18];\n };\n \n-#define HCLGE_VECTOR_ELEMENTS_PER_CMD\t11\n+#define HCLGE_VECTOR_ELEMENTS_PER_CMD\t10\n \n enum hclge_int_type {\n \tHCLGE_INT_TX,\n@@ -252,8 +252,12 @@ struct hclge_ctrl_vector_chain {\n #define HCLGE_INT_TYPE_S\t0\n #define HCLGE_INT_TYPE_M\t0x3\n #define HCLGE_TQP_ID_S\t\t2\n-#define HCLGE_TQP_ID_M\t\t(0x3fff << HCLGE_TQP_ID_S)\n+#define HCLGE_TQP_ID_M\t\t(0x7ff << HCLGE_TQP_ID_S)\n+#define HCLGE_INT_GL_IDX_S\t13\n+#define HCLGE_INT_GL_IDX_M\t(0x3 << HCLGE_INT_GL_IDX_S)\n \t__le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];\n+\tu8 vfid;\n+\tu8 rsv;\n };\n \n #define HCLGE_TC_NUM\t\t8\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\nindex acc4016..3a8cb40 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\n@@ -2346,6 +2346,13 @@ static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,\n \treturn alloc;\n }\n \n+static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)\n+{\n+\thdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;\n+\thdev->num_msi_left += 1;\n+\thdev->num_msi_used -= 1;\n+}\n+\n static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)\n {\n \tint i;\n@@ -2672,19 +2679,21 @@ static int hclge_rss_init_hw(struct hclge_dev *hdev)\n \treturn ret;\n }\n \n-int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,\n-\t\t\t\t struct hnae3_ring_chain_node *ring_chain)\n+int hclge_bind_ring_with_vector(struct hclge_vport *vport,\n+\t\t\t\tint vector_id, bool en,\n+\t\t\t\tstruct hnae3_ring_chain_node *ring_chain)\n {\n \tstruct hclge_dev *hdev = vport->back;\n-\tstruct hclge_ctrl_vector_chain *req;\n \tstruct hnae3_ring_chain_node *node;\n \tstruct hclge_desc desc;\n-\tint ret;\n+\tstruct hclge_ctrl_vector_chain *req\n+\t\t= (struct hclge_ctrl_vector_chain *)desc.data;\n+\tenum hclge_cmd_status status;\n+\tenum hclge_opcode_type op;\n \tint i;\n \n-\thclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);\n-\n-\treq = (struct hclge_ctrl_vector_chain *)desc.data;\n+\top = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;\n+\thclge_cmd_setup_basic_desc(&desc, op, false);\n \treq->int_vector_id = vector_id;\n \n \ti = 0;\n@@ -2694,17 +2703,21 @@ int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,\n \t\t\t hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));\n \t\thnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,\n \t\t\t HCLGE_TQP_ID_S,\tnode->tqp_index);\n+\t\thnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,\n+\t\t\t HCLGE_INT_GL_IDX_S,\n+\t\t\t hnae_get_bit(node->int_gl_idx,\n+\t\t\t\t\t HNAE3_RING_GL_IDX_B));\n \t\treq->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);\n-\n \t\tif (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {\n \t\t\treq->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;\n+\t\t\treq->vfid = vport->vport_id;\n \n-\t\t\tret = hclge_cmd_send(&hdev->hw, &desc, 1);\n-\t\t\tif (ret) {\n+\t\t\tstatus = hclge_cmd_send(&hdev->hw, &desc, 1);\n+\t\t\tif (status) {\n \t\t\t\tdev_err(&hdev->pdev->dev,\n \t\t\t\t\t\"Map TQP fail, status is %d.\\n\",\n-\t\t\t\t\tret);\n-\t\t\t\treturn ret;\n+\t\t\t\t\tstatus);\n+\t\t\t\treturn -EIO;\n \t\t\t}\n \t\t\ti = 0;\n \n@@ -2717,12 +2730,12 @@ int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,\n \n \tif (i > 0) {\n \t\treq->int_cause_num = i;\n-\n-\t\tret = hclge_cmd_send(&hdev->hw, &desc, 1);\n-\t\tif (ret) {\n+\t\treq->vfid = vport->vport_id;\n+\t\tstatus = hclge_cmd_send(&hdev->hw, &desc, 1);\n+\t\tif (status) {\n \t\t\tdev_err(&hdev->pdev->dev,\n-\t\t\t\t\"Map TQP fail, status is %d.\\n\", ret);\n-\t\t\treturn ret;\n+\t\t\t\t\"Map TQP fail, status is %d.\\n\", status);\n+\t\t\treturn -EIO;\n \t\t}\n \t}\n \n@@ -2744,7 +2757,7 @@ int hclge_map_handle_ring_to_vector(struct hnae3_handle *handle,\n \t\treturn vector_id;\n \t}\n \n-\treturn hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);\n+\treturn hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);\n }\n \n static int hclge_unmap_ring_from_vector(\n@@ -2753,11 +2766,7 @@ static int hclge_unmap_ring_from_vector(\n {\n \tstruct hclge_vport *vport = hclge_get_vport(handle);\n \tstruct hclge_dev *hdev = vport->back;\n-\tstruct hclge_ctrl_vector_chain *req;\n-\tstruct hnae3_ring_chain_node *node;\n-\tstruct hclge_desc desc;\n-\tint i, vector_id;\n-\tint ret;\n+\tint vector_id, ret;\n \n \tvector_id = hclge_get_vector_index(hdev, vector);\n \tif (vector_id < 0) {\n@@ -2766,49 +2775,17 @@ static int hclge_unmap_ring_from_vector(\n \t\treturn vector_id;\n \t}\n \n-\thclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);\n-\n-\treq = (struct hclge_ctrl_vector_chain *)desc.data;\n-\treq->int_vector_id = vector_id;\n-\n-\ti = 0;\n-\tfor (node = ring_chain; node; node = node->next) {\n-\t\thnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,\n-\t\t\t HCLGE_INT_TYPE_S,\n-\t\t\t hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));\n-\t\thnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,\n-\t\t\t HCLGE_TQP_ID_S,\tnode->tqp_index);\n-\n-\t\treq->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);\n-\n-\t\tif (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {\n-\t\t\treq->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;\n-\n-\t\t\tret = hclge_cmd_send(&hdev->hw, &desc, 1);\n-\t\t\tif (ret) {\n-\t\t\t\tdev_err(&hdev->pdev->dev,\n-\t\t\t\t\t\"Unmap TQP fail, status is %d.\\n\",\n-\t\t\t\t\tret);\n-\t\t\t\treturn ret;\n-\t\t\t}\n-\t\t\ti = 0;\n-\t\t\thclge_cmd_setup_basic_desc(&desc,\n-\t\t\t\t\t\t HCLGE_OPC_ADD_RING_TO_VECTOR,\n-\t\t\t\t\t\t false);\n-\t\t\treq->int_vector_id = vector_id;\n-\t\t}\n+\tret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);\n+\tif (ret) {\n+\t\tdev_err(&handle->pdev->dev,\n+\t\t\t\"Unmap ring from vector fail. vectorid=%d, ret =%d\\n\",\n+\t\t\tvector_id,\n+\t\t\tret);\n+\t\treturn ret;\n \t}\n \n-\tif (i > 0) {\n-\t\treq->int_cause_num = i;\n-\n-\t\tret = hclge_cmd_send(&hdev->hw, &desc, 1);\n-\t\tif (ret) {\n-\t\t\tdev_err(&hdev->pdev->dev,\n-\t\t\t\t\"Unmap TQP fail, status is %d.\\n\", ret);\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n+\t/* Free this MSIX or MSI vector */\n+\thclge_free_vector(hdev, vector_id);\n \n \treturn 0;\n }\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hns3_enet.c\nindex 1c3e294..2e3c287 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hns3_enet.c\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hns3_enet.c\n@@ -2276,6 +2276,8 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,\n \t\tcur_chain->tqp_index = tx_ring->tqp->tqp_index;\n \t\thnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,\n \t\t\t HNAE3_RING_TYPE_TX);\n+\t\thnae_set_bit(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_B,\n+\t\t\t HNAE3_RING_GL_TX);\n \n \t\tcur_chain->next = NULL;\n \n@@ -2291,6 +2293,8 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,\n \t\t\tchain->tqp_index = tx_ring->tqp->tqp_index;\n \t\t\thnae_set_bit(chain->flag, HNAE3_RING_TYPE_B,\n \t\t\t\t HNAE3_RING_TYPE_TX);\n+\t\t\thnae_set_bit(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_B,\n+\t\t\t\t HNAE3_RING_GL_TX);\n \n \t\t\tcur_chain = chain;\n \t\t}\n@@ -2302,6 +2306,8 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,\n \t\tcur_chain->tqp_index = rx_ring->tqp->tqp_index;\n \t\thnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,\n \t\t\t HNAE3_RING_TYPE_RX);\n+\t\thnae_set_bit(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_B,\n+\t\t\t HNAE3_RING_GL_RX);\n \n \t\trx_ring = rx_ring->next;\n \t}\n@@ -2315,6 +2321,9 @@ static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,\n \t\tchain->tqp_index = rx_ring->tqp->tqp_index;\n \t\thnae_set_bit(chain->flag, HNAE3_RING_TYPE_B,\n \t\t\t HNAE3_RING_TYPE_RX);\n+\t\thnae_set_bit(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_B,\n+\t\t\t HNAE3_RING_GL_RX);\n+\n \t\tcur_chain = chain;\n \n \t\trx_ring = rx_ring->next;\n", "prefixes": [ "net-next", "2/8" ] }