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{
    "id": 808220,
    "url": "http://patchwork.ozlabs.org/api/patches/808220/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504181016-16457-1-git-send-email-yamada.masahiro@socionext.com/",
    "project": {
        "id": 37,
        "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api",
        "name": "Devicetree Bindings",
        "link_name": "devicetree-bindings",
        "list_id": "devicetree.vger.kernel.org",
        "list_email": "devicetree@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1504181016-16457-1-git-send-email-yamada.masahiro@socionext.com>",
    "list_archive_url": null,
    "date": "2017-08-31T12:03:36",
    "name": "clk: uniphier: add PXs3 clock data",
    "commit_ref": null,
    "pull_url": null,
    "state": "not-applicable",
    "archived": true,
    "hash": "27674fa2c5d24d796de5cffb3f5bf21ded771371",
    "submitter": {
        "id": 65882,
        "url": "http://patchwork.ozlabs.org/api/people/65882/?format=api",
        "name": "Masahiro Yamada",
        "email": "yamada.masahiro@socionext.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504181016-16457-1-git-send-email-yamada.masahiro@socionext.com/mbox/",
    "series": [
        {
            "id": 810,
            "url": "http://patchwork.ozlabs.org/api/series/810/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=810",
            "date": "2017-08-31T12:03:36",
            "name": "clk: uniphier: add PXs3 clock data",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/810/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/808220/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/808220/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<devicetree-owner@vger.kernel.org>",
        "X-Original-To": "incoming-dt@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org",
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            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjgzY43yZz9s83\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 31 Aug 2017 22:04:57 +1000 (AEST)",
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            "from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp\n\t[153.142.97.92]) (authenticated)\n\tby conuserg-08.nifty.com with ESMTP id v7VC3laX025207;\n\tThu, 31 Aug 2017 21:03:47 +0900"
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        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com;\n\ts=dec2015msa; t=1504181028;\n\tbh=L89fBidJxsSTs+T235tioaFjmtkYcQ68C/NuTSDYiMg=;\n\th=From:To:Cc:Subject:Date:From;\n\tb=YzFlQdKdlulaIlCV9b5dIosC/Of6t5Ftwu1MKaJEXjUoqB9jC7uYEfELE6zhQFcDM\n\t1bi73j3uQob6p2GRTUkMiShKpw/wRjqw4Ny1r2vg/NI5eEMUqKU7qKSnOAf6gvDmCv\n\tEfKpM/YCLh5Zpmr3I532RMhAgMPB00YC9RW+PzXDVrmKM1kp5O3nrxpqGSXBV71Rs2\n\t9+Y990VQ8Z3Z5HFXVLUZnBN73UFxXny2hFUtumhIK/ulv7FF/2SShxKsEX1WkJ7ois\n\tgUgYkM841wYNvC2G3HuXhh9mbDHqqy4pTcanFyDhfvtQpYadz/ep51v0Ald0cxxX9g\n\txBviCarg0IcYg==",
        "X-Nifty-SrcIP": "[153.142.97.92]",
        "From": "Masahiro Yamada <yamada.masahiro@socionext.com>",
        "To": "linux-clk@vger.kernel.org",
        "Cc": "Masahiro Yamada <yamada.masahiro@socionext.com>,\n\tdevicetree@vger.kernel.org, Michael Turquette <mturquette@baylibre.com>, \n\tStephen Boyd <sboyd@codeaurora.org>,\n\tlinux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,\n\tMark Rutland <mark.rutland@arm.com>, linux-arm-kernel@lists.infradead.org",
        "Subject": "[PATCH] clk: uniphier: add PXs3 clock data",
        "Date": "Thu, 31 Aug 2017 21:03:36 +0900",
        "Message-Id": "<1504181016-16457-1-git-send-email-yamada.masahiro@socionext.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "Sender": "devicetree-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<devicetree.vger.kernel.org>",
        "X-Mailing-List": "devicetree@vger.kernel.org"
    },
    "content": "Add basic clock data for Socionext's new SoC PXs3.\n\nSigned-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>\n---\n\nI confirmed this patch can be cleanly applied on clk-next branch\n(commit 69a6beab085264)\n\n\n .../devicetree/bindings/clock/uniphier-clock.txt   |  3 +++\n drivers/clk/uniphier/clk-uniphier-core.c           | 12 +++++++++\n drivers/clk/uniphier/clk-uniphier-sys.c            | 30 ++++++++++++++++++++++\n drivers/clk/uniphier/clk-uniphier.h                |  1 +\n 4 files changed, 46 insertions(+)",
    "diff": "diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt b/Documentation/devicetree/bindings/clock/uniphier-clock.txt\nindex 2aec32d..7b5f602 100644\n--- a/Documentation/devicetree/bindings/clock/uniphier-clock.txt\n+++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt\n@@ -13,6 +13,7 @@ Required properties:\n     \"socionext,uniphier-pxs2-clock\" - for PXs2/LD6b SoC.\n     \"socionext,uniphier-ld11-clock\" - for LD11 SoC.\n     \"socionext,uniphier-ld20-clock\" - for LD20 SoC.\n+    \"socionext,uniphier-pxs3-clock\" - for PXs3 SoC\n - #clock-cells: should be 1.\n \n Example:\n@@ -54,6 +55,7 @@ Required properties:\n     \"socionext,uniphier-pxs2-sd-clock\"  - for PXs2/LD6b SoC.\n     \"socionext,uniphier-ld11-mio-clock\" - for LD11 SoC.\n     \"socionext,uniphier-ld20-sd-clock\"  - for LD20 SoC.\n+    \"socionext,uniphier-pxs3-sd-clock\"  - for PXs3 SoC\n - #clock-cells: should be 1.\n \n Example:\n@@ -97,6 +99,7 @@ Required properties:\n     \"socionext,uniphier-pxs2-peri-clock\" - for PXs2/LD6b SoC.\n     \"socionext,uniphier-ld11-peri-clock\" - for LD11 SoC.\n     \"socionext,uniphier-ld20-peri-clock\" - for LD20 SoC.\n+    \"socionext,uniphier-pxs3-peri-clock\" - for PXs3 SoC\n - #clock-cells: should be 1.\n \n Example:\ndiff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c\nindex cb6ae26..e09f3dd46 100644\n--- a/drivers/clk/uniphier/clk-uniphier-core.c\n+++ b/drivers/clk/uniphier/clk-uniphier-core.c\n@@ -138,6 +138,10 @@ static const struct of_device_id uniphier_clk_match[] = {\n \t\t.compatible = \"socionext,uniphier-ld20-clock\",\n \t\t.data = uniphier_ld20_sys_clk_data,\n \t},\n+\t{\n+\t\t.compatible = \"socionext,uniphier-pxs3-clock\",\n+\t\t.data = uniphier_pxs3_sys_clk_data,\n+\t},\n \t/* Media I/O clock, SD clock */\n \t{\n \t\t.compatible = \"socionext,uniphier-ld4-mio-clock\",\n@@ -167,6 +171,10 @@ static const struct of_device_id uniphier_clk_match[] = {\n \t\t.compatible = \"socionext,uniphier-ld20-sd-clock\",\n \t\t.data = uniphier_pro5_sd_clk_data,\n \t},\n+\t{\n+\t\t.compatible = \"socionext,uniphier-pxs3-sd-clock\",\n+\t\t.data = uniphier_pro5_sd_clk_data,\n+\t},\n \t/* Peripheral clock */\n \t{\n \t\t.compatible = \"socionext,uniphier-ld4-peri-clock\",\n@@ -196,6 +204,10 @@ static const struct of_device_id uniphier_clk_match[] = {\n \t\t.compatible = \"socionext,uniphier-ld20-peri-clock\",\n \t\t.data = uniphier_pro4_peri_clk_data,\n \t},\n+\t{\n+\t\t.compatible = \"socionext,uniphier-pxs3-peri-clock\",\n+\t\t.data = uniphier_pro4_peri_clk_data,\n+\t},\n \t{ /* sentinel */ }\n };\n \ndiff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c\nindex 6fcf781..7e77b09 100644\n--- a/drivers/clk/uniphier/clk-uniphier-sys.c\n+++ b/drivers/clk/uniphier/clk-uniphier-sys.c\n@@ -195,3 +195,33 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {\n \t\t\t     \"spll/4\", \"spll/8\", \"s2pll/4\", \"s2pll/8\"),\n \t{ /* sentinel */ }\n };\n+\n+const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {\n+\tUNIPHIER_CLK_FACTOR(\"cpll\", -1, \"ref\", 104, 1),\t\t/* ARM: 2600 MHz */\n+\tUNIPHIER_CLK_FACTOR(\"spll\", -1, \"ref\", 80, 1),\t\t/* 2000 MHz */\n+\tUNIPHIER_CLK_FACTOR(\"s2pll\", -1, \"ref\", 88, 1),\t\t/* IPP: 2400 MHz */\n+\tUNIPHIER_CLK_FACTOR(\"uart\", 0, \"spll\", 1, 34),\n+\tUNIPHIER_CLK_FACTOR(\"i2c\", 1, \"spll\", 1, 40),\n+\tUNIPHIER_LD20_SYS_CLK_SD,\n+\tUNIPHIER_LD11_SYS_CLK_NAND(2),\n+\tUNIPHIER_LD11_SYS_CLK_EMMC(4),\n+\tUNIPHIER_CLK_GATE(\"usb30\", 12, NULL, 0x2104, 4),\t/* =GIO0 */\n+\tUNIPHIER_CLK_GATE(\"usb31-0\", 13, NULL, 0x2104, 5),\t/* =GIO1 */\n+\tUNIPHIER_CLK_GATE(\"usb31-1\", 14, NULL, 0x2104, 6),\t/* =GIO1-1 */\n+\tUNIPHIER_CLK_GATE(\"usb30-phy0\", 16, NULL, 0x210c, 16),\n+\tUNIPHIER_CLK_GATE(\"usb30-phy1\", 17, NULL, 0x210c, 18),\n+\tUNIPHIER_CLK_GATE(\"usb30-phy2\", 18, NULL, 0x210c, 20),\n+\tUNIPHIER_CLK_GATE(\"usb31-phy0\", 20, NULL, 0x210c, 17),\n+\tUNIPHIER_CLK_GATE(\"usb31-phy1\", 21, NULL, 0x210c, 19),\n+\t/* CPU gears */\n+\tUNIPHIER_CLK_DIV4(\"cpll\", 2, 3, 4, 8),\n+\tUNIPHIER_CLK_DIV4(\"spll\", 2, 3, 4, 8),\n+\tUNIPHIER_CLK_DIV4(\"s2pll\", 2, 3, 4, 8),\n+\tUNIPHIER_CLK_CPUGEAR(\"cpu-ca53\", 33, 0x8080, 0xf, 8,\n+\t\t\t     \"cpll/2\", \"spll/2\", \"cpll/3\", \"spll/3\",\n+\t\t\t     \"spll/4\", \"spll/8\", \"cpll/4\", \"cpll/8\"),\n+\tUNIPHIER_CLK_CPUGEAR(\"cpu-ipp\", 34, 0x8100, 0xf, 8,\n+\t\t\t     \"s2pll/2\", \"spll/2\", \"s2pll/3\", \"spll/3\",\n+\t\t\t     \"spll/4\", \"spll/8\", \"s2pll/4\", \"s2pll/8\"),\n+\t{ /* sentinel */ }\n+};\ndiff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h\nindex 8271640..d10a009 100644\n--- a/drivers/clk/uniphier/clk-uniphier.h\n+++ b/drivers/clk/uniphier/clk-uniphier.h\n@@ -154,6 +154,7 @@ extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];\n extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];\n extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];\n extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];\n+extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];\n extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[];\n extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];\n extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];\n",
    "prefixes": []
}