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GET /api/patches/808199/?format=api
{ "id": 808199, "url": "http://patchwork.ozlabs.org/api/patches/808199/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504177652-32492-1-git-send-email-Ashish.Kumar@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504177652-32492-1-git-send-email-Ashish.Kumar@nxp.com>", "list_archive_url": null, "date": "2017-08-31T11:07:31", "name": "[U-Boot,v3,1/2] armv8: fsl-layerscape: Support to add RGMII for ls1088aqds", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "1d35c036839e1d3123293dc6b4ca12979e9cf274", "submitter": { "id": 68053, "url": "http://patchwork.ozlabs.org/api/people/68053/?format=api", "name": "Ashish Kumar", "email": "Ashish.kumar@nxp.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504177652-32492-1-git-send-email-Ashish.Kumar@nxp.com/mbox/", "series": [ { "id": 797, "url": "http://patchwork.ozlabs.org/api/series/797/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=797", "date": "2017-08-31T11:07:32", "name": "[U-Boot,v3,1/2] armv8: fsl-layerscape: Support to add RGMII for ls1088aqds", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/797/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808199/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808199/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Thu, 31 Aug 2017 04:07:36 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=BAD_ENC_HEADER,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,\n\tSPF_HELO_PASS autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Ashish Kumar <Ashish.Kumar@nxp.com>", "To": "<u-boot@lists.denx.de>", "Date": "Thu, 31 Aug 2017 16:37:31 +0530", "Message-ID": "<1504177652-32492-1-git-send-email-Ashish.Kumar@nxp.com>", "X-Mailer": "git-send-email 2.7.4", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131486512612631094;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(979002)(6009001)(336005)(39860400002)(39380400002)(2980300002)(1110001)(1109001)(339900001)(199003)(189002)(2351001)(105606002)(106466001)(50466002)(47776003)(48376002)(104016004)(5003940100001)(8676002)(81156014)(81166006)(110136004)(8936002)(50226002)(4326008)(626005)(356003)(305945005)(72206003)(2906002)(8656003)(68736007)(6666003)(36756003)(6916009)(498600001)(54906002)(189998001)(5660300001)(53936002)(77096006)(575784001)(86362001)(50986999)(97736004)(85426001)(969003)(989001)(999001)(1009001)(1019001);\n\tDIR:OUT; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:SN2PR03MB2269; ", "X-Forefront-PRVS": "04163EF38A", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Aug 2017 11:07:39.3287\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN2PR03MB2269", "Cc": "Amrita Kumari <amrita.kumari@nxp.com>", "Subject": "[U-Boot] [PATCH v3 1/2] armv8: fsl-layerscape: Support to add RGMII\n\tfor ls1088aqds", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "This patch adds support for RGMII protocol\n\nNXP's LDPAA2 support RGMII protocol. LS1088A is the\nfirst Soc supporting both RGMII and SGMII.\n\nSigned-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>\nSigned-off-by: Amrita Kumari <amrita.kumari@nxp.com>\nSigned-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>\n---\nv3:\nNo change\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 21 +++++++++++++++++\n arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++++\n .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 +\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 6 +++++\n board/freescale/ls1088a/eth_ls1088aqds.c | 1 -\n drivers/net/ldpaa_eth/ldpaa_wriop.c | 9 ++++++++\n drivers/net/ldpaa_eth/ls1088a.c | 27 ++++++++++++++++++++++\n include/fsl-mc/ldpaa_wriop.h | 2 ++\n 8 files changed, 70 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex 9290268..2af7a76 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -57,6 +57,8 @@ config ARCH_LS1088A\n \tselect SYS_FSL_DDR\n \tselect SYS_FSL_DDR_LE\n \tselect SYS_FSL_DDR_VER_50\n+\tselect SYS_FSL_EC1\n+\tselect SYS_FSL_EC2\n \tselect SYS_FSL_ERRATUM_A009803\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010165\n@@ -64,6 +66,7 @@ config ARCH_LS1088A\n \tselect SYS_FSL_ERRATUM_A008850\n \tselect SYS_FSL_HAS_CCI400\n \tselect SYS_FSL_HAS_DDR4\n+\tselect SYS_FSL_HAS_RGMII\n \tselect SYS_FSL_HAS_SEC\n \tselect SYS_FSL_SEC_COMPAT_5\n \tselect SYS_FSL_SEC_LE\n@@ -406,6 +409,18 @@ config RESV_RAM\n \t be at the high end of physical memory. The reserve RAM may be\n \t excluded from memory bank(s) passed to OS, or marked as reserved.\n \n+config SYS_FSL_EC1\n+\tbool\n+\thelp\n+\t Ethernet controller 1, this is connected to MAC3.\n+\t Provides DPAA2 capabilities\n+\n+config SYS_FSL_EC2\n+\tbool\n+\thelp\n+\t Ethernet controller 2, this is connected to MAC4.\n+\t Provides DPAA2 capabilities\n+\n config SYS_FSL_ERRATUM_A008336\n \tbool\n \n@@ -430,6 +445,12 @@ config SYS_FSL_ERRATUM_A009660\n config SYS_FSL_ERRATUM_A009929\n \tbool\n \n+\n+config SYS_FSL_HAS_RGMII\n+\tbool\n+\tdepends on SYS_FSL_EC1 || SYS_FSL_EC2\n+\n+\n config SYS_MC_RSV_MEM_ALIGN\n \thex \"Management Complex reserved memory alignment\"\n \tdepends on RESV_RAM\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\nindex ec58065..3c9a5ed 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\n@@ -517,6 +517,10 @@ int arch_early_init_r(void)\n \t\t\tprintf(\"Did not wake secondary cores\\n\");\n \t}\n \n+#ifdef CONFIG_SYS_FSL_HAS_RGMII\n+\tfsl_rgmii_init();\n+#endif\n+\n #ifdef CONFIG_SYS_HAS_SERDES\n \tfsl_serdes_init();\n #endif\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\nindex a2c7578..12fd6b8 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\n@@ -159,6 +159,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device);\n enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);\n int is_serdes_prtcl_valid(int serdes, u32 prtcl);\n int serdes_get_number(int serdes, int cfg);\n+void fsl_rgmii_init(void);\n \n #ifdef CONFIG_FSL_LSCH2\n const char *serdes_clock_to_string(u32 clock);\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 99a7413..ffc5fa2 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -247,6 +247,12 @@ struct ccsr_gur {\n #define FSL_CHASSIS3_SRDS1_REGSR\t29\n #define FSL_CHASSIS3_SRDS2_REGSR\t29\n #elif defined(CONFIG_ARCH_LS1088A)\n+#define FSL_CHASSIS3_EC1_REGSR 26\n+#define FSL_CHASSIS3_EC2_REGSR 26\n+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007\n+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0\n+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038\n+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3\n #define\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK\t0xFFFF0000\n #define\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT\t16\n #define\tFSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK\t0x0000FFFF\ndiff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c\nindex a912ff7..a973457 100644\n--- a/board/freescale/ls1088a/eth_ls1088aqds.c\n+++ b/board/freescale/ls1088a/eth_ls1088aqds.c\n@@ -597,7 +597,6 @@ int board_eth_init(bd_t *bis)\n \n \t/* Register the real MDIO1 bus */\n \tfm_memac_mdio_init(bis, memac_mdio0_info);\n-\n \t/* Register the muxing front-ends to the MDIO buses */\n \tls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);\n \tls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);\ndiff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c\nindex f7f26c2..831a330 100644\n--- a/drivers/net/ldpaa_eth/ldpaa_wriop.c\n+++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c\n@@ -37,6 +37,15 @@ void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)\n \t}\n }\n \n+void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if)\n+{\n+\tdpmac_info[dpmac_id].enabled = 1;\n+\tdpmac_info[dpmac_id].id = dpmac_id;\n+\tdpmac_info[dpmac_id].phy_addr = -1;\n+\tdpmac_info[dpmac_id].enet_if = enet_if;\n+}\n+\n+\n /*TODO what it do */\n static int wriop_dpmac_to_index(int dpmac_id)\n {\ndiff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c\nindex 703945c..061935e 100644\n--- a/drivers/net/ldpaa_eth/ls1088a.c\n+++ b/drivers/net/ldpaa_eth/ls1088a.c\n@@ -8,6 +8,7 @@\n #include <fsl-mc/ldpaa_wriop.h>\n #include <asm/io.h>\n #include <asm/arch/fsl_serdes.h>\n+#include <asm/arch/soc.h>\n \n u32 dpmac_to_devdisr[] = {\n \t[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,\n@@ -85,3 +86,29 @@ void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)\n \t\tbreak;\n \t}\n }\n+\n+#ifdef CONFIG_SYS_FSL_HAS_RGMII\n+void fsl_rgmii_init(void)\n+{\n+\tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n+\tu32 ec;\n+\n+#ifdef CONFIG_SYS_FSL_EC1\n+\tec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])\n+\t\t& FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;\n+\tec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;\n+\n+\tif (!ec)\n+\t\twriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);\n+#endif\n+\n+#ifdef CONFIG_SYS_FSL_EC2\n+\tec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])\n+\t\t& FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;\n+\tec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;\n+\n+\tif (!ec)\n+\t\twriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);\n+#endif\n+}\n+#endif\ndiff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h\nindex 8ae0fc0..0ca4956 100644\n--- a/include/fsl-mc/ldpaa_wriop.h\n+++ b/include/fsl-mc/ldpaa_wriop.h\n@@ -69,4 +69,6 @@ void wriop_dpmac_disable(int);\n void wriop_dpmac_enable(int);\n phy_interface_t wriop_dpmac_enet_if(int, int);\n void wriop_init_dpmac_qsgmii(int, int);\n+void wriop_init_rgmii(void);\n+void wriop_init_dpmac_enet_if(int , phy_interface_t);\n #endif\t/* __LDPAA_WRIOP_H */\n", "prefixes": [ "U-Boot", "v3", "1/2" ] }