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GET /api/patches/808172/?format=api
{ "id": 808172, "url": "http://patchwork.ozlabs.org/api/patches/808172/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504176175-31663-1-git-send-email-Ashish.Kumar@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504176175-31663-1-git-send-email-Ashish.Kumar@nxp.com>", "list_archive_url": null, "date": "2017-08-31T10:42:53", "name": "[U-Boot,v5,1/3] armv8: ls1088a: Add NXP LS1088A SoC support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "05162e718e6d0c2d61311d93b26687234cc40a39", "submitter": { "id": 68053, "url": "http://patchwork.ozlabs.org/api/people/68053/?format=api", "name": "Ashish Kumar", "email": "Ashish.kumar@nxp.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504176175-31663-1-git-send-email-Ashish.Kumar@nxp.com/mbox/", "series": [ { "id": 792, "url": "http://patchwork.ozlabs.org/api/series/792/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=792", "date": "2017-08-31T10:42:53", "name": "[U-Boot,v5,1/3] armv8: ls1088a: Add NXP LS1088A SoC support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/792/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808172/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808172/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": 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(version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1341.15\n\tvia Frontend Transport; Thu, 31 Aug 2017 10:43:03 +0000", "from ubuntu1604.ap.freescale.net (ubuntu1604.ap.freescale.net\n\t[10.232.133.7])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv7VAgxgp027748; Thu, 31 Aug 2017 03:43:00 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=BAD_ENC_HEADER,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,\n\tSPF_HELO_PASS\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Ashish Kumar <Ashish.Kumar@nxp.com>", "To": "<u-boot@lists.denx.de>", "Date": "Thu, 31 Aug 2017 16:12:53 +0530", "Message-ID": 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PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(601004)(2401047)(5005006)(13016025)(13018025)(8121501046)(10201501046)(93006095)(93001095)(3002001)(100000703101)(100105400095)(6055026)(6096035)(20161123561025)(201703131430075)(201703131441075)(201703131448075)(201703131433075)(201703161259150)(20161123556025)(20161123563025)(20161123565025)(20161123559100)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:BN6PR03MB3316; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BN6PR03MB3316; ", "X-Forefront-PRVS": "04163EF38A", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Aug 2017 10:43:03.5532\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN6PR03MB3316", "Cc": "Shaohui Xie <Shaohui.Xie@nxp.com>, Alison Wang <alison.wang@nxp.com>,\n\tRaghav Dogra <raghav.dogra@nxp.com>", "Subject": "[U-Boot] [PATCH v5 1/3] armv8: ls1088a: Add NXP LS1088A SoC support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "The QorIQ LS1088A processor is built on the Layerscape\narchitecture combining eight ARM A53 processor cores\nwith advanced, high-performance datapath acceleration\nand networks, peripheral interfaces required for\nnetworking, wireless infrastructure, and general-purpose\nembedded applications.\n\nLS1088A is compliant with the Layerscape Chassis Generation 3.\n\nFeatures summary:\n - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs\n - Cores are in 2 cluster of 4-cores each\n - Cache coherent interconnect (CCI-400)\n - One 64-bit DDR4 SDRAM memory controller with ECC\n - Data path acceleration architecture 2.0 (DPAA2)\n - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs\n - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc\n\nSigned-off-by: Alison Wang <alison.wang@nxp.com>\nSigned-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>\nSigned-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>\nSigned-off-by: Raghav Dogra <raghav.dogra@nxp.com>\nSigned-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>\n---\n\nv5:\nNo change\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 35 +++++-\n arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 +\n arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 43 ++++++-\n .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 19 ++++\n arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 126 +++++++++++++++++++++\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 +\n arch/arm/dts/fsl-ls1088a.dtsi | 78 +++++++++++++\n arch/arm/include/asm/arch-fsl-layerscape/config.h | 62 +++++++++-\n arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +\n .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 3 +-\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 11 ++\n arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 +\n .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 14 +++\n drivers/ddr/fsl/util.c | 2 +-\n drivers/net/ldpaa_eth/Makefile | 1 +\n drivers/net/ldpaa_eth/ls1088a.c | 87 ++++++++++++++\n 16 files changed, 482 insertions(+), 12 deletions(-)\n create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c\n create mode 100644 arch/arm/dts/fsl-ls1088a.dtsi\n create mode 100644 drivers/net/ldpaa_eth/ls1088a.c", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex eb8ccd1..aa2d0d1 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -50,6 +50,29 @@ config ARCH_LS1046A\n \tselect BOARD_EARLY_INIT_F\n \timply SCSI\n \n+config ARCH_LS1088A\n+\tbool\n+\tselect ARMV8_SET_SMPEN\n+\tselect FSL_LSCH3\n+\tselect SYS_FSL_DDR\n+\tselect SYS_FSL_DDR_LE\n+\tselect SYS_FSL_DDR_VER_50\n+\tselect SYS_FSL_ERRATUM_A009803\n+\tselect SYS_FSL_ERRATUM_A009942\n+\tselect SYS_FSL_ERRATUM_A010165\n+\tselect SYS_FSL_ERRATUM_A008511\n+\tselect SYS_FSL_ERRATUM_A008850\n+\tselect SYS_FSL_HAS_CCI400\n+\tselect SYS_FSL_HAS_DDR4\n+\tselect SYS_FSL_HAS_SEC\n+\tselect SYS_FSL_SEC_COMPAT_5\n+\tselect SYS_FSL_SEC_LE\n+\tselect SYS_FSL_SRDS_1\n+\tselect SYS_FSL_SRDS_2\n+\tselect FSL_TZASC_1\n+\tselect ARCH_EARLY_INIT_R\n+\tselect BOARD_EARLY_INIT_F\n+\n config ARCH_LS2080A\n \tbool\n \tselect ARMV8_SET_SMPEN\n@@ -100,7 +123,7 @@ config FSL_LSCH3\n \n config FSL_MC_ENET\n \tbool \"Management Complex network\"\n-\tdepends on ARCH_LS2080A\n+\tdepends on ARCH_LS2080A || ARCH_LS1088A\n \tdefault y\n \tselect RESV_RAM\n \thelp\n@@ -116,6 +139,7 @@ config FSL_PCIE_COMPAT\n \tdefault \"fsl,ls1043a-pcie\" if ARCH_LS1043A\n \tdefault \"fsl,ls1046a-pcie\" if ARCH_LS1046A\n \tdefault \"fsl,ls2080a-pcie\" if ARCH_LS2080A\n+\tdefault \"fsl,ls1088a-pcie\" if ARCH_LS1088A\n \thelp\n \t This compatible is used to find pci controller node in Kernel DT\n \t to complete fixup.\n@@ -230,6 +254,7 @@ config MAX_CPUS\n \tdefault 4 if ARCH_LS1043A\n \tdefault 4 if ARCH_LS1046A\n \tdefault 16 if ARCH_LS2080A\n+\tdefault 8 if ARCH_LS1088A\n \tdefault 1\n \thelp\n \t Set this number to the maximum number of possible CPUs in the SoC.\n@@ -261,10 +286,10 @@ config SYS_CCI400_OFFSET\n \n config SYS_FSL_IFC_BANK_COUNT\n \tint \"Maximum banks of Integrated flash controller\"\n-\tdepends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A\n+\tdepends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A\n \tdefault 4 if ARCH_LS1043A\n \tdefault 4 if ARCH_LS1046A\n-\tdefault 8 if ARCH_LS2080A\n+\tdefault 8 if ARCH_LS2080A || ARCH_LS1088A\n \n config SYS_FSL_HAS_CCI400\n \tbool\n@@ -313,6 +338,7 @@ config SYS_FSL_PCLK_DIV\n \tint \"Platform clock divider\"\n \tdefault 1 if ARCH_LS1043A\n \tdefault 1 if ARCH_LS1046A\n+\tdefault 1 if ARCH_LS1088A\n \tdefault 2\n \thelp\n \t This is the divider that is used to derive Platform clock from\n@@ -406,7 +432,8 @@ config SYS_FSL_ERRATUM_A009929\n config SYS_MC_RSV_MEM_ALIGN\n \thex \"Management Complex reserved memory alignment\"\n \tdepends on RESV_RAM\n-\tdefault 0x20000000\n+\tdefault 0x20000000 if ARCH_LS2080A\n+\tdefault 0x70000000 if ARCH_LS1088A\n \thelp\n \t Reserved memory needs to be aligned for MC to use. Default value\n \t is 512MB.\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile\nindex e3ce018..115c3fc 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile\n@@ -38,3 +38,7 @@ endif\n ifneq ($(CONFIG_ARCH_LS1046A),)\n obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o\n endif\n+\n+ifneq ($(CONFIG_ARCH_LS1088A),)\n+obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o\n+endif\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc\nindex 3ae16ae..276ab90 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc\n@@ -1,11 +1,12 @@\n SoC overview\n \n \t1. LS1043A\n-\t2. LS2080A\n-\t3. LS1012A\n-\t4. LS1046A\n-\t5. LS2088A\n-\t6. LS2081A\n+\t2. LS1088A\n+\t3. LS2080A\n+\t4. LS1012A\n+\t5. LS1046A\n+\t6. LS2088A\n+\t7. LS2081A\n \n LS1043A\n ---------\n@@ -45,6 +46,38 @@ The LS1043A SoC includes the following function and features:\n - Integrated flash controller supporting NAND and NOR flash\n - QorIQ platform's trust architecture 2.1\n \n+LS1088A\n+--------\n+The QorIQ LS1088A processor is built on the Layerscape\n+architecture combining eight ARM A53 processor cores\n+with advanced, high-performance datapath acceleration\n+and networks, peripheral interfaces required for\n+networking, wireless infrastructure, and general-purpose\n+embedded applications.\n+\n+LS1088A is compliant with the Layerscape Chassis Generation 3.\n+\n+Features summary:\n+ - 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs\n+ - Cores are in 2 cluster of 4-cores each\n+ - 1MB L2 - Cache per cluster\n+ - Cache coherent interconnect (CCI-400)\n+ - 1 64-bit DDR4 SDRAM memory controller with ECC\n+ - Data path acceleration architecture 2.0 (DPAA2)\n+ - 4-Lane 10GHz SerDes comprising of WRIOP\n+ - 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART)\n+ - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs\n+ - QSPI, SPI, IFC2.0 supporting NAND, NOR flash\n+ - 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc\n+ - 2 DUARTs\n+ - 4 I2C, GPIO\n+ - Thermal monitor unit(TMU)\n+ - 4 Flextimers and 1 generic timer\n+ - Support for hardware virtualization and partitioning enforcement\n+ - QorIQ platform's trust architecture 3.0\n+ - Service processor (SP) provides pre-boot initialization and secure-boot\n+ capabilities\n+\n LS2080A\n --------\n The LS2080A integrated multicore processor combines eight ARM Cortex-A57\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\nindex ef97556..179cac6 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n@@ -28,6 +28,20 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)\n \treturn;\n }\n \n+/*\n+ *The return value of this func is the serdes protocol used.\n+ *Typically this function is called number of times depending\n+ *upon the number of serdes blocks in the Silicon.\n+ *Zero is used to denote that no serdes was enabled,\n+ *this is the case when golden RCW was used where DPAA2 bring was\n+ *intentionally removed to achieve boot to prompt\n+*/\n+\n+__weak int serdes_get_number(int serdes, int cfg)\n+{\n+\treturn cfg;\n+}\n+\n int is_serdes_configured(enum srds_prtcl device)\n {\n \tint ret = 0;\n@@ -73,6 +87,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)\n \t\tprintf(\"invalid SerDes%d\\n\", sd);\n \t\tbreak;\n \t}\n+\n+\tcfg = serdes_get_number(sd, cfg);\n+\n \t/* Is serdes enabled at all? */\n \tif (cfg == 0)\n \t\treturn -ENODEV;\n@@ -99,6 +116,8 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,\n \n \tcfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;\n \tcfg >>= sd_prctl_shift;\n+\n+\tcfg = serdes_get_number(sd, cfg);\n \tprintf(\"Using SERDES%d Protocol: %d (0x%x)\\n\", sd + 1, cfg, cfg);\n \n \tif (!is_serdes_prtcl_valid(sd, cfg))\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c\nnew file mode 100644\nindex 0000000..9f5cdd5\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c\n@@ -0,0 +1,126 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/fsl_serdes.h>\n+\n+struct serdes_config {\n+\tu8 ip_protocol;\n+\tu8 lanes[SRDS_MAX_LANES];\n+\tu8 rcw_lanes[SRDS_MAX_LANES];\n+};\n+\n+static struct serdes_config serdes1_cfg_tbl[] = {\n+\t/* SerDes 1 */\n+\t{0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 } },\n+\t{0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } },\n+\t{0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } },\n+\t{0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } },\n+\t{0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } },\n+\t{0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } },\n+\t{0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } },\n+\t{0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } },\n+\t{0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } },\n+\t{0x1D, {QSGMII_A, QSGMII_B, XFI1, XFI2 }, {4, 4, 1, 1 } },\n+\t{0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2 }, {4, 4, 3, 1 } },\n+\t{0x1F, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 2 } },\n+\t{0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } },\n+\t{0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } },\n+\t{0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } },\n+\t{0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } },\n+\t\t{}\n+};\n+static struct serdes_config serdes2_cfg_tbl[] = {\n+\t/* SerDes 2 */\n+\t{0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } },\n+\t{0x0D, {PCIE1, PCIE2, PCIE3, SATA1 }, {5, 5, 5, 9 } },\n+\t{0x0E, {PCIE1, PCIE1, PCIE2, SATA1 }, {7, 7, 6, 9 } },\n+\t{0x13, {PCIE1, PCIE1, PCIE3, PCIE3 }, {7, 7, 7, 7 } },\n+\t{0x14, {PCIE1, PCIE2, PCIE3, PCIE3 }, {5, 5, 7, 7 } },\n+\t{0x3C, {NONE, PCIE2, NONE, PCIE3 }, {0, 5, 0, 6 } },\n+\t{}\n+};\n+\n+static struct serdes_config *serdes_cfg_tbl[] = {\n+\tserdes1_cfg_tbl,\n+\tserdes2_cfg_tbl,\n+};\n+\n+int serdes_get_number(int serdes, int cfg)\n+{\n+\tstruct serdes_config *ptr;\n+\tint i, j, index, lnk;\n+\tint is_found, max_lane = SRDS_MAX_LANES;\n+\n+\tif (serdes >= ARRAY_SIZE(serdes_cfg_tbl))\n+\t\treturn 0;\n+\n+\tptr = serdes_cfg_tbl[serdes];\n+\n+\twhile (ptr->ip_protocol) {\n+\t\tis_found = 1;\n+\t\tfor (i = 0, j = max_lane - 1; i < max_lane; i++, j--) {\n+\t\t\tlnk = cfg & (0xf << 4 * i);\n+\t\t\tlnk = lnk >> (4 * i);\n+\n+\t\t\tindex = (serdes == FSL_SRDS_1) ? j : i;\n+\n+\t\t\tif (ptr->rcw_lanes[index] == lnk && is_found)\n+\t\t\t\tis_found = 1;\n+\t\t\telse\n+\t\t\t\tis_found = 0;\n+\t\t}\n+\n+\t\tif (is_found)\n+\t\t\treturn ptr->ip_protocol;\n+\t\tptr++;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)\n+{\n+\tstruct serdes_config *ptr;\n+\n+\tif (serdes >= ARRAY_SIZE(serdes_cfg_tbl))\n+\t\treturn 0;\n+\n+\tptr = serdes_cfg_tbl[serdes];\n+\twhile (ptr->ip_protocol) {\n+\t\tif (ptr->ip_protocol == cfg)\n+\t\t\treturn ptr->lanes[lane];\n+\t\tptr++;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int is_serdes_prtcl_valid(int serdes, u32 prtcl)\n+{\n+\tint i;\n+\tstruct serdes_config *ptr;\n+\n+\tif (serdes >= ARRAY_SIZE(serdes_cfg_tbl))\n+\t\treturn 0;\n+\n+\tptr = serdes_cfg_tbl[serdes];\n+\twhile (ptr->ip_protocol) {\n+\t\tif (ptr->ip_protocol == prtcl)\n+\t\t\tbreak;\n+\t\tptr++;\n+\t}\n+\n+\tif (!ptr->ip_protocol)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < SRDS_MAX_LANES; i++) {\n+\t\tif (ptr->lanes[i] != NONE)\n+\t\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex e13f183..83e2871 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -24,6 +24,7 @@\n #ifdef CONFIG_CHAIN_OF_TRUST\n #include <fsl_validate.h>\n #endif\n+#include <fsl_immap.h>\n \n DECLARE_GLOBAL_DATA_PTR;\n \ndiff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi\nnew file mode 100644\nindex 0000000..421d2de\n--- /dev/null\n+++ b/arch/arm/dts/fsl-ls1088a.dtsi\n@@ -0,0 +1,78 @@\n+/*\n+ * NXP ls1088a SOC common device tree source\n+ *\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+/ {\n+\tcompatible = \"fsl,ls1088a\";\n+\tinterrupt-parent = <&gic>;\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\tmemory@80000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x00000000 0x80000000 0 0x80000000>;\n+\t\t /* DRAM space - 1, size : 2 GB DRAM */\n+\t};\n+\n+\tgic: interrupt-controller@6000000 {\n+\t\tcompatible = \"arm,gic-v3\";\n+\t\treg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */\n+\t\t <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */\n+\t\t#interrupt-cells = <3>;\n+\t\tinterrupt-controller;\n+\t\tinterrupts = <1 9 0x4>;\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */\n+\t\t\t <1 14 0x8>, /* Physical Non-Secure PPI, active-low */\n+\t\t\t <1 11 0x8>, /* Virtual PPI, active-low */\n+\t\t\t <1 10 0x8>; /* Hypervisor PPI, active-low */\n+\t};\n+\n+\tserial0: serial@21c0500 {\n+\t\tdevice_type = \"serial\";\n+\t\tcompatible = \"fsl,ns16550\", \"ns16550a\";\n+\t\treg = <0x0 0x21c0500 0x0 0x100>;\n+\t\tclock-frequency = <0>;\t/* Updated by bootloader */\n+\t\tinterrupts = <0 32 0x1>; /* edge triggered */\n+\t};\n+\n+\tserial1: serial@21c0600 {\n+\t\tdevice_type = \"serial\";\n+\t\tcompatible = \"fsl,ns16550\", \"ns16550a\";\n+\t\treg = <0x0 0x21c0600 0x0 0x100>;\n+\t\tclock-frequency = <0>; \t/* Updated by bootloader */\n+\t\tinterrupts = <0 32 0x1>; /* edge triggered */\n+\t};\n+\n+\tfsl_mc: fsl-mc@80c000000 {\n+\t\tcompatible = \"fsl,qoriq-mc\";\n+\t\treg = <0x00000008 0x0c000000 0 0x40>,\t /* MC portal base */\n+\t\t <0x00000000 0x08340000 0 0x40000>; /* MC control reg */\n+\t};\n+\n+\tdspi: dspi@2100000 {\n+\t\tcompatible = \"fsl,vf610-dspi\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x2100000 0x0 0x10000>;\n+\t\tinterrupts = <0 26 0x4>; /* Level high type */\n+\t\tnum-cs = <6>;\n+\t};\n+\n+\tqspi: quadspi@1550000 {\n+\t\tcompatible = \"fsl,vf610-qspi\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0 0x20c0000 0x0 0x10000>,\n+\t\t\t<0x0 0x20000000 0x0 0x10000000>;\n+\t\treg-names = \"QuadSPI\", \"QuadSPI-memory\";\n+\t\tnum-cs = <4>;\n+\t};\n+};\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h\nindex 79e94f9..a7098be 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h\n@@ -116,6 +116,67 @@\n #define CONFIG_SYS_FSL_ERRATUM_A008751\n \n #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC\t\t1\n+\n+#elif defined(CONFIG_ARCH_LS1088A)\n+#define CONFIG_SYS_FSL_NUM_CC_PLLS\t\t3\n+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS\t\t{ 1, 1 }\n+#define CONFIG_GICV3\n+#define CONFIG_FSL_TZPC_BP147\n+#define CONFIG_FSL_TZASC_400\n+#define CONFIG_SYS_PAGE_SIZE\t\t0x10000\n+\n+#define\tSRDS_MAX_LANES\t4\n+\n+/* TZ Protection Controller Definitions */\n+#define TZPC_BASE\t\t\t\t0x02200000\n+#define TZPCR0SIZE_BASE\t\t\t\t(TZPC_BASE)\n+#define TZPCDECPROT_0_STAT_BASE\t\t\t(TZPC_BASE + 0x800)\n+#define TZPCDECPROT_0_SET_BASE\t\t\t(TZPC_BASE + 0x804)\n+#define TZPCDECPROT_0_CLR_BASE\t\t\t(TZPC_BASE + 0x808)\n+#define TZPCDECPROT_1_STAT_BASE\t\t\t(TZPC_BASE + 0x80C)\n+#define TZPCDECPROT_1_SET_BASE\t\t\t(TZPC_BASE + 0x810)\n+#define TZPCDECPROT_1_CLR_BASE\t\t\t(TZPC_BASE + 0x814)\n+#define TZPCDECPROT_2_STAT_BASE\t\t\t(TZPC_BASE + 0x818)\n+#define TZPCDECPROT_2_SET_BASE\t\t\t(TZPC_BASE + 0x81C)\n+#define TZPCDECPROT_2_CLR_BASE\t\t\t(TZPC_BASE + 0x820)\n+\n+/* Generic Interrupt Controller Definitions */\n+#define GICD_BASE\t\t\t0x06000000\n+#define GICR_BASE\t\t\t0x06100000\n+\n+/* SMMU Defintions */\n+#define SMMU_BASE\t\t\t0x05000000 /* GR0 Base */\n+\n+/* DDR */\n+#define CONFIG_SYS_DDR_BLOCK1_SIZE\t((phys_size_t)2 << 30)\n+#define CONFIG_MAX_MEM_MAPPED\t\tCONFIG_SYS_DDR_BLOCK1_SIZE\n+\n+#define CONFIG_SYS_FSL_CCSR_GUR_LE\n+#define CONFIG_SYS_FSL_CCSR_SCFG_LE\n+#define CONFIG_SYS_FSL_ESDHC_LE\n+#define CONFIG_SYS_FSL_IFC_LE\n+#define CONFIG_SYS_FSL_PEX_LUT_LE\n+\n+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN\n+\n+/* SFP */\n+#define CONFIG_SYS_FSL_SFP_VER_3_4\n+#define CONFIG_SYS_FSL_SFP_LE\n+#define CONFIG_SYS_FSL_SRK_LE\n+\n+/* Security Monitor */\n+#define CONFIG_SYS_FSL_SEC_MON_LE\n+\n+/* Secure Boot */\n+#define CONFIG_ESBC_HDR_LS\n+\n+/* DCFG - GUR */\n+#define CONFIG_SYS_FSL_CCSR_GUR_LE\n+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC\t1\n+#define CONFIG_SYS_FSL_OCRAM_BASE\t0x18000000 /* initial RAM */\n+#define SYS_FSL_OCRAM_SPACE_SIZE\t0x00200000 /* 2M space */\n+#define CONFIG_SYS_FSL_OCRAM_SIZE\t0x00020000 /* Real size 128K */\n+\n #elif defined(CONFIG_FSL_LSCH2)\n #define CONFIG_SYS_FSL_OCRAM_BASE\t\t0x10000000 /* initial RAM */\n #define SYS_FSL_OCRAM_SPACE_SIZE\t\t0x00200000 /* 2M space */\n@@ -218,7 +279,6 @@\n #define GICC_BASE\t\t0x01420000\n \n #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC\t\t1\n-\n #else\n #error SoC not defined\n #endif\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h\nindex c4e5ecc..0126783 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h\n@@ -24,6 +24,10 @@ static struct cpu_type cpu_type_list[] = {\n \tCPU_TYPE_ENTRY(LS1026A, LS1026A, 2),\n \tCPU_TYPE_ENTRY(LS2040A, LS2040A, 4),\n \tCPU_TYPE_ENTRY(LS1012A, LS1012A, 1),\n+\tCPU_TYPE_ENTRY(LS1088A, LS1088A, 8),\n+\tCPU_TYPE_ENTRY(LS1084A, LS1084A, 8),\n+\tCPU_TYPE_ENTRY(LS1048A, LS1048A, 4),\n+\tCPU_TYPE_ENTRY(LS1044A, LS1044A, 4),\n };\n \n #ifndef CONFIG_SYS_DCACHE_OFF\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\nindex a8f9a50..a2c7578 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\n@@ -9,7 +9,7 @@\n \n #include <config.h>\n \n-#ifdef CONFIG_ARCH_LS2080A\n+#ifdef CONFIG_FSL_LSCH3\n enum srds_prtcl {\n \t/*\n \t * Nobody will check whether the device 'NONE' has been configured,\n@@ -158,6 +158,7 @@ void fsl_serdes_init(void);\n int serdes_get_first_lane(u32 sd, enum srds_prtcl device);\n enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);\n int is_serdes_prtcl_valid(int serdes, u32 prtcl);\n+int serdes_get_number(int serdes, int cfg);\n \n #ifdef CONFIG_FSL_LSCH2\n const char *serdes_clock_to_string(u32 clock);\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 59410aa..99a7413 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -246,6 +246,17 @@ struct ccsr_gur {\n #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT\tFSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT\n #define FSL_CHASSIS3_SRDS1_REGSR\t29\n #define FSL_CHASSIS3_SRDS2_REGSR\t29\n+#elif defined(CONFIG_ARCH_LS1088A)\n+#define\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK\t0xFFFF0000\n+#define\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT\t16\n+#define\tFSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK\t0x0000FFFF\n+#define\tFSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT\t0\n+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK\n+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT\n+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK\tFSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK\n+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT\tFSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT\n+#define FSL_CHASSIS3_SRDS1_REGSR\t29\n+#define FSL_CHASSIS3_SRDS2_REGSR\t30\n #endif\n #define RCW_SB_EN_REG_INDEX\t9\n #define RCW_SB_EN_MASK\t\t0x00000400\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h\nindex aeb1273..ea8aced 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h\n@@ -57,6 +57,10 @@ struct cpu_type {\n #define SVR_LS1023A\t\t0x879208\n #define SVR_LS1046A\t\t0x870700\n #define SVR_LS1026A\t\t0x870708\n+#define SVR_LS1048A\t\t0x870320\n+#define SVR_LS1084A\t\t0x870302\n+#define SVR_LS1088A\t\t0x870300\n+#define SVR_LS1044A\t\t0x870322\n #define SVR_LS2045A\t\t0x870120\n #define SVR_LS2080A\t\t0x870110\n #define SVR_LS2085A\t\t0x870100\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\nindex d7d527d..d1891c4 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\n@@ -66,12 +66,26 @@\n #define FSL_USB2_STREAM_ID\t\t2\n #define FSL_SDMMC_STREAM_ID\t\t3\n #define FSL_SATA1_STREAM_ID\t\t4\n+\n+#if defined(CONFIG_ARCH_LS2080A)\n #define FSL_SATA2_STREAM_ID\t\t5\n+#endif\n+\n+#if defined(CONFIG_ARCH_LS2080A)\n #define FSL_DMA_STREAM_ID\t\t6\n+#elif defined(CONFIG_ARCH_LS1088A)\n+#define FSL_DMA_STREAM_ID\t\t5\n+#endif\n \n /* PCI - programmed in PEXn_LUT */\n #define FSL_PEX_STREAM_ID_START\t\t7\n+\n+#if defined(CONFIG_ARCH_LS2080A)\n #define FSL_PEX_STREAM_ID_END\t\t22\n+#elif defined(CONFIG_ARCH_LS1088A)\n+#define FSL_PEX_STREAM_ID_END\t\t18\n+#endif\n+\n \n /* DPAA2 - set in MC DPC and alloced by MC */\n #define FSL_DPAA2_STREAM_ID_START\t23\ndiff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c\nindex 0a305b3..d6e6e78 100644\n--- a/drivers/ddr/fsl/util.c\n+++ b/drivers/ddr/fsl/util.c\n@@ -390,7 +390,7 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,\n \n void remove_unused_controllers(fsl_ddr_info_t *info)\n {\n-#ifdef CONFIG_FSL_LSCH3\n+#ifdef CONFIG_SYS_FSL_HAS_CCN504\n \tint i;\n \tu64 nodeid;\n \tvoid *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);\ndiff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile\nindex 08675ec..13ecd38 100644\n--- a/drivers/net/ldpaa_eth/Makefile\n+++ b/drivers/net/ldpaa_eth/Makefile\n@@ -7,3 +7,4 @@\n obj-y += ldpaa_wriop.o\n obj-y += ldpaa_eth.o\n obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o\n+obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o\ndiff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c\nnew file mode 100644\nindex 0000000..703945c\n--- /dev/null\n+++ b/drivers/net/ldpaa_eth/ls1088a.c\n@@ -0,0 +1,87 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+#include <common.h>\n+#include <phy.h>\n+#include <fsl-mc/ldpaa_wriop.h>\n+#include <asm/io.h>\n+#include <asm/arch/fsl_serdes.h>\n+\n+u32 dpmac_to_devdisr[] = {\n+\t[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,\n+\t[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,\n+\t[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,\n+\t[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,\n+\t[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,\n+\t[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,\n+\t[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,\n+\t[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,\n+\t[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,\n+\t[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,\n+};\n+\n+static int is_device_disabled(int dpmac_id)\n+{\n+\tstruct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;\n+\tu32 devdisr2 = in_le32(&gur->devdisr2);\n+\n+\treturn dpmac_to_devdisr[dpmac_id] & devdisr2;\n+}\n+\n+void wriop_dpmac_disable(int dpmac_id)\n+{\n+\tstruct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;\n+\n+\tsetbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);\n+}\n+\n+void wriop_dpmac_enable(int dpmac_id)\n+{\n+\tstruct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;\n+\n+\tclrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);\n+}\n+\n+phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)\n+{\n+\tenum srds_prtcl;\n+\n+\tif (is_device_disabled(dpmac_id + 1))\n+\t\treturn PHY_INTERFACE_MODE_NONE;\n+\n+\tswitch (lane_prtcl) {\n+\tcase SGMII1:\n+\tcase SGMII2:\n+\tcase SGMII3:\n+\tcase SGMII7:\n+\t\treturn PHY_INTERFACE_MODE_SGMII;\n+\t}\n+\n+\tif (lane_prtcl >= XFI1 && lane_prtcl <= XFI2)\n+\t\treturn PHY_INTERFACE_MODE_XGMII;\n+\n+\tif (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)\n+\t\treturn PHY_INTERFACE_MODE_QSGMII;\n+\n+\treturn PHY_INTERFACE_MODE_NONE;\n+}\n+\n+void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)\n+{\n+\tswitch (lane_prtcl) {\n+\tcase QSGMII_A:\n+\t\twriop_init_dpmac(sd, 3, (int)lane_prtcl);\n+\t\twriop_init_dpmac(sd, 4, (int)lane_prtcl);\n+\t\twriop_init_dpmac(sd, 5, (int)lane_prtcl);\n+\t\twriop_init_dpmac(sd, 6, (int)lane_prtcl);\n+\t\tbreak;\n+\tcase QSGMII_B:\n+\t\twriop_init_dpmac(sd, 7, (int)lane_prtcl);\n+\t\twriop_init_dpmac(sd, 8, (int)lane_prtcl);\n+\t\twriop_init_dpmac(sd, 9, (int)lane_prtcl);\n+\t\twriop_init_dpmac(sd, 10, (int)lane_prtcl);\n+\t\tbreak;\n+\t}\n+}\n", "prefixes": [ "U-Boot", "v5", "1/3" ] }