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GET /api/patches/808133/?format=api
{ "id": 808133, "url": "http://patchwork.ozlabs.org/api/patches/808133/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504167642-14922-2-git-send-email-xieyisheng1@huawei.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504167642-14922-2-git-send-email-xieyisheng1@huawei.com>", "list_archive_url": null, "date": "2017-08-31T08:20:37", "name": "[RFC,1/6] dt-bindings: document stall and PASID properties for IOMMU masters", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "7463d0366833aabb53e664a68053663200c291ed", "submitter": { "id": 72263, "url": "http://patchwork.ozlabs.org/api/people/72263/?format=api", "name": "Yisheng Xie", "email": "xieyisheng1@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504167642-14922-2-git-send-email-xieyisheng1@huawei.com/mbox/", "series": [ { "id": 770, "url": "http://patchwork.ozlabs.org/api/series/770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=770", "date": "2017-08-31T08:20:37", "name": "Add platform device SVM support for ARM SMMUv3", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808133/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808133/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjbCz5fDzz9s7c\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 31 Aug 2017 18:30:23 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751419AbdHaI3Y (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tThu, 31 Aug 2017 04:29:24 -0400", "from szxga04-in.huawei.com ([45.249.212.190]:5496 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751040AbdHaI3U (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Thu, 31 Aug 2017 04:29:20 -0400", "from 172.30.72.59 (EHLO DGGEMS402-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGG21826; Thu, 31 Aug 2017 16:29:12 +0800 (CST)", "from linux-ibm.site (10.175.102.37) by\n\tDGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP\n\tServer id 14.3.301.0; Thu, 31 Aug 2017 16:28:59 +0800" ], "From": "Yisheng Xie <xieyisheng1@huawei.com>", "To": "<jean-philippe.brucker@arm.com>", "CC": "<joro@8bytes.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com>,\n\t<lorenzo.pieralisi@arm.com>, <hanjun.guo@linaro.org>,\n\t<sudeep.holla@arm.com>, <rjw@rjwysocki.net>, <lenb@kernel.org>,\n\t<will.deacon@arm.com>, <robin.murphy@arm.com>,\n\t<robert.moore@intel.com>, <lv.zheng@intel.com>,\n\t<iommu@lists.linux-foundation.org>, <devicetree@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>, <devel@acpica.org>,\n\t<liubo95@huawei.com>, <chenjiankang1@huawei.com>, <xieyisheng@huawei.com>", "Subject": "[RFC PATCH 1/6] dt-bindings: document stall and PASID properties for\n\tIOMMU masters", "Date": "Thu, 31 Aug 2017 16:20:37 +0800", "Message-ID": "<1504167642-14922-2-git-send-email-xieyisheng1@huawei.com>", "X-Mailer": "git-send-email 1.7.12.4", "In-Reply-To": "<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>", "References": "<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.175.102.37]", "X-CFilter-Loop": "Reflected", "X-Mirapoint-Virus-RAPID-Raw": "score=unknown(0),\n\trefid=str=0001.0A010203.59A7C8DB.002E, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32", "X-Mirapoint-Loop-Id": "8ba126ef6085750d0f2fbf455daa2042", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "From: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>\n\nDocument the bindings for stall and PASID capable platform devices.\n\nSigned-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>\n---\n Documentation/devicetree/bindings/iommu/iommu.txt | 13 +++++++++++++\n 1 file changed, 13 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/iommu/iommu.txt b/Documentation/devicetree/bindings/iommu/iommu.txt\nindex 5a8b462..7355d7f 100644\n--- a/Documentation/devicetree/bindings/iommu/iommu.txt\n+++ b/Documentation/devicetree/bindings/iommu/iommu.txt\n@@ -86,6 +86,19 @@ have a means to turn off translation. But it is invalid in such cases to\n disable the IOMMU's device tree node in the first place because it would\n prevent any driver from properly setting up the translations.\n \n+Optional properties:\n+--------------------\n+- dma-can-stall: When present, the master can wait for a DMA transaction\n+ to be handled by the IOMMU and can recover from a fault. For example, if\n+ the page accessed by the DMA transaction isn't mapped, some IOMMUs are\n+ able to stall the transaction and let the OS populate the page tables.\n+ The IOMMU then performs the transaction if the fault was successfully\n+ handled, or aborts the transaction otherwise.\n+\n+- pasid-bits: Some masters support multiple address spaces for DMA. By\n+ tagging DMA transactions with an address space identifier. By default,\n+ this is 0, which means that the device only has one address space.\n+\n \n Notes:\n ======\n", "prefixes": [ "RFC", "1/6" ] }