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GET /api/patches/808087/?format=api
{ "id": 808087, "url": "http://patchwork.ozlabs.org/api/patches/808087/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504163947.4681.10.camel@hbabu-laptop/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504163947.4681.10.camel@hbabu-laptop>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504163947.4681.10.camel@hbabu-laptop/", "date": "2017-08-31T07:19:07", "name": "[V4,7/7] crypto/nx: Add P9 NX support for 842 compression engine", "commit_ref": "b0d6c9bab5e41d07f2bece1ef8c81cd2175b5f88", "pull_url": null, "state": "accepted", "archived": false, "hash": "0c4ba27318161e24487d316e132c18387156b44b", "submitter": { "id": 12875, "url": "http://patchwork.ozlabs.org/api/people/12875/?format=api", "name": "Haren Myneni", "email": "haren@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504163947.4681.10.camel@hbabu-laptop/mbox/", "series": [ { "id": 757, "url": "http://patchwork.ozlabs.org/api/series/757/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=757", "date": "2017-08-31T07:10:13", "name": "Enable NX 842 compression engine on Power9", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/757/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808087/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808087/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjYjp46gkz9sNc\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 31 Aug 2017 17:22:38 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xjYjp3FRJzDrJd\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 31 Aug 2017 17:22:38 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xjYfX6Td6zDqk2\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tThu, 31 Aug 2017 17:19:48 +1000 (AEST)", "from pps.filterd (m0098419.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7V7JgL7042603\n\tfor <linuxppc-dev@lists.ozlabs.org>; Thu, 31 Aug 2017 03:19:46 -0400", "from e31.co.us.ibm.com (e31.co.us.ibm.com [32.97.110.149])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2cpa77xghm-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Thu, 31 Aug 2017 03:19:44 -0400", "from localhost\n\tby e31.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from <haren@linux.vnet.ibm.com>; \n\tThu, 31 Aug 2017 01:19:23 -0600", "from b03cxnp07028.gho.boulder.ibm.com (9.17.130.15)\n\tby e31.co.us.ibm.com (192.168.1.131) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tThu, 31 Aug 2017 01:19:20 -0600", "from b03ledav006.gho.boulder.ibm.com\n\t(b03ledav006.gho.boulder.ibm.com [9.17.130.237])\n\tby b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v7V7JJU25767438; Thu, 31 Aug 2017 00:19:19 -0700", "from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 06B3DC6043;\n\tThu, 31 Aug 2017 01:19:19 -0600 (MDT)", "from [9.70.82.25] (unknown [9.70.82.25])\n\tby b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP id 3C9A2C603C;\n\tThu, 31 Aug 2017 01:19:18 -0600 (MDT)" ], "Subject": "[PATCH V4 7/7] crypto/nx: Add P9 NX support for 842 compression\n\tengine", "From": "Haren Myneni <haren@linux.vnet.ibm.com>", "To": "mpe@ellerman.id.au, herbert@gondor.apana.org.au", "Content-Type": "text/plain; charset=\"UTF-8\"", "Date": "Thu, 31 Aug 2017 00:19:07 -0700", "Mime-Version": "1.0", "X-Mailer": "Evolution 2.28.3 ", "Content-Transfer-Encoding": "7bit", "X-TM-AS-GCONF": "00", "x-cbid": "17083107-8235-0000-0000-00000C331880", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007640; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00910096; UDB=6.00456509;\n\tIPR=6.00690376; \n\tBA=6.00005562; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016938;\n\tXFM=3.00000015; UTC=2017-08-31 07:19:22", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17083107-8236-0000-0000-00003D74560D", "Message-Id": "<1504163947.4681.10.camel@hbabu-laptop>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-31_02:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708310112", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "mikey@neuling.org, linuxram@us.ibm.com, npiggin@gmail.com,\n\tsuka@us.ibm.com, \n\tlinux-crypto@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,\n\tddstreet@ieee.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "This patch adds P9 NX support for 842 compression engine. Virtual\nAccelerator Switchboard (VAS) is used to access 842 engine on P9.\n\nFor each NX engine per chip, setup receive window using\nvas_rx_win_open() which configures RxFIFo with FIFO address, lpid,\npid and tid values. This unique (lpid, pid, tid) combination will\nbe used to identify the target engine.\n\nFor crypto open request, open send window on the NX engine for\nthe corresponding chip / cpu where the open request is executed.\nThis send window will be closed upon crypto close request.\n\nNX provides high and normal priority FIFOs. For compression /\ndecompression requests, we use only hight priority FIFOs in kernel.\n\nEach NX request will be communicated to VAS using copy/paste\ninstructions with vas_copy_crb() / vas_paste_crb() functions.\n\nSigned-off-by: Haren Myneni <haren@us.ibm.com>\nReviewed-by: Ram Pai <linuxram@us.ibm.com>\n\n---\n drivers/crypto/nx/Kconfig | 1 +\n drivers/crypto/nx/nx-842-powernv.c | 377 ++++++++++++++++++++++++++++++++++++-\n 2 files changed, 372 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/crypto/nx/Kconfig b/drivers/crypto/nx/Kconfig\nindex ad7552a6998c..cd5dda9c48f4 100644\n--- a/drivers/crypto/nx/Kconfig\n+++ b/drivers/crypto/nx/Kconfig\n@@ -38,6 +38,7 @@ config CRYPTO_DEV_NX_COMPRESS_PSERIES\n config CRYPTO_DEV_NX_COMPRESS_POWERNV\n \ttristate \"Compression acceleration support on PowerNV platform\"\n \tdepends on PPC_POWERNV\n+\tdepends on PPC_VAS\n \tdefault y\n \thelp\n \t Support for PowerPC Nest (NX) compression acceleration. This\ndiff --git a/drivers/crypto/nx/nx-842-powernv.c b/drivers/crypto/nx/nx-842-powernv.c\nindex c0dd4c7e17d3..874ddf5e9087 100644\n--- a/drivers/crypto/nx/nx-842-powernv.c\n+++ b/drivers/crypto/nx/nx-842-powernv.c\n@@ -23,6 +23,7 @@\n #include <asm/prom.h>\n #include <asm/icswx.h>\n #include <asm/vas.h>\n+#include <asm/reg.h>\n \n MODULE_LICENSE(\"GPL\");\n MODULE_AUTHOR(\"Dan Streetman <ddstreet@ieee.org>\");\n@@ -32,6 +33,9 @@ MODULE_ALIAS_CRYPTO(\"842-nx\");\n \n #define WORKMEM_ALIGN\t(CRB_ALIGN)\n #define CSB_WAIT_MAX\t(5000) /* ms */\n+#define VAS_RETRIES\t(10)\n+/* # of requests allowed per RxFIFO at a time. 0 for unlimited */\n+#define MAX_CREDITS_PER_RXFIFO\t(1024)\n \n struct nx842_workmem {\n \t/* Below fields must be properly aligned */\n@@ -42,16 +46,27 @@ struct nx842_workmem {\n \n \tktime_t start;\n \n+\tstruct vas_window *txwin;\t/* Used with VAS function */\n \tchar padding[WORKMEM_ALIGN]; /* unused, to allow alignment */\n } __packed __aligned(WORKMEM_ALIGN);\n \n struct nx842_coproc {\n \tunsigned int chip_id;\n \tunsigned int ct;\n-\tunsigned int ci;\n+\tunsigned int ci;\t/* Coprocessor instance, used with icswx */\n+\tstruct {\n+\t\tstruct vas_window *rxwin;\n+\t\tint id;\n+\t} vas;\n \tstruct list_head list;\n };\n \n+/*\n+ * Send the request to NX engine on the chip for the corresponding CPU\n+ * where the process is executing. Use with VAS function.\n+ */\n+static DEFINE_PER_CPU(struct nx842_coproc *, coproc_inst);\n+\n /* no cpu hotplug on powernv, so this list never changes after init */\n static LIST_HEAD(nx842_coprocs);\n static unsigned int nx842_ct;\t/* used in icswx function */\n@@ -513,6 +528,104 @@ static int nx842_exec_icswx(const unsigned char *in, unsigned int inlen,\n }\n \n /**\n+ * nx842_exec_vas - compress/decompress data using the 842 algorithm\n+ *\n+ * (De)compression provided by the NX842 coprocessor on IBM PowerNV systems.\n+ * This compresses or decompresses the provided input buffer into the provided\n+ * output buffer.\n+ *\n+ * Upon return from this function @outlen contains the length of the\n+ * output data. If there is an error then @outlen will be 0 and an\n+ * error will be specified by the return code from this function.\n+ *\n+ * The @workmem buffer should only be used by one function call at a time.\n+ *\n+ * @in: input buffer pointer\n+ * @inlen: input buffer size\n+ * @out: output buffer pointer\n+ * @outlenp: output buffer size pointer\n+ * @workmem: working memory buffer pointer, size determined by\n+ * nx842_powernv_driver.workmem_size\n+ * @fc: function code, see CCW Function Codes in nx-842.h\n+ *\n+ * Returns:\n+ * 0\t\tSuccess, output of length @outlenp stored in the buffer\n+ *\t\tat @out\n+ * -ENODEV\tHardware unavailable\n+ * -ENOSPC\tOutput buffer is to small\n+ * -EMSGSIZE\tInput buffer too large\n+ * -EINVAL\tbuffer constraints do not fix nx842_constraints\n+ * -EPROTO\thardware error during operation\n+ * -ETIMEDOUT\thardware did not complete operation in reasonable time\n+ * -EINTR\toperation was aborted\n+ */\n+static int nx842_exec_vas(const unsigned char *in, unsigned int inlen,\n+\t\t\t\t unsigned char *out, unsigned int *outlenp,\n+\t\t\t\t void *workmem, int fc)\n+{\n+\tstruct coprocessor_request_block *crb;\n+\tstruct coprocessor_status_block *csb;\n+\tstruct nx842_workmem *wmem;\n+\tstruct vas_window *txwin;\n+\tint ret, i = 0;\n+\tu32 ccw;\n+\tunsigned int outlen = *outlenp;\n+\n+\twmem = PTR_ALIGN(workmem, WORKMEM_ALIGN);\n+\n+\t*outlenp = 0;\n+\n+\tcrb = &wmem->crb;\n+\tcsb = &crb->csb;\n+\n+\tret = nx842_config_crb(in, inlen, out, outlen, wmem);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tccw = 0;\n+\tccw = SET_FIELD(CCW_FC_842, ccw, fc);\n+\tcrb->ccw = cpu_to_be32(ccw);\n+\n+\ttxwin = wmem->txwin;\n+\t/* shoudn't happen, we don't load without a coproc */\n+\tif (!txwin) {\n+\t\tpr_err_ratelimited(\"NX-842 coprocessor is not available\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdo {\n+\t\twmem->start = ktime_get();\n+\t\tpreempt_disable();\n+\t\t/*\n+\t\t * VAS copy CRB into L2 cache. Refer <asm/vas.h>.\n+\t\t * @crb and @offset.\n+\t\t */\n+\t\tvas_copy_crb(crb, 0);\n+\n+\t\t/*\n+\t\t * VAS paste previously copied CRB to NX.\n+\t\t * @txwin, @offset and @last (must be true).\n+\t\t */\n+\t\tret = vas_paste_crb(txwin, 0, 1);\n+\t\tpreempt_enable();\n+\t\t/*\n+\t\t * Retry copy/paste function for VAS failures.\n+\t\t */\n+\t} while (ret && (i++ < VAS_RETRIES));\n+\n+\tif (ret) {\n+\t\tpr_err_ratelimited(\"VAS copy/paste failed\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = wait_for_csb(wmem, csb);\n+\tif (!ret)\n+\t\t*outlenp = be32_to_cpu(csb->count);\n+\n+\treturn ret;\n+}\n+\n+/**\n * nx842_powernv_compress - Compress data using the 842 algorithm\n *\n * Compression provided by the NX842 coprocessor on IBM PowerNV systems.\n@@ -576,6 +689,201 @@ static inline void nx842_add_coprocs_list(struct nx842_coproc *coproc,\n \tlist_add(&coproc->list, &nx842_coprocs);\n }\n \n+/*\n+ * Identify chip ID for each CPU and save coprocesor adddress for the\n+ * corresponding NX engine in percpu coproc_inst.\n+ * coproc_inst is used in crypto_init to open send window on the NX instance\n+ * for the corresponding CPU / chip where the open request is executed.\n+ */\n+static void nx842_set_per_cpu_coproc(struct nx842_coproc *coproc)\n+{\n+\tunsigned int i, chip_id;\n+\n+\tfor_each_possible_cpu(i) {\n+\t\tchip_id = cpu_to_chip_id(i);\n+\n+\t\tif (coproc->chip_id == chip_id)\n+\t\t\tper_cpu(coproc_inst, i) = coproc;\n+\t}\n+}\n+\n+\n+static struct vas_window *nx842_alloc_txwin(struct nx842_coproc *coproc)\n+{\n+\tstruct vas_window *txwin = NULL;\n+\tstruct vas_tx_win_attr txattr;\n+\n+\t/*\n+\t * Kernel requests will be high priority. So open send\n+\t * windows only for high priority RxFIFO entries.\n+\t */\n+\tvas_init_tx_win_attr(&txattr, coproc->ct);\n+\ttxattr.lpid = 0;\t/* lpid is 0 for kernel requests */\n+\ttxattr.pid = 0;\t\t/* pid is 0 for kernel requests */\n+\n+\t/*\n+\t * Open a VAS send window which is used to send request to NX.\n+\t */\n+\ttxwin = vas_tx_win_open(coproc->vas.id, coproc->ct, &txattr);\n+\tif (IS_ERR(txwin)) {\n+\t\tpr_err(\"ibm,nx-842: Can not open TX window: %ld\\n\",\n+\t\t\t\tPTR_ERR(txwin));\n+\t\treturn NULL;\n+\t}\n+\n+\treturn txwin;\n+}\n+\n+static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,\n+\t\t\t\t\tint vasid)\n+{\n+\tstruct vas_window *rxwin = NULL;\n+\tstruct vas_rx_win_attr rxattr;\n+\tstruct nx842_coproc *coproc;\n+\tu32 lpid, pid, tid, fifo_size;\n+\tu64 rx_fifo;\n+\tconst char *priority;\n+\tint ret;\n+\n+\tret = of_property_read_u64(dn, \"rx-fifo-address\", &rx_fifo);\n+\tif (ret) {\n+\t\tpr_err(\"Missing rx-fifo-address property\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = of_property_read_u32(dn, \"rx-fifo-size\", &fifo_size);\n+\tif (ret) {\n+\t\tpr_err(\"Missing rx-fifo-size property\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = of_property_read_u32(dn, \"lpid\", &lpid);\n+\tif (ret) {\n+\t\tpr_err(\"Missing lpid property\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = of_property_read_u32(dn, \"pid\", &pid);\n+\tif (ret) {\n+\t\tpr_err(\"Missing pid property\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = of_property_read_u32(dn, \"tid\", &tid);\n+\tif (ret) {\n+\t\tpr_err(\"Missing tid property\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = of_property_read_string(dn, \"priority\", &priority);\n+\tif (ret) {\n+\t\tpr_err(\"Missing priority property\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tcoproc = kzalloc(sizeof(*coproc), GFP_KERNEL);\n+\tif (!coproc)\n+\t\treturn -ENOMEM;\n+\n+\tif (!strcmp(priority, \"High\"))\n+\t\tcoproc->ct = VAS_COP_TYPE_842_HIPRI;\n+\telse if (!strcmp(priority, \"Normal\"))\n+\t\tcoproc->ct = VAS_COP_TYPE_842;\n+\telse {\n+\t\tpr_err(\"Invalid RxFIFO priority value\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto err_out;\n+\t}\n+\n+\tvas_init_rx_win_attr(&rxattr, coproc->ct);\n+\trxattr.rx_fifo = (void *)rx_fifo;\n+\trxattr.rx_fifo_size = fifo_size;\n+\trxattr.lnotify_lpid = lpid;\n+\trxattr.lnotify_pid = pid;\n+\trxattr.lnotify_tid = tid;\n+\trxattr.wcreds_max = MAX_CREDITS_PER_RXFIFO;\n+\n+\t/*\n+\t * Open a VAS receice window which is used to configure RxFIFO\n+\t * for NX.\n+\t */\n+\trxwin = vas_rx_win_open(vasid, coproc->ct, &rxattr);\n+\tif (IS_ERR(rxwin)) {\n+\t\tret = PTR_ERR(rxwin);\n+\t\tpr_err(\"setting RxFIFO with VAS failed: %d\\n\",\n+\t\t\tret);\n+\t\tgoto err_out;\n+\t}\n+\n+\tcoproc->vas.rxwin = rxwin;\n+\tcoproc->vas.id = vasid;\n+\tnx842_add_coprocs_list(coproc, chip_id);\n+\n+\t/*\n+\t * Kernel requests use only high priority FIFOs. So save coproc\n+\t * info in percpu coproc_inst which will be used to open send\n+\t * windows for crypto open requests later.\n+\t */\n+\tif (coproc->ct == VAS_COP_TYPE_842_HIPRI)\n+\t\tnx842_set_per_cpu_coproc(coproc);\n+\n+\treturn 0;\n+\n+err_out:\n+\tkfree(coproc);\n+\treturn ret;\n+}\n+\n+\n+static int __init nx842_powernv_probe_vas(struct device_node *pn)\n+{\n+\tstruct device_node *dn;\n+\tint chip_id, vasid, ret = 0;\n+\tint nx_fifo_found = 0;\n+\n+\tchip_id = of_get_ibm_chip_id(pn);\n+\tif (chip_id < 0) {\n+\t\tpr_err(\"ibm,chip-id missing\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor_each_compatible_node(dn, NULL, \"ibm,power9-vas-x\") {\n+\t\tif (of_get_ibm_chip_id(dn) == chip_id)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (!dn) {\n+\t\tpr_err(\"Missing VAS device node\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (of_property_read_u32(dn, \"ibm,vas-id\", &vasid)) {\n+\t\tpr_err(\"Missing ibm,vas-id device property\\n\");\n+\t\tof_node_put(dn);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tof_node_put(dn);\n+\n+\tfor_each_child_of_node(pn, dn) {\n+\t\tif (of_device_is_compatible(dn, \"ibm,p9-nx-842\")) {\n+\t\t\tret = vas_cfg_coproc_info(dn, chip_id, vasid);\n+\t\t\tif (ret) {\n+\t\t\t\tof_node_put(dn);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t\tnx_fifo_found++;\n+\t\t}\n+\t}\n+\n+\tif (!nx_fifo_found) {\n+\t\tpr_err(\"NX842 FIFO nodes are missing\\n\");\n+\t\tret = -EINVAL;\n+\t}\n+\n+\treturn ret;\n+}\n+\n static int __init nx842_powernv_probe(struct device_node *dn)\n {\n \tstruct nx842_coproc *coproc;\n@@ -622,6 +930,9 @@ static void nx842_delete_coprocs(void)\n \tstruct nx842_coproc *coproc, *n;\n \n \tlist_for_each_entry_safe(coproc, n, &nx842_coprocs, list) {\n+\t\tif (coproc->vas.rxwin)\n+\t\t\tvas_win_close(coproc->vas.rxwin);\n+\n \t\tlist_del(&coproc->list);\n \t\tkfree(coproc);\n \t}\n@@ -643,6 +954,46 @@ static struct nx842_driver nx842_powernv_driver = {\n \t.decompress =\tnx842_powernv_decompress,\n };\n \n+static int nx842_powernv_crypto_init_vas(struct crypto_tfm *tfm)\n+{\n+\tstruct nx842_crypto_ctx *ctx = crypto_tfm_ctx(tfm);\n+\tstruct nx842_workmem *wmem;\n+\tstruct nx842_coproc *coproc;\n+\tint ret;\n+\n+\tret = nx842_crypto_init(tfm, &nx842_powernv_driver);\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\twmem = PTR_ALIGN((struct nx842_workmem *)ctx->wmem, WORKMEM_ALIGN);\n+\tcoproc = per_cpu(coproc_inst, smp_processor_id());\n+\n+\tret = -EINVAL;\n+\tif (coproc && coproc->vas.rxwin) {\n+\t\twmem->txwin = nx842_alloc_txwin(coproc);\n+\t\tif (!IS_ERR(wmem->txwin))\n+\t\t\treturn 0;\n+\n+\t\tret = PTR_ERR(wmem->txwin);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+void nx842_powernv_crypto_exit_vas(struct crypto_tfm *tfm)\n+{\n+\tstruct nx842_crypto_ctx *ctx = crypto_tfm_ctx(tfm);\n+\tstruct nx842_workmem *wmem;\n+\n+\twmem = PTR_ALIGN((struct nx842_workmem *)ctx->wmem, WORKMEM_ALIGN);\n+\n+\tif (wmem && wmem->txwin)\n+\t\tvas_win_close(wmem->txwin);\n+\n+\tnx842_crypto_exit(tfm);\n+}\n+\n static int nx842_powernv_crypto_init(struct crypto_tfm *tfm)\n {\n \treturn nx842_crypto_init(tfm, &nx842_powernv_driver);\n@@ -676,13 +1027,27 @@ static __init int nx842_powernv_init(void)\n \tBUILD_BUG_ON(DDE_BUFFER_ALIGN % DDE_BUFFER_SIZE_MULT);\n \tBUILD_BUG_ON(DDE_BUFFER_SIZE_MULT % DDE_BUFFER_LAST_MULT);\n \n-\tfor_each_compatible_node(dn, NULL, \"ibm,power-nx\")\n-\t\tnx842_powernv_probe(dn);\n+\tfor_each_compatible_node(dn, NULL, \"ibm,power9-nx\") {\n+\t\tret = nx842_powernv_probe_vas(dn);\n+\t\tif (ret) {\n+\t\t\tnx842_delete_coprocs();\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n \n-\tif (!nx842_ct)\n-\t\treturn -ENODEV;\n+\tif (list_empty(&nx842_coprocs)) {\n+\t\tfor_each_compatible_node(dn, NULL, \"ibm,power-nx\")\n+\t\t\tnx842_powernv_probe(dn);\n+\n+\t\tif (!nx842_ct)\n+\t\t\treturn -ENODEV;\n \n-\tnx842_powernv_exec = nx842_exec_icswx;\n+\t\tnx842_powernv_exec = nx842_exec_icswx;\n+\t} else {\n+\t\tnx842_powernv_exec = nx842_exec_vas;\n+\t\tnx842_powernv_alg.cra_init = nx842_powernv_crypto_init_vas;\n+\t\tnx842_powernv_alg.cra_exit = nx842_powernv_crypto_exit_vas;\n+\t}\n \n \tret = crypto_register_alg(&nx842_powernv_alg);\n \tif (ret) {\n", "prefixes": [ "V4", "7/7" ] }