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GET /api/patches/807978/?format=api
{ "id": 807978, "url": "http://patchwork.ozlabs.org/api/patches/807978/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/20170830233609.13855-2-stefan.bruens@rwth-aachen.de/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170830233609.13855-2-stefan.bruens@rwth-aachen.de>", "list_archive_url": null, "date": "2017-08-30T23:36:07", "name": "[1/3] dmaengine: sun6i: Correct DMA support on H3", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e81ce71116c782a22774b66fd7fd2d0f257e129c", "submitter": { "id": 67055, "url": "http://patchwork.ozlabs.org/api/people/67055/?format=api", "name": "Stefan Brüns", "email": "stefan.bruens@rwth-aachen.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/20170830233609.13855-2-stefan.bruens@rwth-aachen.de/mbox/", "series": [ { "id": 725, "url": "http://patchwork.ozlabs.org/api/series/725/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/list/?series=725", "date": "2017-08-30T23:36:06", "name": "dmaengine: Fix DMA on current allwinner SoCs, add A64 support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/725/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807978/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807978/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"smQm/K1n\"; dkim-atps=neutral" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjMRF5N0kz9s7f\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tThu, 31 Aug 2017 09:39:21 +1000 (AEST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnCZm-0002SH-5S; Wed, 30 Aug 2017 23:39:14 +0000", "from mail-out-1.itc.rwth-aachen.de ([134.130.5.46])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnCXG-0001o0-TA for linux-arm-kernel@lists.infradead.org;\n\tWed, 30 Aug 2017 23:36:41 +0000", "from rwthex-w2-b.rwth-ad.de ([134.130.26.159])\n\tby mail-in-1.itc.rwth-aachen.de with ESMTP; 31 Aug 2017 01:36:18 +0200", "from pebbles.fritz.box (77.182.248.91) by rwthex-w2-b.rwth-ad.de\n\t(2002:8682:1a9f::8682:1a9f) with Microsoft SMTP Server (TLS) id\n\t15.0.1320.4; Thu, 31 Aug 2017 01:36:17 +0200" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=q0AlLy8sIBgY9UyJqYQfxNGR81Z1mXWzjgxDJ2rssyk=;\n\tb=smQm/K1nkamwUk\n\tP7XtOLUtpNFquT35ufS2j4DNVOcu+9+hsX5L+aEx7e/ixOvgwHzIojaWWmzEY9yesqIH1YS3g/gep\n\tJpzn+G8/Mi776dS5P1bzV1v9ZUPwAAz+uyEbMPGMrdNkVpJAV7ie2zR7DZqjIOGKMm5MsfMcX0eRc\n\toTyTG7il5dKRsb/QqCrbobgi4IpS4v27cUtp6VZX9x6yceyLXKbJAkYYHGJHmTGtrv7E51gh7X0RC\n\tu6Kz3+9j1dx7FklqXulYa7YGfOvvAHpA61Go2rnn4Sjx7xnG+yXWWHq037ba9PuaWNEDtlPFMn8Sw\n\t5XOH/tjc9dX3h94waxHw==;", "X-IronPort-AV": "E=Sophos;i=\"5.41,450,1498514400\"; d=\"scan'208\";a=\"11027211\"", "From": "=?utf-8?q?Stefan_Br=C3=BCns?= <stefan.bruens@rwth-aachen.de>", "To": "<linux-sunxi@googlegroups.com>", "Subject": "[PATCH 1/3] dmaengine: sun6i: Correct DMA support on H3", "Date": "Thu, 31 Aug 2017 01:36:07 +0200", "Message-ID": "<20170830233609.13855-2-stefan.bruens@rwth-aachen.de>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170830233609.13855-1-stefan.bruens@rwth-aachen.de>", "References": "<20170830233609.13855-1-stefan.bruens@rwth-aachen.de>", "MIME-Version": "1.0", "X-Originating-IP": "[77.182.248.91]", "X-ClientProxiedBy": "rwthex-w2-a.rwth-ad.de (2002:8682:1a9e::8682:1a9e) To\n\trwthex-w2-b.rwth-ad.de (2002:8682:1a9f::8682:1a9f)", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20170830_163639_468488_B09D56DD ", "X-CRM114-Status": "GOOD ( 15.66 )", "X-Spam-Score": "-4.2 (----)", "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.130.5.46 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Cc": "devicetree@vger.kernel.org, Vinod Koul <vinod.koul@intel.com>,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai <wens@csie.org>,\n\tRob Herring <robh+dt@kernel.org>, dmaengine@vger.kernel.org,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>,\n\tlinux-arm-kernel@lists.infradead.org", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "H3 (and A64/H5) have a sligthly different DMA controller compared with\nolder SoC generations:\n\n- it supports a buswidth of 8 bytes\n- it supports burst length of 4 and 16 transfers\n- the register offset for the burst lengths are different, it uses bits\n [6:7]/[22:23] instead of [7:8]/[23:24] for the src/dest lengths.\n\nSet the src_addr_widths/dest_addr_widths fields in struct dma_device\naccording to the supported widths and use these for verification of the\nslave configuration.\n\nAs struct dma_device has no detailed information for supported burst\nlengths (only maxburst), the information is added to the config.\n\nSeparating verification of the config and conversion to register values\nallows to keep both independent of the used controller.\n\nSigned-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>\n---\n drivers/dma/sun6i-dma.c | 128 +++++++++++++++++++++++++++++++++---------------\n 1 file changed, 88 insertions(+), 40 deletions(-)", "diff": "diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c\nindex a2358780ab2c..5f4eee4513e5 100644\n--- a/drivers/dma/sun6i-dma.c\n+++ b/drivers/dma/sun6i-dma.c\n@@ -48,6 +48,9 @@\n #define SUN8I_DMA_GATE\t\t0x20\n #define SUN8I_DMA_GATE_ENABLE\t0x4\n \n+#define SUNXI_H3_SECURITE_REG\t\t0x20\n+#define SUNXI_H3_DMA_GATE\t\t0x28\n+#define SUNXI_H3_DMA_GATE_ENABLE\t0x4\n /*\n * Channels specific registers\n */\n@@ -65,13 +68,15 @@\n #define DMA_CHAN_CFG_SRC_DRQ(x)\t\t((x) & 0x1f)\n #define DMA_CHAN_CFG_SRC_IO_MODE\tBIT(5)\n #define DMA_CHAN_CFG_SRC_LINEAR_MODE\t(0 << 5)\n-#define DMA_CHAN_CFG_SRC_BURST(x)\t(((x) & 0x3) << 7)\n+#define DMA_CHAN_CFG_SRC_BURST_A31(x)\t(((x) & 0x3) << 7)\n+#define DMA_CHAN_CFG_SRC_BURST_H3(x)\t(((x) & 0x3) << 6)\n #define DMA_CHAN_CFG_SRC_WIDTH(x)\t(((x) & 0x3) << 9)\n \n #define DMA_CHAN_CFG_DST_DRQ(x)\t\t(DMA_CHAN_CFG_SRC_DRQ(x) << 16)\n #define DMA_CHAN_CFG_DST_IO_MODE\t(DMA_CHAN_CFG_SRC_IO_MODE << 16)\n #define DMA_CHAN_CFG_DST_LINEAR_MODE\t(DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)\n-#define DMA_CHAN_CFG_DST_BURST(x)\t(DMA_CHAN_CFG_SRC_BURST(x) << 16)\n+#define DMA_CHAN_CFG_DST_BURST_A31(x)\t(DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)\n+#define DMA_CHAN_CFG_DST_BURST_H3(x)\t(DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)\n #define DMA_CHAN_CFG_DST_WIDTH(x)\t(DMA_CHAN_CFG_SRC_WIDTH(x) << 16)\n \n #define DMA_CHAN_CUR_SRC\t0x10\n@@ -90,6 +95,16 @@\n #define NORMAL_WAIT\t8\n #define DRQ_SDRAM\t1\n \n+/* Between SoC generations, there are some significant differences:\n+ * - A23 added a clock gate register\n+ * - the H3 burst length field has a different offset\n+ */\n+enum dmac_variant {\n+\tDMAC_VARIANT_A31,\n+\tDMAC_VARIANT_A23,\n+\tDMAC_VARIANT_H3,\n+};\n+\n /*\n * Hardware channels / ports representation\n *\n@@ -101,6 +116,7 @@ struct sun6i_dma_config {\n \tu32 nr_max_channels;\n \tu32 nr_max_requests;\n \tu32 nr_max_vchans;\n+\tenum dmac_variant dmac_variant;\n };\n \n /*\n@@ -240,8 +256,12 @@ static inline s8 convert_burst(u32 maxburst)\n \tswitch (maxburst) {\n \tcase 1:\n \t\treturn 0;\n+\tcase 4:\n+\t\treturn 1;\n \tcase 8:\n \t\treturn 2;\n+\tcase 16:\n+\t\treturn 3;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\n@@ -249,11 +269,7 @@ static inline s8 convert_burst(u32 maxburst)\n \n static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)\n {\n-\tif ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||\n-\t (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))\n-\t\treturn -EINVAL;\n-\n-\treturn addr_width >> 1;\n+\treturn ilog2(addr_width);\n }\n \n static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)\n@@ -499,45 +515,58 @@ static int set_config(struct sun6i_dma_dev *sdev,\n \t\t\tenum dma_transfer_direction direction,\n \t\t\tu32 *p_cfg)\n {\n+\tenum dma_slave_buswidth src_addr_width, dst_addr_width;\n+\tu32 src_maxburst, dst_maxburst, supported_burst_length;\n \ts8 src_width, dst_width, src_burst, dst_burst;\n \n+\tsrc_addr_width = sconfig->src_addr_width;\n+\tdst_addr_width = sconfig->dst_addr_width;\n+\tsrc_maxburst = sconfig->src_maxburst;\n+\tdst_maxburst = sconfig->dst_maxburst;\n+\n+\tif (sdev->cfg->dmac_variant == DMAC_VARIANT_H3)\n+\t\tsupported_burst_length = BIT(1) | BIT(4) | BIT(8) | BIT(16);\n+\telse\n+\t\tsupported_burst_length = BIT(1) | BIT(8);\n+\n \tswitch (direction) {\n \tcase DMA_MEM_TO_DEV:\n-\t\tsrc_burst = convert_burst(sconfig->src_maxburst ?\n-\t\t\t\t\tsconfig->src_maxburst : 8);\n-\t\tsrc_width = convert_buswidth(sconfig->src_addr_width !=\n-\t\t\t\t\t\tDMA_SLAVE_BUSWIDTH_UNDEFINED ?\n-\t\t\t\tsconfig->src_addr_width :\n-\t\t\t\tDMA_SLAVE_BUSWIDTH_4_BYTES);\n-\t\tdst_burst = convert_burst(sconfig->dst_maxburst);\n-\t\tdst_width = convert_buswidth(sconfig->dst_addr_width);\n+\t\tif (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)\n+\t\t\tsrc_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\t\tsrc_maxburst = src_maxburst ? src_maxburst : 8;\n \t\tbreak;\n \tcase DMA_DEV_TO_MEM:\n-\t\tsrc_burst = convert_burst(sconfig->src_maxburst);\n-\t\tsrc_width = convert_buswidth(sconfig->src_addr_width);\n-\t\tdst_burst = convert_burst(sconfig->dst_maxburst ?\n-\t\t\t\t\tsconfig->dst_maxburst : 8);\n-\t\tdst_width = convert_buswidth(sconfig->dst_addr_width !=\n-\t\t\t\t\t\tDMA_SLAVE_BUSWIDTH_UNDEFINED ?\n-\t\t\t\tsconfig->dst_addr_width :\n-\t\t\t\tDMA_SLAVE_BUSWIDTH_4_BYTES);\n+\t\tif (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)\n+\t\t\tdst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\t\tdst_maxburst = dst_maxburst ? dst_maxburst : 8;\n \t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\n \n-\tif (src_burst < 0)\n-\t\treturn src_burst;\n-\tif (src_width < 0)\n-\t\treturn src_width;\n-\tif (dst_burst < 0)\n-\t\treturn dst_burst;\n-\tif (dst_width < 0)\n-\t\treturn dst_width;\n-\n-\t*p_cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) |\n-\t\tDMA_CHAN_CFG_SRC_WIDTH(src_width) |\n-\t\tDMA_CHAN_CFG_DST_BURST(dst_burst) |\n+\tif (!(BIT(src_addr_width) & sdev->slave.src_addr_widths))\n+\t\treturn -EINVAL;\n+\tif (!(BIT(dst_addr_width) & sdev->slave.dst_addr_widths))\n+\t\treturn -EINVAL;\n+\tif (!(BIT(src_maxburst) & supported_burst_length))\n+\t\treturn -EINVAL;\n+\tif (!(BIT(dst_maxburst) & supported_burst_length))\n+\t\treturn -EINVAL;\n+\n+\tsrc_width = convert_buswidth(src_addr_width);\n+\tdst_width = convert_buswidth(dst_addr_width);\n+\tdst_burst = convert_burst(dst_maxburst);\n+\tsrc_burst = convert_burst(src_maxburst);\n+\n+\tif (sdev->cfg->dmac_variant == DMAC_VARIANT_H3) {\n+\t\t*p_cfg = DMA_CHAN_CFG_SRC_BURST_H3(src_burst) |\n+\t\t\t DMA_CHAN_CFG_DST_BURST_H3(dst_burst);\n+\t} else {\n+\t\t*p_cfg = DMA_CHAN_CFG_SRC_BURST_A31(src_burst) |\n+\t\t\t DMA_CHAN_CFG_DST_BURST_A31(dst_burst);\n+\t}\n+\n+\t*p_cfg |= DMA_CHAN_CFG_SRC_WIDTH(src_width) |\n \t\tDMA_CHAN_CFG_DST_WIDTH(dst_width);\n \n \treturn 0;\n@@ -582,11 +611,17 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(\n \t\tDMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |\n \t\tDMA_CHAN_CFG_DST_LINEAR_MODE |\n \t\tDMA_CHAN_CFG_SRC_LINEAR_MODE |\n-\t\tDMA_CHAN_CFG_SRC_BURST(burst) |\n \t\tDMA_CHAN_CFG_SRC_WIDTH(width) |\n-\t\tDMA_CHAN_CFG_DST_BURST(burst) |\n \t\tDMA_CHAN_CFG_DST_WIDTH(width);\n \n+\tif (sdev->cfg->dmac_variant == DMAC_VARIANT_H3) {\n+\t\tv_lli->cfg |= DMA_CHAN_CFG_SRC_BURST_H3(burst) |\n+\t\t\t DMA_CHAN_CFG_DST_BURST_H3(burst);\n+\t} else {\n+\t\tv_lli->cfg |= DMA_CHAN_CFG_SRC_BURST_A31(burst) |\n+\t\t\t DMA_CHAN_CFG_DST_BURST_A31(burst);\n+\t}\n+\n \tsun6i_dma_lli_add(NULL, v_lli, p_lli, txd);\n \n \tsun6i_dma_dump_lli(vchan, v_lli);\n@@ -998,6 +1033,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = {\n \t.nr_max_channels = 16,\n \t.nr_max_requests = 30,\n \t.nr_max_vchans = 53,\n+\t.dmac_variant = DMAC_VARIANT_A31,\n };\n \n /*\n@@ -1009,23 +1045,29 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = {\n \t.nr_max_channels = 8,\n \t.nr_max_requests = 24,\n \t.nr_max_vchans = 37,\n+\t.dmac_variant = DMAC_VARIANT_A23,\n };\n \n static struct sun6i_dma_config sun8i_a83t_dma_cfg = {\n \t.nr_max_channels = 8,\n \t.nr_max_requests = 28,\n \t.nr_max_vchans = 39,\n+\t.dmac_variant = DMAC_VARIANT_A23,\n };\n \n /*\n * The H3 has 12 physical channels, a maximum DRQ port id of 27,\n * and a total of 34 usable source and destination endpoints.\n+ * It also supports additional burst lengths and bus widths,\n+ * and the burst length fields have different offsets.\n */\n \n static struct sun6i_dma_config sun8i_h3_dma_cfg = {\n \t.nr_max_channels = 12,\n \t.nr_max_requests = 27,\n \t.nr_max_vchans = 34,\n+\t.dmac_variant = DMAC_VARIANT_H3,\n+};\n };\n \n static const struct of_device_id sun6i_dma_match[] = {\n@@ -1110,6 +1152,10 @@ static int sun6i_dma_probe(struct platform_device *pdev)\n \tsdc->slave.dst_addr_widths\t\t= BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\n \t\t\t\t\t\t BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\n \t\t\t\t\t\t BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);\n+\tif (sdc->cfg->dmac_variant == DMAC_VARIANT_H3) {\n+\t\tsdc->slave.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);\n+\t\tsdc->slave.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);\n+\t}\n \tsdc->slave.directions\t\t\t= BIT(DMA_DEV_TO_MEM) |\n \t\t\t\t\t\t BIT(DMA_MEM_TO_DEV);\n \tsdc->slave.residue_granularity\t\t= DMA_RESIDUE_GRANULARITY_BURST;\n@@ -1177,10 +1223,12 @@ static int sun6i_dma_probe(struct platform_device *pdev)\n \t/*\n \t * sun8i variant requires us to toggle a dma gating register,\n \t * as seen in Allwinner's SDK. This register is not documented\n-\t * in the A23 user manual.\n+\t * in the A23 user manual, but appears in e.g. the H83T manual.\n+\t * For the H3, H5 and A64, the register has a different location\n \t */\n-\tif (of_device_is_compatible(pdev->dev.of_node,\n-\t\t\t\t \"allwinner,sun8i-a23-dma\"))\n+\tif (sdc->cfg->dmac_variant == DMAC_VARIANT_H3)\n+\t\twritel(SUNXI_H3_DMA_GATE_ENABLE, sdc->base + SUNXI_H3_DMA_GATE);\n+\telse if (sdc->cfg->dmac_variant == DMAC_VARIANT_A23)\n \t\twritel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE);\n \n \treturn 0;\n", "prefixes": [ "1/3" ] }