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GET /api/patches/807963/?format=api
{ "id": 807963, "url": "http://patchwork.ozlabs.org/api/patches/807963/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170830225225.27925-6-f4bug@amsat.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170830225225.27925-6-f4bug@amsat.org>", "list_archive_url": null, "date": "2017-08-30T22:52:23", "name": "[v2,5/7] mips: MIPSCPU model subclasses", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "208b2b9ee97fc412ae16d07218d63b738f2e25c5", "submitter": { "id": 70924, "url": "http://patchwork.ozlabs.org/api/people/70924/?format=api", "name": "Philippe Mathieu-Daudé", "email": "f4bug@amsat.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170830225225.27925-6-f4bug@amsat.org/mbox/", "series": [ { "id": 718, "url": "http://patchwork.ozlabs.org/api/series/718/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=718", "date": "2017-08-30T22:52:19", "name": "[v2,1/7] mips: move hw/mips/cputimer.c to target/mips/", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/718/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807963/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807963/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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<philippe.mathieu.daude@gmail.com>)\n\tid 1dnBr0-0003VA-51\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 18:52:59 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dnBqy-0002Gh-LE\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 18:52:58 -0400", "from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:35788)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dnBqy-0002GW-Fc\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 18:52:56 -0400", "by mail-qt0-x241.google.com with SMTP id u11so6363254qtu.2\n\tfor <qemu-devel@nongnu.org>; Wed, 30 Aug 2017 15:52:56 -0700 (PDT)", "from yoga.offpageads.com ([181.93.89.178])\n\tby smtp.gmail.com with ESMTPSA id\n\t54sm4449874qts.31.2017.08.30.15.52.52\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 30 Aug 2017 15:52:55 -0700 (PDT)" ], "DKIM-Signature": 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s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references:mime-version:content-transfer-encoding;\n\tbh=yi+pjInDxGAOIHNZmFO102gPGjOYyRgoxki9IDvo6Fc=;\n\tb=ZP5E9UfNpEtKKKqTB4xmH2EMQuDYsvWgDiA2NQrQknjIc+oUQbTQwHpcYNSMHrkq7N\n\tmDrpP8jlfkm31ujl5aQR5Xj6VTIs0l8JnnRptPQ3W+tY/Kv3ryoNLu5lMvcJraK89GiK\n\t8TaXv3aMd1uRkZfeUQcUKh1Mk4+NCkW31CseOB76vUcLc2wj3n2UovFAQqpXPKh5pfBu\n\toLC74UN/aYo5Vuvl2x6AaVDn3bUJzlKi0YDDMVnQXFFZ9KPKCZabmD85xcqudIr2kQ6N\n\tCSLgG7LDc/M8EjHcjWPKf2eNlhYMCAyNV9PqW3NaCP+cwGCtAoiEFJohZ+K/ScpnbJ/E\n\txe1w==", "X-Gm-Message-State": "AHYfb5hcY/kL55MBgVrjiG80ibU14il+UNj29UYzsAsY8s3Udv37CKU4\n\t1SkdRHvkDfdN9g==", "X-Received": "by 10.200.44.106 with SMTP id e39mr4299646qta.140.1504133575855; \n\tWed, 30 Aug 2017 15:52:55 -0700 (PDT)", "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>", "To": "Igor Mammedov <imammedo@redhat.com>, =?utf-8?q?Herv=C3=A9_Poussineau?=\n\t<hpoussin@reactos.org>, \tAurelien Jarno <aurelien@aurel32.net>,\n\tEduardo Habkost <ehabkost@redhat.com>, \n\tMarcel Apfelbaum <marcel@redhat.com>,\n\tJames Hogan <james.hogan@imgtec.com>, Yongbok Kim\n\t<yongbok.kim@imgtec.com>", "Date": "Wed, 30 Aug 2017 19:52:23 -0300", "Message-Id": "<20170830225225.27925-6-f4bug@amsat.org>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170830225225.27925-1-f4bug@amsat.org>", "References": "<20170830225225.27925-1-f4bug@amsat.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400d:c0d::241", "Subject": "[Qemu-devel] [PATCH v2 5/7] mips: MIPSCPU model subclasses", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Thomas Huth <thuth@redhat.com>, qemu-devel@nongnu.org, =?utf-8?q?Phili?=\n\t=?utf-8?q?ppe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Igor Mammedov <imammedo@redhat.com>\n\nRegister separate QOM types for each mips cpu model,\nso it would be possible to reuse generic CPU creation\nroutines.\n\nSigned-off-by: Igor Mammedov <imammedo@redhat.com>\nSigned-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\n[PMD: use internal.h, use void* to hold cpu_def in MIPSCPUClass,\n mark MIPSCPU abstract]\nTested-by: James Hogan <james.hogan@imgtec.com>\n---\n target/mips/cpu-qom.h | 1 +\n target/mips/internal.h | 59 ++++++++++++++++++++++++++++++++++++++++++++\n target/mips/cpu.c | 53 ++++++++++++++++++++++++++++++++++++++-\n target/mips/translate.c | 13 +++++-----\n target/mips/translate_init.c | 58 ++-----------------------------------------\n 5 files changed, 120 insertions(+), 64 deletions(-)", "diff": "diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h\nindex 3f5bf23823..085711d8f9 100644\n--- a/target/mips/cpu-qom.h\n+++ b/target/mips/cpu-qom.h\n@@ -49,6 +49,7 @@ typedef struct MIPSCPUClass {\n \n DeviceRealize parent_realize;\n void (*parent_reset)(CPUState *cpu);\n+ const void *cpu_def;\n } MIPSCPUClass;\n \n typedef struct MIPSCPU MIPSCPU;\ndiff --git a/target/mips/internal.h b/target/mips/internal.h\nindex cf4c9db427..45ded3484c 100644\n--- a/target/mips/internal.h\n+++ b/target/mips/internal.h\n@@ -7,6 +7,65 @@\n #ifndef MIPS_INTERNAL_H\n #define MIPS_INTERNAL_H\n \n+\n+/* MMU types, the first four entries have the same layout as the\n+ CP0C0_MT field. */\n+enum mips_mmu_types {\n+ MMU_TYPE_NONE,\n+ MMU_TYPE_R4000,\n+ MMU_TYPE_RESERVED,\n+ MMU_TYPE_FMT,\n+ MMU_TYPE_R3000,\n+ MMU_TYPE_R6000,\n+ MMU_TYPE_R8000\n+};\n+\n+struct mips_def_t {\n+ const char *name;\n+ int32_t CP0_PRid;\n+ int32_t CP0_Config0;\n+ int32_t CP0_Config1;\n+ int32_t CP0_Config2;\n+ int32_t CP0_Config3;\n+ int32_t CP0_Config4;\n+ int32_t CP0_Config4_rw_bitmask;\n+ int32_t CP0_Config5;\n+ int32_t CP0_Config5_rw_bitmask;\n+ int32_t CP0_Config6;\n+ int32_t CP0_Config7;\n+ target_ulong CP0_LLAddr_rw_bitmask;\n+ int CP0_LLAddr_shift;\n+ int32_t SYNCI_Step;\n+ int32_t CCRes;\n+ int32_t CP0_Status_rw_bitmask;\n+ int32_t CP0_TCStatus_rw_bitmask;\n+ int32_t CP0_SRSCtl;\n+ int32_t CP1_fcr0;\n+ int32_t CP1_fcr31_rw_bitmask;\n+ int32_t CP1_fcr31;\n+ int32_t MSAIR;\n+ int32_t SEGBITS;\n+ int32_t PABITS;\n+ int32_t CP0_SRSConf0_rw_bitmask;\n+ int32_t CP0_SRSConf0;\n+ int32_t CP0_SRSConf1_rw_bitmask;\n+ int32_t CP0_SRSConf1;\n+ int32_t CP0_SRSConf2_rw_bitmask;\n+ int32_t CP0_SRSConf2;\n+ int32_t CP0_SRSConf3_rw_bitmask;\n+ int32_t CP0_SRSConf3;\n+ int32_t CP0_SRSConf4_rw_bitmask;\n+ int32_t CP0_SRSConf4;\n+ int32_t CP0_PageGrain_rw_bitmask;\n+ int32_t CP0_PageGrain;\n+ target_ulong CP0_EBaseWG_rw_bitmask;\n+ int insn_flags;\n+ enum mips_mmu_types mmu_type;\n+};\n+\n+extern const struct mips_def_t mips_defs[];\n+extern const int mips_defs_number;\n+\n enum CPUMIPSMSADataFormat {\n DF_BYTE = 0,\n DF_HALF,\ndiff --git a/target/mips/cpu.c b/target/mips/cpu.c\nindex e3ef835599..84b6f8bf68 100644\n--- a/target/mips/cpu.c\n+++ b/target/mips/cpu.c\n@@ -146,12 +146,37 @@ static void mips_cpu_initfn(Object *obj)\n CPUState *cs = CPU(obj);\n MIPSCPU *cpu = MIPS_CPU(obj);\n CPUMIPSState *env = &cpu->env;\n+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);\n \n cs->env_ptr = env;\n \n if (tcg_enabled()) {\n mips_tcg_init();\n }\n+\n+ if (mcc->cpu_def) {\n+ env->cpu_model = mcc->cpu_def;\n+ }\n+}\n+\n+static char *mips_cpu_type_name(const char *cpu_model)\n+{\n+ return g_strdup_printf(\"%s-\" TYPE_MIPS_CPU, cpu_model);\n+}\n+\n+static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)\n+{\n+ ObjectClass *oc;\n+ char *typename;\n+\n+ if (cpu_model == NULL) {\n+ return NULL;\n+ }\n+\n+ typename = mips_cpu_type_name(cpu_model);\n+ oc = object_class_by_name(typename);\n+ g_free(typename);\n+ return oc;\n }\n \n static void mips_cpu_class_init(ObjectClass *c, void *data)\n@@ -166,6 +191,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)\n mcc->parent_reset = cc->reset;\n cc->reset = mips_cpu_reset;\n \n+ cc->class_by_name = mips_cpu_class_by_name;\n cc->has_work = mips_cpu_has_work;\n cc->do_interrupt = mips_cpu_do_interrupt;\n cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;\n@@ -193,14 +219,39 @@ static const TypeInfo mips_cpu_type_info = {\n .parent = TYPE_CPU,\n .instance_size = sizeof(MIPSCPU),\n .instance_init = mips_cpu_initfn,\n- .abstract = false,\n+ .abstract = true,\n .class_size = sizeof(MIPSCPUClass),\n .class_init = mips_cpu_class_init,\n };\n \n+static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)\n+{\n+ MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);\n+ mcc->cpu_def = data;\n+}\n+\n+static void mips_register_cpudef_type(const struct mips_def_t *def)\n+{\n+ char *typename = mips_cpu_type_name(def->name);\n+ TypeInfo ti = {\n+ .name = typename,\n+ .parent = TYPE_MIPS_CPU,\n+ .class_init = mips_cpu_cpudef_class_init,\n+ .class_data = (void *)def,\n+ };\n+\n+ type_register(&ti);\n+ g_free(typename);\n+}\n+\n static void mips_cpu_register_types(void)\n {\n+ int i;\n+\n type_register_static(&mips_cpu_type_info);\n+ for (i = 0; i < mips_defs_number; i++) {\n+ mips_register_cpudef_type(&mips_defs[i]);\n+ }\n }\n \n type_init(mips_cpu_register_types)\ndiff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 94c38e8755..f7128bc91d 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -20525,16 +20525,15 @@ void cpu_mips_realize_env(CPUMIPSState *env)\n \n MIPSCPU *cpu_mips_init(const char *cpu_model)\n {\n+ ObjectClass *oc;\n MIPSCPU *cpu;\n- CPUMIPSState *env;\n- const mips_def_t *def;\n \n- def = cpu_mips_find_by_name(cpu_model);\n- if (!def)\n+ oc = cpu_class_by_name(TYPE_MIPS_CPU, cpu_model);\n+ if (oc == NULL) {\n return NULL;\n- cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));\n- env = &cpu->env;\n- env->cpu_model = def;\n+ }\n+\n+ cpu = MIPS_CPU(object_new(object_class_get_name(oc)));\n \n object_property_set_bool(OBJECT(cpu), true, \"realized\", NULL);\n \ndiff --git a/target/mips/translate_init.c b/target/mips/translate_init.c\nindex 255d25bacd..8bbded46c4 100644\n--- a/target/mips/translate_init.c\n+++ b/target/mips/translate_init.c\n@@ -51,64 +51,9 @@\n #define MIPS_CONFIG5 \\\n ((0 << CP0C5_M))\n \n-/* MMU types, the first four entries have the same layout as the\n- CP0C0_MT field. */\n-enum mips_mmu_types {\n- MMU_TYPE_NONE,\n- MMU_TYPE_R4000,\n- MMU_TYPE_RESERVED,\n- MMU_TYPE_FMT,\n- MMU_TYPE_R3000,\n- MMU_TYPE_R6000,\n- MMU_TYPE_R8000\n-};\n-\n-struct mips_def_t {\n- const char *name;\n- int32_t CP0_PRid;\n- int32_t CP0_Config0;\n- int32_t CP0_Config1;\n- int32_t CP0_Config2;\n- int32_t CP0_Config3;\n- int32_t CP0_Config4;\n- int32_t CP0_Config4_rw_bitmask;\n- int32_t CP0_Config5;\n- int32_t CP0_Config5_rw_bitmask;\n- int32_t CP0_Config6;\n- int32_t CP0_Config7;\n- target_ulong CP0_LLAddr_rw_bitmask;\n- int CP0_LLAddr_shift;\n- int32_t SYNCI_Step;\n- int32_t CCRes;\n- int32_t CP0_Status_rw_bitmask;\n- int32_t CP0_TCStatus_rw_bitmask;\n- int32_t CP0_SRSCtl;\n- int32_t CP1_fcr0;\n- int32_t CP1_fcr31_rw_bitmask;\n- int32_t CP1_fcr31;\n- int32_t MSAIR;\n- int32_t SEGBITS;\n- int32_t PABITS;\n- int32_t CP0_SRSConf0_rw_bitmask;\n- int32_t CP0_SRSConf0;\n- int32_t CP0_SRSConf1_rw_bitmask;\n- int32_t CP0_SRSConf1;\n- int32_t CP0_SRSConf2_rw_bitmask;\n- int32_t CP0_SRSConf2;\n- int32_t CP0_SRSConf3_rw_bitmask;\n- int32_t CP0_SRSConf3;\n- int32_t CP0_SRSConf4_rw_bitmask;\n- int32_t CP0_SRSConf4;\n- int32_t CP0_PageGrain_rw_bitmask;\n- int32_t CP0_PageGrain;\n- target_ulong CP0_EBaseWG_rw_bitmask;\n- int insn_flags;\n- enum mips_mmu_types mmu_type;\n-};\n-\n /*****************************************************************************/\n /* MIPS CPU definitions */\n-static const mips_def_t mips_defs[] =\n+const mips_def_t mips_defs[] =\n {\n {\n .name = \"4Kc\",\n@@ -808,6 +753,7 @@ static const mips_def_t mips_defs[] =\n \n #endif\n };\n+const int mips_defs_number = ARRAY_SIZE(mips_defs);\n \n static const mips_def_t *cpu_mips_find_by_name (const char *name)\n {\n", "prefixes": [ "v2", "5/7" ] }