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GET /api/patches/807923/?format=api
{ "id": 807923, "url": "http://patchwork.ozlabs.org/api/patches/807923/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/538699c64b5601e8800b77da29f7951bf23f57ce.1504129273.git.shorne@gmail.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<538699c64b5601e8800b77da29f7951bf23f57ce.1504129273.git.shorne@gmail.com>", "list_archive_url": null, "date": "2017-08-30T21:58:36", "name": "[05/13] irqchip: add initial support for ompic", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "157ae3cc512c0e8c55c89d9940e8b1cd9c1f25b5", "submitter": { "id": 68420, "url": "http://patchwork.ozlabs.org/api/people/68420/?format=api", "name": "Stafford Horne", "email": "shorne@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/538699c64b5601e8800b77da29f7951bf23f57ce.1504129273.git.shorne@gmail.com/mbox/", "series": [ { "id": 705, "url": "http://patchwork.ozlabs.org/api/series/705/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=705", "date": "2017-08-30T21:58:36", "name": null, "version": 1, "mbox": "http://patchwork.ozlabs.org/series/705/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807923/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807923/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"eCAuywIo\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjKFn5F8qz9sN5\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 31 Aug 2017 08:01:01 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751566AbdH3WAs (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tWed, 30 Aug 2017 18:00:48 -0400", "from mail-pf0-f195.google.com ([209.85.192.195]:35022 \"EHLO\n\tmail-pf0-f195.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751559AbdH3WAp (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Wed, 30 Aug 2017 18:00:45 -0400", "by mail-pf0-f195.google.com with SMTP id g13so5077350pfm.2;\n\tWed, 30 Aug 2017 15:00:45 -0700 (PDT)", "from localhost (g71.58-98-164.ppp.wakwak.ne.jp. [58.98.164.71])\n\tby smtp.gmail.com with ESMTPSA id\n\to75sm11418679pfa.87.2017.08.30.15.00.43\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 30 Aug 2017 15:00:44 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:in-reply-to:references;\n\tbh=iogKYzv1S8K7ae+2ja9bvMvDEmjQu0VJksvk016ViYA=;\n\tb=eCAuywIoVJ51pYIYZh1xJ4D6JvaN6RTvVanCMpoAOxmru4FDFle2ZAv52JAOUgCTs2\n\tepvstOZXKTIqY3TqGiPPQhyKXSbT+ZuBX4yEr0anSrjPAMAAR6qDuWvwm8KWgX6/MaZy\n\t+HMtSX2j51SXvirpw5jjPeTRzmwQosBlklhpkpIgy1fP0Q/ySrEcB6q6TWfN+czsZwfi\n\tFdwMn+AvInpu64GaHxQ9EdzvaHvzAN//BubfOziMxJA/u+o5Q1nESdP2iFxfFsBS0Dwz\n\tx/YFdoiFXkf6XYHe9L/sB917ajyZUW07lViYxJyoWsvjF8cQgI+FcX+ExEEImI93xM/7\n\th+8g==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:in-reply-to:references;\n\tbh=iogKYzv1S8K7ae+2ja9bvMvDEmjQu0VJksvk016ViYA=;\n\tb=jCk9dfqv28MxMb6p443pHeOGlrAcnYKl6rJRmVOdMPb/r/lTPZdtOeEebO52xdxdEE\n\tOeTL186vz8c5XIbw5yI0eeoqCHotBAEJmCtq8UffL2W3EJokKG6E8MLUczEulu3Dur84\n\tQ2sgeyk3SHEOYTKPUsHg3KaxaXA04n8SGLDlbuofqIS4djCZwceT0S7ZSasdJM4JmLM7\n\tyyJ63nIFuNTRZLfqgLhA74jVRmgwox8aTQZ/USu/rD7QBKBi7cusc0XrCN9YlOW8zKZN\n\tSpe/j6/VgMBvtIHGDRdIaibHEGhSZM8wlWfKR1/0e0sWQyCewEYDSLzPG1iXlopOJt/F\n\tzggg==", "X-Gm-Message-State": "AHYfb5hZKhcQ0OvCyASrBCe7TZRJxlF3Ruu+xgXNCCcs5E/2lBNYQbpu\n\teSN5b7b3oFCacs91JPV1Rg==", "X-Received": "by 10.84.217.201 with SMTP id d9mr37358plj.125.1504130445007;\n\tWed, 30 Aug 2017 15:00:45 -0700 (PDT)", "From": "Stafford Horne <shorne@gmail.com>", "To": "LKML <linux-kernel@vger.kernel.org>", "Cc": "Openrisc <openrisc@lists.librecores.org>,\n\tStefan Kristiansson <stefan.kristiansson@saunalahti.fi>,\n\tStafford Horne <shorne@gmail.com>, Thomas Gleixner <tglx@linutronix.de>, \n\tJason Cooper <jason@lakedaemon.net>,\n\tMarc Zyngier <marc.zyngier@arm.com>, \n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,\n\tJonas Bonn <jonas@southpole.se>, devicetree@vger.kernel.org", "Subject": "[PATCH 05/13] irqchip: add initial support for ompic", "Date": "Thu, 31 Aug 2017 06:58:36 +0900", "Message-Id": "<538699c64b5601e8800b77da29f7951bf23f57ce.1504129273.git.shorne@gmail.com>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": [ "<cover.1504129273.git.shorne@gmail.com>", "<cover.1504129273.git.shorne@gmail.com>" ], "References": [ "<cover.1504129273.git.shorne@gmail.com>", "<cover.1504129273.git.shorne@gmail.com>" ], "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\n\nIPI driver for OpenRISC Multicore programmable interrupt controller as\ndescribed in the Multicore support section of the OpenRISC 1.2\nproposed architecture specification:\n\n https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf\n\nEach OpenRISC core contains a full interrupt controller which is used in\nthe SMP architecture for interrupt balancing. This IPI device is the\nonly external device required for enabling SMP on OpenRISC.\n\nPending ops are stored in a memory bit mask which can allow multiple\npending operations to be set and serviced at a time. This is mostly\nborrowed from the alpha IPI implementation.\n\nSigned-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\n[shorne@gmail.com: converted ops to bitmask, wrote commit message]\nSigned-off-by: Stafford Horne <shorne@gmail.com>\n---\n .../bindings/interrupt-controller/ompic.txt | 22 ++++\n arch/openrisc/Kconfig | 1 +\n drivers/irqchip/Kconfig | 4 +\n drivers/irqchip/Makefile | 1 +\n drivers/irqchip/irq-ompic.c | 117 +++++++++++++++++++++\n 5 files changed, 145 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ompic.txt\n create mode 100644 drivers/irqchip/irq-ompic.c", "diff": "diff --git a/Documentation/devicetree/bindings/interrupt-controller/ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt\nnew file mode 100644\nindex 000000000000..4176ecc3366d\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt\n@@ -0,0 +1,22 @@\n+OpenRISC Multicore Programmable Interrupt Controller\n+\n+Required properties:\n+\n+- compatible : This should be \"ompic\"\n+- reg : Specifies base physical address and size of the register space. The\n+ size can be arbitrary based on the number of cores the controller has\n+ been configured to handle, typically 8 bytes per core.\n+- interrupt-controller : Identifies the node as an interrupt controller\n+- #interrupt-cells : Specifies the number of cells needed to encode an\n+ interrupt source. The value shall be 1.\n+- interrupts : Specifies the interrupt line to which the ompic is wired.\n+\n+Example:\n+\n+ompic: ompic {\n+\tcompatible = \"ompic\";\n+\treg = <0x98000000 16>;\n+\t#interrupt-cells = <1>;\n+\tinterrupt-controller;\n+\tinterrupts = <1>;\n+};\ndiff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig\nindex 214c837ce597..dd7e55e7e42d 100644\n--- a/arch/openrisc/Kconfig\n+++ b/arch/openrisc/Kconfig\n@@ -30,6 +30,7 @@ config OPENRISC\n \tselect NO_BOOTMEM\n \tselect ARCH_USE_QUEUED_SPINLOCKS\n \tselect ARCH_USE_QUEUED_RWLOCKS\n+\tselect OMPIC if SMP\n \n config CPU_BIG_ENDIAN\n \tdef_bool y\ndiff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig\nindex f1fd5f44d1d4..3fa60e6667a7 100644\n--- a/drivers/irqchip/Kconfig\n+++ b/drivers/irqchip/Kconfig\n@@ -145,6 +145,10 @@ config CLPS711X_IRQCHIP\n \tselect SPARSE_IRQ\n \tdefault y\n \n+config OMPIC\n+\tbool\n+\tselect IRQ_DOMAIN\n+\n config OR1K_PIC\n \tbool\n \tselect IRQ_DOMAIN\ndiff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile\nindex e88d856cc09c..123047d7a20d 100644\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL)\t\t+= irq-dw-apb-ictl.o\n obj-$(CONFIG_METAG)\t\t\t+= irq-metag-ext.o\n obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)\t+= irq-metag.o\n obj-$(CONFIG_CLPS711X_IRQCHIP)\t\t+= irq-clps711x.o\n+obj-$(CONFIG_OMPIC)\t\t\t+= irq-ompic.o\n obj-$(CONFIG_OR1K_PIC)\t\t\t+= irq-or1k-pic.o\n obj-$(CONFIG_ORION_IRQCHIP)\t\t+= irq-orion.o\n obj-$(CONFIG_OMAP_IRQCHIP)\t\t+= irq-omap-intc.o\ndiff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c\nnew file mode 100644\nindex 000000000000..438819f8a5a7\n--- /dev/null\n+++ b/drivers/irqchip/irq-ompic.c\n@@ -0,0 +1,117 @@\n+/*\n+ * Open Multi-Processor Interrupt Controller driver\n+ *\n+ * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\n+ *\n+ * This file is licensed under the terms of the GNU General Public License\n+ * version 2. This program is licensed \"as is\" without any warranty of any\n+ * kind, whether express or implied.\n+ */\n+\n+#include <linux/io.h>\n+#include <linux/interrupt.h>\n+#include <linux/smp.h>\n+#include <linux/of.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_address.h>\n+#include <linux/irqchip/chained_irq.h>\n+#include <linux/delay.h>\n+\n+#include <linux/irqchip.h>\n+\n+#define OMPIC_IPI_BASE\t\t\t0x0\n+#define OMPIC_IPI_CTRL(cpu)\t\t(OMPIC_IPI_BASE + 0x0 + (cpu)*8)\n+#define OMPIC_IPI_STAT(cpu)\t\t(OMPIC_IPI_BASE + 0x4 + (cpu)*8)\n+\n+#define OMPIC_IPI_CTRL_IRQ_ACK\t\t(1 << 31)\n+#define OMPIC_IPI_CTRL_IRQ_GEN\t\t(1 << 30)\n+#define OMPIC_IPI_CTRL_DST(cpu)\t\t(((cpu) & 0x3fff) << 16)\n+\n+#define OMPIC_IPI_STAT_IRQ_PENDING\t(1 << 30)\n+\n+#define OMPIC_IPI_DATA(x)\t\t((x) & 0xffff)\n+\n+static struct {\n+\tunsigned long ops;\n+} ipi_data[NR_CPUS];\n+\n+static void __iomem *ompic_base;\n+\n+static inline u32 ompic_readreg(void __iomem *base, loff_t offset)\n+{\n+\treturn ioread32be(base + offset);\n+}\n+\n+static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)\n+{\n+\tiowrite32be(data, base + offset);\n+}\n+\n+#ifdef CONFIG_SMP\n+void ompic_raise_softirq(const struct cpumask *mask, unsigned int irq)\n+{\n+\tunsigned int dst_cpu;\n+\tunsigned int src_cpu = smp_processor_id();\n+\n+\tfor_each_cpu(dst_cpu, mask) {\n+\t\tset_bit(irq, &ipi_data[dst_cpu].ops);\n+\n+\t\tompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu),\n+\t\t\t OMPIC_IPI_CTRL_IRQ_GEN |\n+\t\t\t OMPIC_IPI_CTRL_DST(dst_cpu) |\n+\t\t\t OMPIC_IPI_DATA(1));\n+\t}\n+}\n+#endif\n+\n+irqreturn_t ompic_ipi_handler(int irq, void *dev_id)\n+{\n+\tunsigned int cpu = smp_processor_id();\n+\tunsigned long *pending_ops = &ipi_data[cpu].ops;\n+\tunsigned long ops;\n+\n+\tompic_writereg(ompic_base, OMPIC_IPI_CTRL(cpu), OMPIC_IPI_CTRL_IRQ_ACK);\n+\twhile ((ops = xchg(pending_ops, 0)) != 0) {\n+\t\tdo {\n+\t\t\tunsigned long ipi;\n+\n+\t\t\tipi = ops & -ops;\n+\t\t\tops &= ~ipi;\n+\t\t\tipi = __ffs(ipi);\n+\n+\t\t\thandle_IPI(ipi);\n+\t\t} while (ops);\n+\t}\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static struct irqaction ompi_ipi_irqaction = {\n+\t.handler = ompic_ipi_handler,\n+\t.flags = IRQF_PERCPU,\n+\t.name = \"ompic_ipi\",\n+};\n+\n+#ifdef CONFIG_OF\n+int __init ompic_of_init(struct device_node *node, struct device_node *parent)\n+{\n+\tint irq;\n+\n+\tif (WARN_ON(!node))\n+\t\treturn -ENODEV;\n+\n+\tmemset(ipi_data, 0, sizeof(ipi_data));\n+\n+\tompic_base = of_iomap(node, 0);\n+\n+\tirq = irq_of_parse_and_map(node, 0);\n+\tsetup_irq(irq, &ompi_ipi_irqaction);\n+\n+#ifdef CONFIG_SMP\n+\tset_smp_cross_call(ompic_raise_softirq);\n+#endif\n+\n+\treturn 0;\n+}\n+IRQCHIP_DECLARE(ompic, \"ompic\", ompic_of_init);\n+#endif\n", "prefixes": [ "05/13" ] }