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GET /api/patches/807714/?format=api
{ "id": 807714, "url": "http://patchwork.ozlabs.org/api/patches/807714/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170830083135.9183-2-tuomas.tynkkynen@iki.fi/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170830083135.9183-2-tuomas.tynkkynen@iki.fi>", "list_archive_url": null, "date": "2017-08-30T08:31:34", "name": "[U-Boot,1/2] PCI: Add driver for a 'pci-host-ecam-generic' host controller", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "b6f15470ac383d91c89ccab5343b674bf3fb9c91", "submitter": { "id": 32296, "url": "http://patchwork.ozlabs.org/api/people/32296/?format=api", "name": "Tuomas Tynkkynen", "email": "tuomas.tynkkynen@iki.fi" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170830083135.9183-2-tuomas.tynkkynen@iki.fi/mbox/", "series": [ { "id": 650, "url": "http://patchwork.ozlabs.org/api/series/650/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=650", "date": "2017-08-30T08:31:33", "name": "Board for QEMU's '-machine virt' on ARM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/650/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807714/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807714/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"iIzLqsjo\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjBG22G3lz9sNn\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 31 Aug 2017 02:45:46 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 08799C22279; Wed, 30 Aug 2017 16:44:44 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id F14BEC21F33;\n\tWed, 30 Aug 2017 16:44:21 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid BD09EC21E16; Wed, 30 Aug 2017 08:32:08 +0000 (UTC)", "from mail-lf0-f68.google.com (mail-lf0-f68.google.com\n\t[209.85.215.68])\n\tby lists.denx.de (Postfix) with ESMTPS id 14F1CC21E11\n\tfor <u-boot@lists.denx.de>; Wed, 30 Aug 2017 08:32:08 +0000 (UTC)", "by mail-lf0-f68.google.com with SMTP id l140so3474460lfg.3\n\tfor <u-boot@lists.denx.de>; Wed, 30 Aug 2017 01:32:08 -0700 (PDT)", "from duuni.srv.tuxera.com ([194.100.106.190])\n\tby smtp.gmail.com with ESMTPSA id\n\t10sm991637ljn.38.2017.08.30.01.32.06\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 30 Aug 2017 01:32:06 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tRCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=cEVypkrzGEOkbHc7EzzluBXC1TlzIu80YBiwK53bZoc=;\n\tb=iIzLqsjo5Vq9NCDkgnQYoR01QvPAwgXye8JsNsA10LNMKsUe/ll/UxrQI0Oqh7t0gv\n\tKupSmKp7kLuW6dso5h9EYh0Zqd6zK8c/P6pZqs+2TyPfeyrX43Rb/Nj24+ZU55FnCtZO\n\tiIQp470lDfaHn2aHCt1OkL6BjiFODL67+/9nplQxehT/1USioas7Zwmhoiq/mZ7FpR4a\n\t/riP6C+Nb/SaJ9ToDzCJkL3lNOngZ9EeYJ/tbhIRVASRJowQMm6TbtllSAuzs8B3Nb1U\n\tUWzSibsV9+SAf4XDiuEXYNzuM5ZpqfH8cpbFSfYUyG9oE3zSB7jI1pGNbMNm6R6FFDhH\n\tcMkw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references;\n\tbh=cEVypkrzGEOkbHc7EzzluBXC1TlzIu80YBiwK53bZoc=;\n\tb=WQkJyScB/qhRzoXzF7bjuYOwULjhSEIFLRzr3VfxwdFm0Kyhz40yQgSgrL2m/ZENxs\n\tRJosvL1yha1RHwzpfSvxqKcIr2Ngw1L5A3BwXYtOXyi4YIpuA1kMWOHQP88lm51Ehf23\n\tDhWX1dTh9FgDXd0plHAYAcZuXfz/hY4RzkQTSh3LMMdT+DtBUKVv4lAVcBH0wBDqThA+\n\t9Tr4ekpF7ONHQOmHQknhYXFtSoWNHm1+VIUmR0jzP4nIMQ1kXi1fEEhiYKfg7iY1zTD5\n\tQCrYfhn76lDo+GP0doP3mgMTA92hn20yd9MqBGdp75wxXbCdgUR0X6naFFGzMm9xhivV\n\tPelQ==", "X-Gm-Message-State": "AHYfb5gtjciMRhwcSImga6kZPvYdl6npSVjdDuox3Re8JOcPTIU1taN+\n\t6KY1ecUx2RLnyJjv", "X-Received": "by 10.46.33.136 with SMTP id h8mr377364lji.70.1504081927296;\n\tWed, 30 Aug 2017 01:32:07 -0700 (PDT)", "From": "Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>", "To": "u-boot@lists.denx.de", "Date": "Wed, 30 Aug 2017 11:31:34 +0300", "Message-Id": "<20170830083135.9183-2-tuomas.tynkkynen@iki.fi>", "X-Mailer": "git-send-email 2.13.0", "In-Reply-To": "<20170830083135.9183-1-tuomas.tynkkynen@iki.fi>", "References": "<20170830083135.9183-1-tuomas.tynkkynen@iki.fi>", "X-Mailman-Approved-At": "Wed, 30 Aug 2017 16:44:19 +0000", "Cc": "Tom Rini <trini@konsulko.com>", "Subject": "[U-Boot] [PATCH 1/2] PCI: Add driver for a 'pci-host-ecam-generic'\n\thost controller", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "QEMU emulates such a device with '-machine virt,highmem=off' on ARM.\nThe 'highmem=off' part is required for things to work as the PCI code\nin U-Boot doesn't seem to support 64-bit BARs.\n\nThis driver is basically a copy-paste of the Xilinx PCIE driver with the\nXilinx-specific bits removed and compatible string changed... The\ngeneric code should probably be extracted into some sort of library\nfunctions instead of duplicating them before committing this driver.\n\nSigned-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>\n---\n drivers/pci/Kconfig | 8 ++\n drivers/pci/Makefile | 1 +\n drivers/pci/pcie_ecam_generic.c | 193 ++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 202 insertions(+)\n create mode 100644 drivers/pci/pcie_ecam_generic.c", "diff": "diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig\nindex e2a1c0a409..745161fb9f 100644\n--- a/drivers/pci/Kconfig\n+++ b/drivers/pci/Kconfig\n@@ -33,6 +33,14 @@ config PCI_PNP\n \thelp\n \t Enable PCI memory and I/O space resource allocation and assignment.\n \n+config PCIE_ECAM_GENERIC\n+\tbool \"Generic PCI-E ECAM support\"\n+\tdefault n\n+\tdepends on DM_PCI\n+\thelp\n+\t Say Y here if you want to enable support for generic ECAM-based\n+\t PCIe controllers, such as the one emulated by QEMU.\n+\n config PCIE_DW_MVEBU\n \tbool \"Enable Armada-8K PCIe driver (DesignWare core)\"\n \tdefault n\ndiff --git a/drivers/pci/Makefile b/drivers/pci/Makefile\nindex ad44e83996..5eb12efbf5 100644\n--- a/drivers/pci/Makefile\n+++ b/drivers/pci/Makefile\n@@ -17,6 +17,7 @@ obj-$(CONFIG_PCI) += pci.o pci_auto_old.o\n endif\n obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o\n \n+obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o\n obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o\n obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o\n obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o\ndiff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c\nnew file mode 100644\nindex 0000000000..039e378cb0\n--- /dev/null\n+++ b/drivers/pci/pcie_ecam_generic.c\n@@ -0,0 +1,193 @@\n+/*\n+ * Generic PCIE host provided by e.g. QEMU\n+ *\n+ * Heavily based on drivers/pci/pcie_xilinx.c\n+ *\n+ * Copyright (C) 2016 Imagination Technologies\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <pci.h>\n+\n+#include <asm/io.h>\n+\n+/**\n+ * struct generic_ecam_pcie - generic_ecam PCIe controller state\n+ * @hose: The parent classes PCI controller state\n+ * @cfg_base: The base address of memory mapped configuration space\n+ */\n+struct generic_ecam_pcie {\n+\tstruct pci_controller hose;\n+\tvoid *cfg_base;\n+};\n+\n+/**\n+ * pcie_generic_ecam_config_address() - Calculate the address of a config access\n+ * @pcie: Pointer to the PCI controller state\n+ * @bdf: Identifies the PCIe device to access\n+ * @offset: The offset into the device's configuration space\n+ * @paddress: Pointer to the pointer to write the calculates address to\n+ *\n+ * Calculates the address that should be accessed to perform a PCIe\n+ * configuration space access for a given device identified by the PCIe\n+ * controller device @pcie and the bus, device & function numbers in @bdf. If\n+ * access to the device is not valid then the function will return an error\n+ * code. Otherwise the address to access will be written to the pointer pointed\n+ * to by @paddress.\n+ *\n+ * Return: 0 on success, else -ENODEV\n+ */\n+static int pcie_generic_ecam_config_address(struct generic_ecam_pcie *pcie, pci_dev_t bdf,\n+\t\t\t\t uint offset, void **paddress)\n+{\n+\tunsigned int bus = PCI_BUS(bdf);\n+\tunsigned int dev = PCI_DEV(bdf);\n+\tunsigned int func = PCI_FUNC(bdf);\n+\tvoid *addr;\n+\n+\taddr = pcie->cfg_base;\n+\taddr += bus << 20;\n+\taddr += dev << 15;\n+\taddr += func << 12;\n+\taddr += offset;\n+\t*paddress = addr;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * pcie_generic_ecam_read_config() - Read from configuration space\n+ * @pcie: Pointer to the PCI controller state\n+ * @bdf: Identifies the PCIe device to access\n+ * @offset: The offset into the device's configuration space\n+ * @valuep: A pointer at which to store the read value\n+ * @size: Indicates the size of access to perform\n+ *\n+ * Read a value of size @size from offset @offset within the configuration\n+ * space of the device identified by the bus, device & function numbers in @bdf\n+ * on the PCI bus @bus.\n+ *\n+ * Return: 0 on success, else -ENODEV or -EINVAL\n+ */\n+static int pcie_generic_ecam_read_config(struct udevice *bus, pci_dev_t bdf,\n+\t\t\t\t uint offset, ulong *valuep,\n+\t\t\t\t enum pci_size_t size)\n+{\n+\tstruct generic_ecam_pcie *pcie = dev_get_priv(bus);\n+\tvoid *address;\n+\tint err;\n+\n+\terr = pcie_generic_ecam_config_address(pcie, bdf, offset, &address);\n+\tif (err < 0) {\n+\t\t*valuep = pci_get_ff(size);\n+\t\treturn 0;\n+\t}\n+\n+\tswitch (size) {\n+\tcase PCI_SIZE_8:\n+\t\t*valuep = __raw_readb(address);\n+\t\treturn 0;\n+\tcase PCI_SIZE_16:\n+\t\t*valuep = __raw_readw(address);\n+\t\treturn 0;\n+\tcase PCI_SIZE_32:\n+\t\t*valuep = __raw_readl(address);\n+\t\treturn 0;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+/**\n+ * pcie_generic_ecam_write_config() - Write to configuration space\n+ * @pcie: Pointer to the PCI controller state\n+ * @bdf: Identifies the PCIe device to access\n+ * @offset: The offset into the device's configuration space\n+ * @value: The value to write\n+ * @size: Indicates the size of access to perform\n+ *\n+ * Write the value @value of size @size from offset @offset within the\n+ * configuration space of the device identified by the bus, device & function\n+ * numbers in @bdf on the PCI bus @bus.\n+ *\n+ * Return: 0 on success, else -ENODEV or -EINVAL\n+ */\n+static int pcie_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf,\n+\t\t\t\t uint offset, ulong value,\n+\t\t\t\t enum pci_size_t size)\n+{\n+\tstruct generic_ecam_pcie *pcie = dev_get_priv(bus);\n+\tvoid *address;\n+\tint err;\n+\n+\terr = pcie_generic_ecam_config_address(pcie, bdf, offset, &address);\n+\tif (err < 0)\n+\t\treturn 0;\n+\n+\tswitch (size) {\n+\tcase PCI_SIZE_8:\n+\t\t__raw_writeb(value, address);\n+\t\treturn 0;\n+\tcase PCI_SIZE_16:\n+\t\t__raw_writew(value, address);\n+\t\treturn 0;\n+\tcase PCI_SIZE_32:\n+\t\t__raw_writel(value, address);\n+\t\treturn 0;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+/**\n+ * pcie_generic_ecam_ofdata_to_platdata() - Translate from DT to device state\n+ * @dev: A pointer to the device being operated on\n+ *\n+ * Translate relevant data from the device tree pertaining to device @dev into\n+ * state that the driver will later make use of. This state is stored in the\n+ * device's private data structure.\n+ *\n+ * Return: 0 on success, else -EINVAL\n+ */\n+static int pcie_generic_ecam_ofdata_to_platdata(struct udevice *dev)\n+{\n+\tstruct generic_ecam_pcie *pcie = dev_get_priv(dev);\n+\tstruct fdt_resource reg_res;\n+\tDECLARE_GLOBAL_DATA_PTR;\n+\tint err;\n+\n+\terr = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), \"reg\",\n+\t\t\t 0, ®_res);\n+\tif (err < 0) {\n+\t\terror(\"\\\"reg\\\" resource not found\\n\");\n+\t\treturn err;\n+\t}\n+\n+\tpcie->cfg_base = map_physmem(reg_res.start,\n+\t\t\t\t fdt_resource_size(®_res),\n+\t\t\t\t MAP_NOCACHE);\n+\n+\treturn 0;\n+}\n+\n+static const struct dm_pci_ops pcie_generic_ecam_ops = {\n+\t.read_config\t= pcie_generic_ecam_read_config,\n+\t.write_config\t= pcie_generic_ecam_write_config,\n+};\n+\n+static const struct udevice_id pcie_generic_ecam_ids[] = {\n+\t{ .compatible = \"pci-host-ecam-generic\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(pcie_generic_ecam) = {\n+\t.name\t\t\t= \"pcie_generic_ecam\",\n+\t.id\t\t\t= UCLASS_PCI,\n+\t.of_match\t\t= pcie_generic_ecam_ids,\n+\t.ops\t\t\t= &pcie_generic_ecam_ops,\n+\t.ofdata_to_platdata\t= pcie_generic_ecam_ofdata_to_platdata,\n+\t.priv_auto_alloc_size\t= sizeof(struct generic_ecam_pcie),\n+};\n", "prefixes": [ "U-Boot", "1/2" ] }