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GET /api/patches/807674/?format=api
{ "id": 807674, "url": "http://patchwork.ozlabs.org/api/patches/807674/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504106024-23569-6-git-send-email-sricharan@codeaurora.org/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504106024-23569-6-git-send-email-sricharan@codeaurora.org>", "list_archive_url": null, "date": "2017-08-30T15:13:43", "name": "[v2,5/6] remoteproc: qcom: Add support for q6v5-wcss pil", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d8fa3d975a25384d4e9bed2c0a8a6a29d66b0ae5", "submitter": { "id": 65960, "url": "http://patchwork.ozlabs.org/api/people/65960/?format=api", "name": "Sricharan Ramabadhran", "email": "sricharan@codeaurora.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504106024-23569-6-git-send-email-sricharan@codeaurora.org/mbox/", "series": [ { "id": 634, "url": "http://patchwork.ozlabs.org/api/series/634/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=634", "date": "2017-08-30T15:13:38", "name": "Add support for Hexagon q6v5-wcss integrated core", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/634/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807674/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807674/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"MBi8kgfB\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"ASjgKMGb\"; \n\tdkim-atps=neutral", "pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org", "pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sricharan@codeaurora.org" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj8Dt4S2yz9sN7\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 31 Aug 2017 01:14:38 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751826AbdH3POY (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tWed, 30 Aug 2017 11:14:24 -0400", "from smtp.codeaurora.org ([198.145.29.96]:49026 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751816AbdH3POU (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Wed, 30 Aug 2017 11:14:20 -0400", "by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 8F61960768; Wed, 30 Aug 2017 15:14:19 +0000 (UTC)", "from srichara-linux.qualcomm.com\n\t(blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com\n\t[103.229.19.19])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: sricharan@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 75B8F60768;\n\tWed, 30 Aug 2017 15:14:13 +0000 (UTC)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1504106059;\n\tbh=iwu1Rn/2EsBI1ioLg90IBHs3ee9z24BCrEkY8CstYFM=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=MBi8kgfBFjZvkn4oTIQxEzQVyCr+U3t0ccPJu713l9qrFREsaEOrrPbrh5GHId6Zy\n\ttycYnXAS98VvfBPuXUyMiCf8Gep1NqbrgmCf6QsjPZwlNRHizUGdf5drdh1eQtERS3\n\tyKmgoY0Z2xGeUvshvYogBGvyVz5rRgAMY6YH3st0=", "v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1504106057;\n\tbh=iwu1Rn/2EsBI1ioLg90IBHs3ee9z24BCrEkY8CstYFM=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=ASjgKMGbRuOP8kK35EylRWSfNsdeZsgWSdYyzqlJ5G34LhcAhb4AqrGfSMNuFey1W\n\tG53m5O68xNaZ04DMaYQoKjd82AAn6a4VDuxYnWRZ7JuehLHKO088FHwJP12WniIOdh\n\tibBV31L4cFKZ49ibCmNZXXCABWiw4dFFvh57T614=" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0", "DMARC-Filter": "OpenDMARC Filter v1.3.2 smtp.codeaurora.org 75B8F60768", "From": "Sricharan R <sricharan@codeaurora.org>", "To": "bjorn.andersson@linaro.org, ohad@wizery.com, robh+dt@kernel.org,\n\tmark.rutland@arm.com, andy.gross@linaro.org,\n\tdavid.brown@linaro.org, linux-remoteproc@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org", "Cc": "sricharan@codeaurora.org", "Subject": "[PATCH v2 5/6] remoteproc: qcom: Add support for q6v5-wcss pil", "Date": "Wed, 30 Aug 2017 20:43:43 +0530", "Message-Id": "<1504106024-23569-6-git-send-email-sricharan@codeaurora.org>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1504106024-23569-1-git-send-email-sricharan@codeaurora.org>", "References": "<1504106024-23569-1-git-send-email-sricharan@codeaurora.org>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "IPQ8074 has an integrated Hexagon dsp core q6v5 and a wireless lan\n(Lithium) IP. An mdt type single image format is used for the\nfirmware. So the mdt_load function can be directly used to load\nthe firmware. Also add the relevant resets required for this core.\n\nSigned-off-by: Sricharan R <sricharan@codeaurora.org>\n---\n .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 ++-\n drivers/remoteproc/qcom_q6v5_pil.c | 53 +++++++++++++++++++++-\n 2 files changed, 58 insertions(+), 2 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt\nindex 87a8e51..a0a9ad3 100644\n--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt\n+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt\n@@ -12,6 +12,7 @@ on the Qualcomm Hexagon core.\n \t\t \"qcom,msm8974-mss-pil\"\n \n \t\t \"qcom,msm8996-mss-pil\"\n+\t\t \"qcom,ipq8074-wcss-pil\"\n - reg:\n \tUsage: required\n \tValue type: <prop-encoded-array>\n@@ -49,11 +50,15 @@ on the Qualcomm Hexagon core.\n \tUsage: required\n \tValue type: <phandle>\n \tDefinition: reference to the reset-controller for the modem sub-system\n+\t\t reference to the list of 3 reset-controllers for the\n+\t\t wcss sub-system\n \n - reset-names:\n \tUsage: required\n \tValue type: <stringlist>\n-\tDefinition: must be \"mss_restart\"\n+\tDefinition: must be \"mss_restart\" for the modem sub-system\n+\tDefinition: must be \"wcss_aon_reset\", \"wcss_reset\", \"wcss_q6_reset\"\n+\t\t for the wcss syb-system\n \n - cx-supply:\n - mss-supply:\ndiff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c\nindex 232134c..8da1cc7 100644\n--- a/drivers/remoteproc/qcom_q6v5_pil.c\n+++ b/drivers/remoteproc/qcom_q6v5_pil.c\n@@ -129,6 +129,9 @@ struct q6v5 {\n \tu32 halt_nc;\n \n \tstruct reset_control *mss_restart;\n+\tstruct reset_control *wcss_aon_reset;\n+\tstruct reset_control *wcss_reset;\n+\tstruct reset_control *wcss_q6_reset;\n \n \tstruct qcom_smem_state *state;\n \tunsigned stop_bit;\n@@ -178,6 +181,7 @@ enum {\n \tMSS_MSM8916,\n \tMSS_MSM8974,\n \tMSS_MSM8996,\n+\tWCSS_IPQ8074,\n };\n \n static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,\n@@ -356,6 +360,21 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)\n \treturn 0;\n }\n \n+static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)\n+{\n+\tstruct q6v5 *qproc = rproc->priv;\n+\n+\treturn qcom_mdt_load_no_init(qproc->dev, fw, rproc->firmware,\n+\t\t\t\t 0, qproc->mba_region, qproc->mba_phys,\n+\t\t\t\t qproc->mba_size);\n+}\n+\n+static const struct rproc_fw_ops q6v5_wcss_fw_ops = {\n+\t.find_rsc_table = q6v5_find_rsc_table,\n+\t.load = q6v5_wcss_load,\n+\t.get_boot_addr = rproc_elf_get_boot_addr,\n+};\n+\n static const struct rproc_fw_ops q6v5_fw_ops = {\n \t.find_rsc_table = q6v5_find_rsc_table,\n \t.load = q6v5_load,\n@@ -1055,6 +1074,26 @@ static int q6v5_init_clocks(struct device *dev, struct clk **clks,\n \treturn i;\n }\n \n+static int q6v5_wcss_init_reset(struct q6v5 *qproc)\n+{\n+\tqproc->wcss_aon_reset = devm_reset_control_get(qproc->dev,\n+\t\t\t\t\t\t \"wcss_aon_reset\");\n+\tif (IS_ERR(qproc->wcss_aon_reset))\n+\t\treturn PTR_ERR(qproc->wcss_aon_reset);\n+\n+\tqproc->wcss_reset = devm_reset_control_get(qproc->dev,\n+\t\t\t\t\t\t \"wcss_reset\");\n+\tif (IS_ERR(qproc->wcss_reset))\n+\t\treturn PTR_ERR(qproc->wcss_reset);\n+\n+\tqproc->wcss_q6_reset = devm_reset_control_get(qproc->dev,\n+\t\t\t\t\t\t \"wcss_q6_reset\");\n+\tif (IS_ERR(qproc->wcss_q6_reset))\n+\t\treturn PTR_ERR(qproc->wcss_q6_reset);\n+\n+\treturn 0;\n+}\n+\n static int q6v5_init_reset(struct q6v5 *qproc)\n {\n \tqproc->mss_restart = devm_reset_control_get(qproc->dev, NULL);\n@@ -1113,6 +1152,9 @@ static int q6v5_alloc_memory_region(struct q6v5 *qproc)\n \t\treturn -EBUSY;\n \t}\n \n+\tif (qproc->version == WCSS_IPQ8074)\n+\t\treturn 0;\n+\n \tchild = of_get_child_by_name(qproc->dev->of_node, \"mpss\");\n \tnode = of_parse_phandle(child, \"memory-region\", 0);\n \tret = of_address_to_resource(node, 0, &r);\n@@ -1156,6 +1198,7 @@ static int q6v5_probe(struct platform_device *pdev)\n \tqproc = (struct q6v5 *)rproc->priv;\n \tqproc->dev = &pdev->dev;\n \tqproc->rproc = rproc;\n+\tqproc->version = desc->version;\n \tplatform_set_drvdata(pdev, qproc);\n \n \tinit_completion(&qproc->start_done);\n@@ -1205,7 +1248,6 @@ static int q6v5_probe(struct platform_device *pdev)\n \tif (ret)\n \t\tgoto free_rproc;\n \n-\tqproc->version = desc->version;\n \tqproc->need_mem_protection = desc->need_mem_protection;\n \tret = q6v5_request_irq(qproc, pdev, \"wdog\", q6v5_wdog_interrupt);\n \tif (ret < 0)\n@@ -1352,11 +1394,20 @@ static int q6v5_remove(struct platform_device *pdev)\n \t.ops = &q6v5_ops,\n };\n \n+static const struct rproc_hexagon_res ipq8074_wcss = {\n+\t.hexagon_mba_image = \"IPQ8074/q6_fw.mdt\",\n+\t.need_mem_protection = false,\n+\t.version = WCSS_IPQ8074,\n+\t.init_reset = q6v5_wcss_init_reset,\n+\t.fw_ops = &q6v5_wcss_fw_ops,\n+};\n+\n static const struct of_device_id q6v5_of_match[] = {\n \t{ .compatible = \"qcom,q6v5-pil\", .data = &msm8916_mss},\n \t{ .compatible = \"qcom,msm8916-mss-pil\", .data = &msm8916_mss},\n \t{ .compatible = \"qcom,msm8974-mss-pil\", .data = &msm8974_mss},\n \t{ .compatible = \"qcom,msm8996-mss-pil\", .data = &msm8996_mss},\n+\t{ .compatible = \"qcom,ipq8074-wcss-pil\", .data = &ipq8074_wcss},\n \t{ },\n };\n MODULE_DEVICE_TABLE(of, q6v5_of_match);\n", "prefixes": [ "v2", "5/6" ] }