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GET /api/patches/807671/?format=api
{ "id": 807671, "url": "http://patchwork.ozlabs.org/api/patches/807671/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170830150459.67452-2-andriy.shevchenko@linux.intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170830150459.67452-2-andriy.shevchenko@linux.intel.com>", "list_archive_url": null, "date": "2017-08-30T15:04:58", "name": "[U-Boot,v1,1/2] x86: tangier: Enable ACPI support for Intel Tangier", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "b3e12c8fa558e9e6951e6bd72687ebfe6e42c377", "submitter": { "id": 8583, "url": "http://patchwork.ozlabs.org/api/people/8583/?format=api", "name": "Andy Shevchenko", "email": "andriy.shevchenko@linux.intel.com" }, "delegate": { "id": 56520, "url": "http://patchwork.ozlabs.org/api/users/56520/?format=api", "username": "bmeng", "first_name": "Bin", "last_name": "Meng", "email": "bmeng.cn@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170830150459.67452-2-andriy.shevchenko@linux.intel.com/mbox/", "series": [ { "id": 633, "url": "http://patchwork.ozlabs.org/api/series/633/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=633", "date": "2017-08-30T15:04:59", "name": "edison: Enable ACPI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/633/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807671/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807671/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj83y0nRfz9sN7\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 31 Aug 2017 01:06:54 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid C703CC22967; Wed, 30 Aug 2017 15:06:20 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id DAD8CC2295B;\n\tWed, 30 Aug 2017 15:06:15 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid B6332C22297; Wed, 30 Aug 2017 15:05:51 +0000 (UTC)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby lists.denx.de (Postfix) with ESMTPS id E141DC228D7\n\tfor <u-boot@lists.denx.de>; Wed, 30 Aug 2017 15:05:47 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t30 Aug 2017 08:05:04 -0700", "from black.fi.intel.com ([10.237.72.28])\n\tby fmsmga002.fm.intel.com with ESMTP; 30 Aug 2017 08:05:00 -0700", "by black.fi.intel.com (Postfix, from userid 1003)\n\tid 0B09B4B; Wed, 30 Aug 2017 18:04:59 +0300 (EEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.41,448,1498546800\"; d=\"scan'208\";\n\ta=\"1212544797\"", "From": "Andy Shevchenko <andriy.shevchenko@linux.intel.com>", "To": "Bin Meng <bmeng.cn@gmail.com>, U-Boot Mailing List <u-boot@lists.denx.de>,\n\tSimon Glass <sjg@chromium.org>, Stefan Roese <sr@denx.de>,\n\tFerry Toth <ftoth@telfort.nl>", "Date": "Wed, 30 Aug 2017 18:04:58 +0300", "Message-Id": "<20170830150459.67452-2-andriy.shevchenko@linux.intel.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170830150459.67452-1-andriy.shevchenko@linux.intel.com>", "References": "<20170830150459.67452-1-andriy.shevchenko@linux.intel.com>", "Cc": "Andy Shevchenko <andriy.shevchenko@linux.intel.com>", "Subject": "[U-Boot] [PATCH v1 1/2] x86: tangier: Enable ACPI support for Intel\n\tTangier", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Intel Tangier SoC is a part of Intel Merrifield platform which doesn't\nutilize ACPI by default. Here is an attempt to unleash ACPI flexibility\npower on Intel Merrifield based platforms.\n\nThe change brings minimum support of the devices that found on\nIntel Merrifield based end user device.\n\nSigned-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>\n---\n arch/x86/cpu/tangier/Makefile | 1 +\n arch/x86/cpu/tangier/acpi.c | 86 ++++++\n .../include/asm/arch-tangier/acpi/global_nvs.asl | 16 ++\n .../x86/include/asm/arch-tangier/acpi/platform.asl | 31 +++\n .../include/asm/arch-tangier/acpi/southcluster.asl | 306 +++++++++++++++++++++\n arch/x86/include/asm/arch-tangier/global_nvs.h | 22 ++\n 6 files changed, 462 insertions(+)\n create mode 100644 arch/x86/cpu/tangier/acpi.c\n create mode 100644 arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl\n create mode 100644 arch/x86/include/asm/arch-tangier/acpi/platform.asl\n create mode 100644 arch/x86/include/asm/arch-tangier/acpi/southcluster.asl\n create mode 100644 arch/x86/include/asm/arch-tangier/global_nvs.h", "diff": "diff --git a/arch/x86/cpu/tangier/Makefile b/arch/x86/cpu/tangier/Makefile\nindex d146b3f5c2..92cfa555ed 100644\n--- a/arch/x86/cpu/tangier/Makefile\n+++ b/arch/x86/cpu/tangier/Makefile\n@@ -5,3 +5,4 @@\n #\n \n obj-y += car.o tangier.o sdram.o\n+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o\ndiff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c\nnew file mode 100644\nindex 0000000000..fb15ce40ad\n--- /dev/null\n+++ b/arch/x86/cpu/tangier/acpi.c\n@@ -0,0 +1,86 @@\n+/*\n+ * Copyright (c) 2017 Intel Corporation\n+ *\n+ * Partially based on acpi.c for other x86 platforms\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <cpu.h>\n+#include <dm.h>\n+#include <dm/uclass-internal.h>\n+#include <asm/acpi_table.h>\n+#include <asm/ioapic.h>\n+#include <asm/mpspec.h>\n+#include <asm/tables.h>\n+#include <asm/arch/global_nvs.h>\n+\n+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,\n+\t\t void *dsdt)\n+{\n+\tstruct acpi_table_header *header = &(fadt->header);\n+\n+\tmemset((void *)fadt, 0, sizeof(struct acpi_fadt));\n+\n+\tacpi_fill_header(header, \"FACP\");\n+\theader->length = sizeof(struct acpi_fadt);\n+\theader->revision = 6;\n+\n+\tfadt->firmware_ctrl = (u32)facs;\n+\tfadt->dsdt = (u32)dsdt;\n+\tfadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;\n+\n+\tfadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT |\n+\t\t\t ACPI_FADT_NO_PCIE_ASPM_CONTROL;\n+\tfadt->flags =\n+\t\tACPI_FADT_WBINVD |\n+\t\tACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON |\n+\t\tACPI_FADT_SEALED_CASE | ACPI_FADT_HEADLESS |\n+\t\tACPI_FADT_HW_REDUCED_ACPI;\n+\n+\tfadt->minor_revision = 2;\n+\n+\tfadt->x_firmware_ctl_l = (u32)facs;\n+\tfadt->x_firmware_ctl_h = 0;\n+\tfadt->x_dsdt_l = (u32)dsdt;\n+\tfadt->x_dsdt_h = 0;\n+\n+\theader->checksum = table_compute_checksum(fadt, header->length);\n+}\n+\n+u32 acpi_fill_madt(u32 current)\n+{\n+\tcurrent += acpi_create_madt_lapics(current);\n+\n+\tcurrent += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,\n+\t\t\tio_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);\n+\n+\treturn current;\n+}\n+\n+u32 acpi_fill_mcfg(u32 current)\n+{\n+\tcurrent += acpi_create_mcfg_mmconfig\n+\t\t((struct acpi_mcfg_mmconfig *)current,\n+\t\t0x3f500000, 0x0, 0x0, 0x0);\n+\n+\treturn current;\n+}\n+\n+void acpi_create_gnvs(struct acpi_global_nvs *gnvs)\n+{\n+\tstruct udevice *dev;\n+\tint ret;\n+\n+\t/* at least we have one processor */\n+\tgnvs->pcnt = 1;\n+\n+\t/* override the processor count with actual number */\n+\tret = uclass_find_first_device(UCLASS_CPU, &dev);\n+\tif (ret == 0 && dev != NULL) {\n+\t\tret = cpu_get_count(dev);\n+\t\tif (ret > 0)\n+\t\t\tgnvs->pcnt = ret;\n+\t}\n+}\ndiff --git a/arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl b/arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl\nnew file mode 100644\nindex 0000000000..84fffbe140\n--- /dev/null\n+++ b/arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl\n@@ -0,0 +1,16 @@\n+/*\n+ * Copyright (c) 2017 Intel Corporation\n+ *\n+ * Partially based on global_nvs.asl for other x86 platforms\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm/acpi/global_nvs.h>\n+\n+OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)\n+Field(GNVS, ByteAcc, NoLock, Preserve)\n+{\n+ Offset (0x00),\n+ PCNT, 2, /* processor count */\n+}\ndiff --git a/arch/x86/include/asm/arch-tangier/acpi/platform.asl b/arch/x86/include/asm/arch-tangier/acpi/platform.asl\nnew file mode 100644\nindex 0000000000..a57b7cb319\n--- /dev/null\n+++ b/arch/x86/include/asm/arch-tangier/acpi/platform.asl\n@@ -0,0 +1,31 @@\n+/*\n+ * Copyright (c) 2017 Intel Corporation\n+ *\n+ * Partially based on platform.asl for other x86 platforms\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm/acpi/statdef.asl>\n+\n+/*\n+ * The _PTS method (Prepare To Sleep) is called before the OS is\n+ * entering a sleep state. The sleep state number is passed in Arg0.\n+ */\n+Method(_PTS, 1)\n+{\n+}\n+\n+/* The _WAK method is called on system wakeup */\n+Method(_WAK, 1)\n+{\n+ Return (Package() {0, 0})\n+}\n+\n+/* ACPI global NVS */\n+#include \"global_nvs.asl\"\n+\n+Scope (\\_SB)\n+{\n+ #include \"southcluster.asl\"\n+}\ndiff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl\nnew file mode 100644\nindex 0000000000..d3a9b114cb\n--- /dev/null\n+++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl\n@@ -0,0 +1,306 @@\n+/*\n+ * Copyright (c) 2017 Intel Corporation\n+ *\n+ * Partially based on southcluster.asl for other x86 platforms\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+Device (PCI0)\n+{\n+ Name (_HID, EISAID(\"PNP0A08\")) /* PCIe */\n+ Name (_CID, EISAID(\"PNP0A03\")) /* PCI */\n+\n+ Name (_ADR, 0)\n+ Name (_BBN, 0)\n+\n+ Name (MCRS, ResourceTemplate()\n+ {\n+ /* Bus Numbers */\n+ WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,\n+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)\n+\n+ /* IO Region 0 */\n+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,\n+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)\n+\n+ /* PCI Config Space */\n+ IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)\n+\n+ /* IO Region 1 */\n+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,\n+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)\n+\n+ /* GPIO Low Memory Region */\n+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,\n+ Cacheable, ReadWrite,\n+ 0x00000000, 0x000ddcc0, 0x000ddccf, 0x00000000,\n+ 0x00000010, , , GP00)\n+\n+ /* PSH Memory Region 0 */\n+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,\n+ Cacheable, ReadWrite,\n+ 0x00000000, 0x04819000, 0x04898fff, 0x00000000,\n+ 0x00080000, , , PSH0)\n+\n+ /* PSH Memory Region 1 */\n+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,\n+ Cacheable, ReadWrite,\n+ 0x00000000, 0x04919000, 0x04920fff, 0x00000000,\n+ 0x00008000, , , PSH1)\n+\n+ /* SST Memory Region */\n+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,\n+ Cacheable, ReadWrite,\n+ 0x00000000, 0x05e00000, 0x05ffffff, 0x00000000,\n+ 0x00200000, , , SST0)\n+\n+ /* PCI Memory Region */\n+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,\n+ Cacheable, ReadWrite,\n+ 0x00000000, 0x80000000, 0xffffffff, 0x00000000,\n+ 0x80000000, , , PMEM)\n+ })\n+\n+ Method (_CRS, 0, Serialized)\n+ {\n+ Return (MCRS)\n+ }\n+\n+ Method (_OSC, 4)\n+ {\n+ /* Check for proper GUID */\n+ If (LEqual(Arg0, ToUUID(\"33db4d5b-1ff7-401c-9657-7441c03dd766\"))) {\n+ /* Let OS control everything */\n+ Return (Arg3)\n+ } Else {\n+ /* Unrecognized UUID */\n+ CreateDWordField(Arg3, 0, CDW1)\n+ Or(CDW1, 4, CDW1)\n+ Return (Arg3)\n+ }\n+ }\n+\n+ Device (SDHC)\n+ {\n+ Name (_ADR, 0x00010003)\n+ Name (_DEP, Package (0x01)\n+ {\n+ GPIO\n+ })\n+ Name (PSTS, Zero)\n+\n+ Method (_STA)\n+ {\n+ Return (STA_VISIBLE)\n+ }\n+\n+ Method (_PS3, 0, NotSerialized)\n+ {\n+ }\n+\n+ Method (_PS0, 0, NotSerialized)\n+ {\n+ If (PSTS == Zero)\n+ {\n+ If (^^GPIO.AVBL == One)\n+ {\n+ ^^GPIO.WFD3 = One\n+ PSTS = One\n+ }\n+ }\n+ }\n+\n+ /* BCM43340 */\n+ Device (BRC1)\n+ {\n+ Name (_ADR, One)\n+ Name (_DEP, Package (0x01)\n+ {\n+ GPIO\n+ })\n+\n+ Method (_STA)\n+ {\n+ Return (STA_VISIBLE)\n+ }\n+\n+ Method (_RMV, 0, NotSerialized)\n+ {\n+ Return (Zero)\n+ }\n+\n+ Method (_PS3, 0, NotSerialized)\n+ {\n+ If (^^^GPIO.AVBL == One)\n+ {\n+ ^^^GPIO.WFD3 = Zero\n+ PSTS = Zero\n+ }\n+ }\n+\n+ Method (_PS0, 0, NotSerialized)\n+ {\n+ If (PSTS == Zero)\n+ {\n+ If (^^^GPIO.AVBL == One)\n+ {\n+ ^^^GPIO.WFD3 = One\n+ PSTS = One\n+ }\n+ }\n+ }\n+ }\n+\n+ Device (BRC2)\n+ {\n+ Name (_ADR, 0x02)\n+ Method (_STA, 0, NotSerialized)\n+ {\n+ Return (STA_VISIBLE)\n+ }\n+\n+ Method (_RMV, 0, NotSerialized)\n+ {\n+ Return (Zero)\n+ }\n+ }\n+ }\n+\n+ Device (SPI5)\n+ {\n+ Name (_ADR, 0x00070001)\n+ Name (_DEP, Package (0x01)\n+ {\n+ GPIO\n+ })\n+ Name (RBUF, ResourceTemplate()\n+ {\n+ GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,\n+ \"\\\\_SB.PCI0.GPIO\", 0, ResourceConsumer, , ) { 91 }\n+ GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,\n+ \"\\\\_SB.PCI0.GPIO\", 0, ResourceConsumer, , ) { 92 }\n+ GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,\n+ \"\\\\_SB.PCI0.GPIO\", 0, ResourceConsumer, , ) { 93 }\n+ GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,\n+ \"\\\\_SB.PCI0.GPIO\", 0, ResourceConsumer, , ) { 94 }\n+ })\n+\n+ Method (_CRS, 0, NotSerialized)\n+ {\n+ Return (RBUF)\n+ }\n+\n+ /*\n+ * See\n+ * http://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt\n+ * for more information about GPIO bindings.\n+ */\n+ Name (_DSD, Package () {\n+ ToUUID(\"daffd814-6eba-4d8c-8a91-bc9bbf4aa301\"),\n+ Package () {\n+ Package () {\n+ \"cs-gpios\", Package () {\n+ ^SPI5, 0, 0, 0,\n+ ^SPI5, 1, 0, 0,\n+ ^SPI5, 2, 0, 0,\n+ ^SPI5, 3, 0, 0,\n+ },\n+ },\n+ }\n+ })\n+\n+ Method (_STA, 0, NotSerialized)\n+ {\n+ Return (STA_VISIBLE)\n+ }\n+ }\n+\n+ Device (I2C1)\n+ {\n+ Name (_ADR, 0x00080000)\n+\n+ Method (_STA, 0, NotSerialized)\n+ {\n+ Return (STA_VISIBLE)\n+ }\n+ }\n+\n+ Device (GPIO)\n+ {\n+ Name (_ADR, 0x000c0000)\n+ Name (_DEP, Package (0x01)\n+ {\n+ \\_SB.FLIS\n+ })\n+\n+ Method (_STA)\n+ {\n+ Return (STA_VISIBLE)\n+ }\n+\n+ Name (AVBL, Zero)\n+ Method (_REG, 2, NotSerialized)\n+ {\n+ If (Arg0 == 0x08)\n+ {\n+ AVBL = Arg1\n+ }\n+ }\n+\n+ OperationRegion (GPOP, GeneralPurposeIo, Zero, 0x04)\n+ Field (GPOP, ByteAcc, NoLock, Preserve)\n+ {\n+ Connection (\n+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,\n+ \"\\\\_SB.PCI0.GPIO\", 0, ResourceConsumer, , ) { 56 }\n+ ),\n+ WFD3, 1,\n+ }\n+ }\n+\n+ Device (PWM0)\n+ {\n+ Name (_ADR, 0x00170000)\n+\n+ Method (_STA, 0, NotSerialized)\n+ {\n+ Return (STA_VISIBLE)\n+ }\n+ }\n+}\n+\n+Device (FLIS)\n+{\n+ Name (_HID, \"PRP0001\")\n+ Name (_DDN, \"Intel Merrifield Family-Level Interface Shim\")\n+ Name (RBUF, ResourceTemplate()\n+ {\n+ Memory32Fixed(ReadWrite, 0xFF0C0000, 0x00008000, )\n+ PinGroup(\"spi5\", ResourceProducer, ) { 90, 91, 92, 93, 94, 95, 96 }\n+ PinGroup(\"uart0\", ResourceProducer, ) { 115, 116, 117, 118 }\n+ PinGroup(\"uart1\", ResourceProducer, ) { 119, 120, 121, 122 }\n+ PinGroup(\"uart2\", ResourceProducer, ) { 123, 124, 125, 126 }\n+ PinGroup(\"pwm0\", ResourceProducer, ) { 144 }\n+ PinGroup(\"pwm1\", ResourceProducer, ) { 145 }\n+ PinGroup(\"pwm2\", ResourceProducer, ) { 132 }\n+ PinGroup(\"pwm3\", ResourceProducer, ) { 133 }\n+ })\n+\n+ Method (_CRS, 0, NotSerialized)\n+ {\n+ Return (RBUF)\n+ }\n+\n+ Name (_DSD, Package () {\n+ ToUUID(\"daffd814-6eba-4d8c-8a91-bc9bbf4aa301\"),\n+ Package () {\n+ Package () {\"compatible\", Package () {\"intel,merrifield-pinctrl\"}},\n+ }\n+ })\n+\n+ Method (_STA, 0, NotSerialized)\n+ {\n+ Return (STA_VISIBLE)\n+ }\n+}\ndiff --git a/arch/x86/include/asm/arch-tangier/global_nvs.h b/arch/x86/include/asm/arch-tangier/global_nvs.h\nnew file mode 100644\nindex 0000000000..8ab5cf2aa2\n--- /dev/null\n+++ b/arch/x86/include/asm/arch-tangier/global_nvs.h\n@@ -0,0 +1,22 @@\n+/*\n+ * Copyright (c) 2017 Intel Corporation\n+ *\n+ * Partially based on global_nvs.h for other x86 platforms\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef _GLOBAL_NVS_H_\n+#define _GLOBAL_NVS_H_\n+\n+struct __packed acpi_global_nvs {\n+\tu8\tpcnt;\t\t/* processor count */\n+\n+\t/*\n+\t * Add padding so sizeof(struct acpi_global_nvs) == 0x100.\n+\t * This must match the size defined in the global_nvs.asl.\n+\t */\n+\tu8\trsvd[255];\n+};\n+\n+#endif /* _GLOBAL_NVS_H_ */\n", "prefixes": [ "U-Boot", "v1", "1/2" ] }